1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
70 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addPreserved<AliasAnalysis>();
74 // LiveVariables isn't really required by this analysis, it is only required
75 // here to make sure it is live during TwoAddressInstructionPass and
76 // PHIElimination. This is temporary.
77 AU.addRequired<LiveVariables>();
78 AU.addPreserved<LiveVariables>();
79 AU.addPreservedID(MachineLoopInfoID);
80 AU.addRequiredTransitiveID(MachineDominatorsID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreserved<SlotIndexes>();
83 AU.addRequiredTransitive<SlotIndexes>();
84 MachineFunctionPass::getAnalysisUsage(AU);
87 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
88 DomTree(nullptr), LRCalc(nullptr) {
89 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
92 LiveIntervals::~LiveIntervals() {
96 void LiveIntervals::releaseMemory() {
97 // Free the live intervals themselves.
98 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
99 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
100 VirtRegIntervals.clear();
101 RegMaskSlots.clear();
103 RegMaskBlocks.clear();
105 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
106 delete RegUnitRanges[i];
107 RegUnitRanges.clear();
109 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
110 VNInfoAllocator.Reset();
113 /// runOnMachineFunction - calculates LiveIntervals
115 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
117 MRI = &MF->getRegInfo();
118 TRI = MF->getSubtarget().getRegisterInfo();
119 TII = MF->getSubtarget().getInstrInfo();
120 AA = &getAnalysis<AliasAnalysis>();
121 Indexes = &getAnalysis<SlotIndexes>();
122 DomTree = &getAnalysis<MachineDominatorTree>();
124 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
125 MRI->enableSubRegLiveness(true);
128 LRCalc = new LiveRangeCalc();
130 // Allocate space for all virtual registers.
131 VirtRegIntervals.resize(MRI->getNumVirtRegs());
135 computeLiveInRegUnits();
137 if (EnablePrecomputePhysRegs) {
138 // For stress testing, precompute live ranges of all physical register
139 // units, including reserved registers.
140 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
147 /// print - Implement the dump method.
148 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
149 OS << "********** INTERVALS **********\n";
151 // Dump the regunits.
152 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
153 if (LiveRange *LR = RegUnitRanges[i])
154 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
156 // Dump the virtregs.
157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
158 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
159 if (hasInterval(Reg))
160 OS << getInterval(Reg) << '\n';
164 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
165 OS << ' ' << RegMaskSlots[i];
171 void LiveIntervals::printInstrs(raw_ostream &OS) const {
172 OS << "********** MACHINEINSTRS **********\n";
173 MF->print(OS, Indexes);
176 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
177 void LiveIntervals::dumpInstrs() const {
182 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
183 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
184 llvm::huge_valf : 0.0F;
185 return new LiveInterval(reg, Weight);
189 /// computeVirtRegInterval - Compute the live interval of a virtual register,
190 /// based on defs and uses.
191 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
192 assert(LRCalc && "LRCalc not initialized.");
193 assert(LI.empty() && "Should only compute empty intervals.");
194 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
195 LRCalc->createDeadDefs(LI);
196 LRCalc->extendToUses(LI);
197 computeDeadValues(LI, LI);
200 void LiveIntervals::computeVirtRegs() {
201 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
202 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
203 if (MRI->reg_nodbg_empty(Reg))
205 createAndComputeVirtRegInterval(Reg);
209 void LiveIntervals::computeRegMasks() {
210 RegMaskBlocks.resize(MF->getNumBlockIDs());
212 // Find all instructions with regmask operands.
213 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
215 MachineBasicBlock *MBB = MBBI;
216 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
217 RMB.first = RegMaskSlots.size();
218 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
220 for (MIOperands MO(MI); MO.isValid(); ++MO) {
221 if (!MO->isRegMask())
223 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
224 RegMaskBits.push_back(MO->getRegMask());
226 // Compute the number of register mask instructions in this block.
227 RMB.second = RegMaskSlots.size() - RMB.first;
231 //===----------------------------------------------------------------------===//
232 // Register Unit Liveness
233 //===----------------------------------------------------------------------===//
235 // Fixed interference typically comes from ABI boundaries: Function arguments
236 // and return values are passed in fixed registers, and so are exception
237 // pointers entering landing pads. Certain instructions require values to be
238 // present in specific registers. That is also represented through fixed
242 /// computeRegUnitInterval - Compute the live range of a register unit, based
243 /// on the uses and defs of aliasing registers. The range should be empty,
244 /// or contain only dead phi-defs from ABI blocks.
245 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
246 assert(LRCalc && "LRCalc not initialized.");
247 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
249 // The physregs aliasing Unit are the roots and their super-registers.
250 // Create all values as dead defs before extending to uses. Note that roots
251 // may share super-registers. That's OK because createDeadDefs() is
252 // idempotent. It is very rare for a register unit to have multiple roots, so
253 // uniquing super-registers is probably not worthwhile.
254 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
255 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
256 Supers.isValid(); ++Supers) {
257 if (!MRI->reg_empty(*Supers))
258 LRCalc->createDeadDefs(LR, *Supers);
262 // Now extend LR to reach all uses.
263 // Ignore uses of reserved registers. We only track defs of those.
264 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
265 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
266 Supers.isValid(); ++Supers) {
267 unsigned Reg = *Supers;
268 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
269 LRCalc->extendToUses(LR, Reg);
275 /// computeLiveInRegUnits - Precompute the live ranges of any register units
276 /// that are live-in to an ABI block somewhere. Register values can appear
277 /// without a corresponding def when entering the entry block or a landing pad.
279 void LiveIntervals::computeLiveInRegUnits() {
280 RegUnitRanges.resize(TRI->getNumRegUnits());
281 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
283 // Keep track of the live range sets allocated.
284 SmallVector<unsigned, 8> NewRanges;
286 // Check all basic blocks for live-ins.
287 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
289 const MachineBasicBlock *MBB = MFI;
291 // We only care about ABI blocks: Entry + landing pads.
292 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
295 // Create phi-defs at Begin for all live-in registers.
296 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
297 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
298 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
299 LIE = MBB->livein_end(); LII != LIE; ++LII) {
300 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
301 unsigned Unit = *Units;
302 LiveRange *LR = RegUnitRanges[Unit];
304 LR = RegUnitRanges[Unit] = new LiveRange();
305 NewRanges.push_back(Unit);
307 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
309 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
312 DEBUG(dbgs() << '\n');
314 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
316 // Compute the 'normal' part of the ranges.
317 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
318 unsigned Unit = NewRanges[i];
319 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
324 static void createSegmentsForValues(LiveRange &LR,
325 iterator_range<LiveInterval::vni_iterator> VNIs) {
326 for (auto VNI : VNIs) {
329 SlotIndex Def = VNI->def;
330 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
334 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
336 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
337 ShrinkToUsesWorkList &WorkList,
338 const LiveRange &OldRange) {
339 // Keep track of the PHIs that are in use.
340 SmallPtrSet<VNInfo*, 8> UsedPHIs;
341 // Blocks that have already been added to WorkList as live-out.
342 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
344 // Extend intervals to reach all uses in WorkList.
345 while (!WorkList.empty()) {
346 SlotIndex Idx = WorkList.back().first;
347 VNInfo *VNI = WorkList.back().second;
349 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
350 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
352 // Extend the live range for VNI to be live at Idx.
353 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
354 assert(ExtVNI == VNI && "Unexpected existing value number");
356 // Is this a PHIDef we haven't seen before?
357 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
358 !UsedPHIs.insert(VNI).second)
360 // The PHI is live, make sure the predecessors are live-out.
361 for (auto &Pred : MBB->predecessors()) {
362 if (!LiveOut.insert(Pred).second)
364 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
365 // A predecessor is not required to have a live-out value for a PHI.
366 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
367 WorkList.push_back(std::make_pair(Stop, PVNI));
372 // VNI is live-in to MBB.
373 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
374 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
376 // Make sure VNI is live-out from the predecessors.
377 for (auto &Pred : MBB->predecessors()) {
378 if (!LiveOut.insert(Pred).second)
380 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
381 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
382 "Wrong value out of predecessor");
383 WorkList.push_back(std::make_pair(Stop, VNI));
388 /// shrinkToUses - After removing some uses of a register, shrink its live
389 /// range to just the remaining uses. This method does not compute reaching
390 /// defs for new uses, and it doesn't remove dead defs.
391 bool LiveIntervals::shrinkToUses(LiveInterval *li,
392 SmallVectorImpl<MachineInstr*> *dead) {
393 DEBUG(dbgs() << "Shrink: " << *li << '\n');
394 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
395 && "Can only shrink virtual registers");
397 // Shrink subregister live ranges.
398 for (LiveInterval::subrange_iterator I = li->subrange_begin(),
399 E = li->subrange_end(); I != E; ++I) {
400 shrinkToUses(*I, li->reg);
403 // Find all the values used, including PHI kills.
404 ShrinkToUsesWorkList WorkList;
406 // Visit all instructions reading li->reg.
407 for (MachineRegisterInfo::reg_instr_iterator
408 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
410 MachineInstr *UseMI = &*(I++);
411 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
413 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
414 LiveQueryResult LRQ = li->Query(Idx);
415 VNInfo *VNI = LRQ.valueIn();
417 // This shouldn't happen: readsVirtualRegister returns true, but there is
418 // no live value. It is likely caused by a target getting <undef> flags
420 DEBUG(dbgs() << Idx << '\t' << *UseMI
421 << "Warning: Instr claims to read non-existent value in "
425 // Special case: An early-clobber tied operand reads and writes the
426 // register one slot early.
427 if (VNInfo *DefVNI = LRQ.valueDefined())
430 WorkList.push_back(std::make_pair(Idx, VNI));
433 // Create new live ranges with only minimal live segments per def.
435 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
436 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
438 // Handle dead values.
440 computeDeadValues(NewLR, *li, &CanSeparate, li->reg, dead);
442 // Move the trimmed segments back.
443 li->segments.swap(NewLR.segments);
444 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
448 void LiveIntervals::computeDeadValues(LiveRange &Segments, LiveRange &LR,
449 bool *CanSeparateRes, unsigned Reg,
450 SmallVectorImpl<MachineInstr*> *dead) {
451 bool CanSeparate = false;
452 for (auto VNI : make_range(LR.vni_begin(), LR.vni_end())) {
455 LiveRange::iterator LRI = Segments.FindSegmentContaining(VNI->def);
456 assert(LRI != Segments.end() && "Missing segment for PHI");
457 if (LRI->end != VNI->def.getDeadSlot())
459 if (VNI->isPHIDef()) {
460 // This is a dead PHI. Remove it.
462 Segments.removeSegment(LRI->start, LRI->end);
463 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
465 } else if (dead != nullptr) {
466 // This is a dead def. Make sure the instruction knows.
467 MachineInstr *MI = getInstructionFromIndex(VNI->def);
468 assert(MI && "No instruction defining live value");
469 MI->addRegisterDead(Reg, TRI);
470 if (dead && MI->allDefsAreDead()) {
471 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
476 if (CanSeparateRes != nullptr)
477 *CanSeparateRes = CanSeparate;
480 bool LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
482 DEBUG(dbgs() << "Shrink: " << SR << '\n');
483 assert(TargetRegisterInfo::isVirtualRegister(Reg)
484 && "Can only shrink virtual registers");
485 // Find all the values used, including PHI kills.
486 ShrinkToUsesWorkList WorkList;
488 // Visit all instructions reading Reg.
490 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
491 MachineInstr *UseMI = MO.getParent();
492 if (UseMI->isDebugValue())
494 // Maybe the operand is for a subregister we don't care about.
495 unsigned SubReg = MO.getSubReg();
497 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
498 if ((SubRegMask & SR.LaneMask) == 0)
501 // We only need to visit each instruction once.
502 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
507 LiveQueryResult LRQ = SR.Query(Idx);
508 VNInfo *VNI = LRQ.valueIn();
509 // For Subranges it is possible that only undef values are left in that
510 // part of the subregister, so there is no real liverange at the use
514 // Special case: An early-clobber tied operand reads and writes the
515 // register one slot early.
516 if (VNInfo *DefVNI = LRQ.valueDefined())
519 WorkList.push_back(std::make_pair(Idx, VNI));
522 // Create a new live ranges with only minimal live segments per def.
524 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
525 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
527 // Handle dead values.
529 computeDeadValues(NewLR, SR, &CanSeparate);
531 // Move the trimmed ranges back.
532 SR.segments.swap(NewLR.segments);
533 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
537 void LiveIntervals::extendToIndices(LiveRange &LR,
538 ArrayRef<SlotIndex> Indices) {
539 assert(LRCalc && "LRCalc not initialized.");
540 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
541 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
542 LRCalc->extend(LR, Indices[i]);
545 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
546 SmallVectorImpl<SlotIndex> *EndPoints) {
547 LiveQueryResult LRQ = LI->Query(Kill);
548 VNInfo *VNI = LRQ.valueOut();
552 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
553 SlotIndex MBBStart, MBBEnd;
554 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
556 // If VNI isn't live out from KillMBB, the value is trivially pruned.
557 if (LRQ.endPoint() < MBBEnd) {
558 LI->removeSegment(Kill, LRQ.endPoint());
559 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
563 // VNI is live out of KillMBB.
564 LI->removeSegment(Kill, MBBEnd);
565 if (EndPoints) EndPoints->push_back(MBBEnd);
567 // Find all blocks that are reachable from KillMBB without leaving VNI's live
568 // range. It is possible that KillMBB itself is reachable, so start a DFS
569 // from each successor.
570 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
572 for (MachineBasicBlock::succ_iterator
573 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
574 SuccI != SuccE; ++SuccI) {
575 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
576 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
578 MachineBasicBlock *MBB = *I;
580 // Check if VNI is live in to MBB.
581 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
582 LiveQueryResult LRQ = LI->Query(MBBStart);
583 if (LRQ.valueIn() != VNI) {
584 // This block isn't part of the VNI segment. Prune the search.
589 // Prune the search if VNI is killed in MBB.
590 if (LRQ.endPoint() < MBBEnd) {
591 LI->removeSegment(MBBStart, LRQ.endPoint());
592 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
597 // VNI is live through MBB.
598 LI->removeSegment(MBBStart, MBBEnd);
599 if (EndPoints) EndPoints->push_back(MBBEnd);
605 //===----------------------------------------------------------------------===//
606 // Register allocator hooks.
609 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
610 // Keep track of regunit ranges.
611 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
613 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
614 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
615 if (MRI->reg_nodbg_empty(Reg))
617 LiveInterval *LI = &getInterval(Reg);
621 // Find the regunit intervals for the assigned register. They may overlap
622 // the virtual register live range, cancelling any kills.
624 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
626 LiveRange &RURanges = getRegUnit(*Units);
627 if (RURanges.empty())
629 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
632 // Every instruction that kills Reg corresponds to a segment range end
634 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
636 // A block index indicates an MBB edge.
637 if (RI->end.isBlock())
639 MachineInstr *MI = getInstructionFromIndex(RI->end);
643 // Check if any of the regunits are live beyond the end of RI. That could
644 // happen when a physreg is defined as a copy of a virtreg:
646 // %EAX = COPY %vreg5
647 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
650 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
651 bool CancelKill = false;
652 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
653 LiveRange &RRanges = *RU[u].first;
654 LiveRange::iterator &I = RU[u].second;
655 if (I == RRanges.end())
657 I = RRanges.advanceTo(I, RI->end);
658 if (I == RRanges.end() || I->start >= RI->end)
660 // I is overlapping RI.
665 MI->clearRegisterKills(Reg, nullptr);
667 MI->addRegisterKilled(Reg, nullptr);
673 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
674 // A local live range must be fully contained inside the block, meaning it is
675 // defined and killed at instructions, not at block boundaries. It is not
676 // live in or or out of any block.
678 // It is technically possible to have a PHI-defined live range identical to a
679 // single block, but we are going to return false in that case.
681 SlotIndex Start = LI.beginIndex();
685 SlotIndex Stop = LI.endIndex();
689 // getMBBFromIndex doesn't need to search the MBB table when both indexes
690 // belong to proper instructions.
691 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
692 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
693 return MBB1 == MBB2 ? MBB1 : nullptr;
697 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
698 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
700 const VNInfo *PHI = *I;
701 if (PHI->isUnused() || !PHI->isPHIDef())
703 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
704 // Conservatively return true instead of scanning huge predecessor lists.
705 if (PHIMBB->pred_size() > 100)
707 for (MachineBasicBlock::const_pred_iterator
708 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
709 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
716 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
717 const MachineBlockFrequencyInfo *MBFI,
718 const MachineInstr *MI) {
719 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
720 const float Scale = 1.0f / MBFI->getEntryFreq();
721 return (isDef + isUse) * (Freq.getFrequency() * Scale);
725 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
726 LiveInterval& Interval = createEmptyInterval(reg);
727 VNInfo* VN = Interval.getNextValue(
728 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
729 getVNInfoAllocator());
730 LiveRange::Segment S(
731 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
732 getMBBEndIdx(startInst->getParent()), VN);
733 Interval.addSegment(S);
739 //===----------------------------------------------------------------------===//
740 // Register mask functions
741 //===----------------------------------------------------------------------===//
743 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
744 BitVector &UsableRegs) {
747 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
749 // Use a smaller arrays for local live ranges.
750 ArrayRef<SlotIndex> Slots;
751 ArrayRef<const uint32_t*> Bits;
752 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
753 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
754 Bits = getRegMaskBitsInBlock(MBB->getNumber());
756 Slots = getRegMaskSlots();
757 Bits = getRegMaskBits();
760 // We are going to enumerate all the register mask slots contained in LI.
761 // Start with a binary search of RegMaskSlots to find a starting point.
762 ArrayRef<SlotIndex>::iterator SlotI =
763 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
764 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
766 // No slots in range, LI begins after the last call.
772 assert(*SlotI >= LiveI->start);
773 // Loop over all slots overlapping this segment.
774 while (*SlotI < LiveI->end) {
775 // *SlotI overlaps LI. Collect mask bits.
777 // This is the first overlap. Initialize UsableRegs to all ones.
779 UsableRegs.resize(TRI->getNumRegs(), true);
782 // Remove usable registers clobbered by this mask.
783 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
784 if (++SlotI == SlotE)
787 // *SlotI is beyond the current LI segment.
788 LiveI = LI.advanceTo(LiveI, *SlotI);
791 // Advance SlotI until it overlaps.
792 while (*SlotI < LiveI->start)
793 if (++SlotI == SlotE)
798 //===----------------------------------------------------------------------===//
799 // IntervalUpdate class.
800 //===----------------------------------------------------------------------===//
802 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
803 class LiveIntervals::HMEditor {
806 const MachineRegisterInfo& MRI;
807 const TargetRegisterInfo& TRI;
810 SmallPtrSet<LiveRange*, 8> Updated;
814 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
815 const TargetRegisterInfo& TRI,
816 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
817 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
818 UpdateFlags(UpdateFlags) {}
820 // FIXME: UpdateFlags is a workaround that creates live intervals for all
821 // physregs, even those that aren't needed for regalloc, in order to update
822 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
823 // flags, and postRA passes will use a live register utility instead.
824 LiveRange *getRegUnitLI(unsigned Unit) {
826 return &LIS.getRegUnit(Unit);
827 return LIS.getCachedRegUnit(Unit);
830 /// Update all live ranges touched by MI, assuming a move from OldIdx to
832 void updateAllRanges(MachineInstr *MI) {
833 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
834 bool hasRegMask = false;
835 for (MIOperands MO(MI); MO.isValid(); ++MO) {
840 // Aggressively clear all kill flags.
841 // They are reinserted by VirtRegRewriter.
843 MO->setIsKill(false);
845 unsigned Reg = MO->getReg();
848 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
849 LiveInterval &LI = LIS.getInterval(Reg);
850 if (LI.hasSubRanges()) {
851 unsigned SubReg = MO->getSubReg();
852 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
853 for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
854 SE = LI.subrange_end(); S != SE; ++S) {
855 if ((S->LaneMask & LaneMask) == 0)
857 updateRange(*S, Reg, S->LaneMask);
860 updateRange(LI, Reg, 0);
864 // For physregs, only update the regunits that actually have a
865 // precomputed live range.
866 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
867 if (LiveRange *LR = getRegUnitLI(*Units))
868 updateRange(*LR, *Units, 0);
871 updateRegMaskSlots();
875 /// Update a single live range, assuming an instruction has been moved from
876 /// OldIdx to NewIdx.
877 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
878 if (!Updated.insert(&LR).second)
882 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
883 dbgs() << PrintReg(Reg);
885 dbgs() << format(" L%04X", LaneMask);
887 dbgs() << PrintRegUnit(Reg, &TRI);
889 dbgs() << ":\t" << LR << '\n';
891 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
894 handleMoveUp(LR, Reg, LaneMask);
895 DEBUG(dbgs() << " -->\t" << LR << '\n');
899 /// Update LR to reflect an instruction has been moved downwards from OldIdx
902 /// 1. Live def at OldIdx:
903 /// Move def to NewIdx, assert endpoint after NewIdx.
905 /// 2. Live def at OldIdx, killed at NewIdx:
906 /// Change to dead def at NewIdx.
907 /// (Happens when bundling def+kill together).
909 /// 3. Dead def at OldIdx:
910 /// Move def to NewIdx, possibly across another live value.
912 /// 4. Def at OldIdx AND at NewIdx:
913 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
914 /// (Happens when bundling multiple defs together).
916 /// 5. Value read at OldIdx, killed before NewIdx:
917 /// Extend kill to NewIdx.
919 void handleMoveDown(LiveRange &LR) {
920 // First look for a kill at OldIdx.
921 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
922 LiveRange::iterator E = LR.end();
923 // Is LR even live at OldIdx?
924 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
927 // Handle a live-in value.
928 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
929 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
930 // If the live-in value already extends to NewIdx, there is nothing to do.
931 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
933 // Aggressively remove all kill flags from the old kill point.
934 // Kill flags shouldn't be used while live intervals exist, they will be
935 // reinserted by VirtRegRewriter.
936 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
937 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
938 if (MO->isReg() && MO->isUse())
939 MO->setIsKill(false);
940 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
941 // overlapping ranges. Case 5 above.
942 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
943 // If this was a kill, there may also be a def. Otherwise we're done.
949 // Check for a def at OldIdx.
950 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
952 // We have a def at OldIdx.
953 VNInfo *DefVNI = I->valno;
954 assert(DefVNI->def == I->start && "Inconsistent def");
955 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
956 // If the defined value extends beyond NewIdx, just move the def down.
957 // This is case 1 above.
958 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
959 I->start = DefVNI->def;
962 // The remaining possibilities are now:
963 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
964 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
965 // In either case, it is possible that there is an existing def at NewIdx.
966 assert((I->end == OldIdx.getDeadSlot() ||
967 SlotIndex::isSameInstr(I->end, NewIdx)) &&
968 "Cannot move def below kill");
969 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
970 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
971 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
972 // coalesced into that value.
973 assert(NewI->valno != DefVNI && "Multiple defs of value?");
974 LR.removeValNo(DefVNI);
977 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
978 // If the def at OldIdx was dead, we allow it to be moved across other LR
979 // values. The new range should be placed immediately before NewI, move any
980 // intermediate ranges up.
981 assert(NewI != I && "Inconsistent iterators");
982 std::copy(std::next(I), NewI, I);
984 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
987 /// Update LR to reflect an instruction has been moved upwards from OldIdx
990 /// 1. Live def at OldIdx:
991 /// Hoist def to NewIdx.
993 /// 2. Dead def at OldIdx:
994 /// Hoist def+end to NewIdx, possibly move across other values.
996 /// 3. Dead def at OldIdx AND existing def at NewIdx:
997 /// Remove value defined at OldIdx, coalescing it with existing value.
999 /// 4. Live def at OldIdx AND existing def at NewIdx:
1000 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1001 /// (Happens when bundling multiple defs together).
1003 /// 5. Value killed at OldIdx:
1004 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1007 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1008 // First look for a kill at OldIdx.
1009 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1010 LiveRange::iterator E = LR.end();
1011 // Is LR even live at OldIdx?
1012 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1015 // Handle a live-in value.
1016 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1017 // If the live-in value isn't killed here, there is nothing to do.
1018 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1020 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1021 // another use, we need to search for that use. Case 5 above.
1022 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1024 // If OldIdx also defines a value, there couldn't have been another use.
1025 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1026 // No def, search for the new kill.
1027 // This can never be an early clobber kill since there is no def.
1028 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1033 // Now deal with the def at OldIdx.
1034 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1035 VNInfo *DefVNI = I->valno;
1036 assert(DefVNI->def == I->start && "Inconsistent def");
1037 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1039 // Check for an existing def at NewIdx.
1040 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1041 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1042 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1043 // There is an existing def at NewIdx.
1044 if (I->end.isDead()) {
1045 // Case 3: Remove the dead def at OldIdx.
1046 LR.removeValNo(DefVNI);
1049 // Case 4: Replace def at NewIdx with live def at OldIdx.
1050 I->start = DefVNI->def;
1051 LR.removeValNo(NewI->valno);
1055 // There is no existing def at NewIdx. Hoist DefVNI.
1056 if (!I->end.isDead()) {
1057 // Leave the end point of a live def.
1058 I->start = DefVNI->def;
1062 // DefVNI is a dead def. It may have been moved across other values in LR,
1063 // so move I up to NewI. Slide [NewI;I) down one position.
1064 std::copy_backward(NewI, I, std::next(I));
1065 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1068 void updateRegMaskSlots() {
1069 SmallVectorImpl<SlotIndex>::iterator RI =
1070 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1072 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1073 "No RegMask at OldIdx.");
1074 *RI = NewIdx.getRegSlot();
1075 assert((RI == LIS.RegMaskSlots.begin() ||
1076 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1077 "Cannot move regmask instruction above another call");
1078 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1079 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1080 "Cannot move regmask instruction below another call");
1083 // Return the last use of reg between NewIdx and OldIdx.
1084 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1086 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1087 SlotIndex LastUse = NewIdx;
1088 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1089 unsigned SubReg = MO.getSubReg();
1090 if (SubReg != 0 && LaneMask != 0
1091 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1094 const MachineInstr *MI = MO.getParent();
1095 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1096 if (InstSlot > LastUse && InstSlot < OldIdx)
1102 // This is a regunit interval, so scanning the use list could be very
1103 // expensive. Scan upwards from OldIdx instead.
1104 assert(NewIdx < OldIdx && "Expected upwards move");
1105 SlotIndexes *Indexes = LIS.getSlotIndexes();
1106 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1108 // OldIdx may not correspond to an instruction any longer, so set MII to
1109 // point to the next instruction after OldIdx, or MBB->end().
1110 MachineBasicBlock::iterator MII = MBB->end();
1111 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1112 Indexes->getNextNonNullIndex(OldIdx)))
1113 if (MI->getParent() == MBB)
1116 MachineBasicBlock::iterator Begin = MBB->begin();
1117 while (MII != Begin) {
1118 if ((--MII)->isDebugValue())
1120 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1122 // Stop searching when NewIdx is reached.
1123 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1126 // Check if MII uses Reg.
1127 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1129 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1130 TRI.hasRegUnit(MO->getReg(), Reg))
1133 // Didn't reach NewIdx. It must be the first instruction in the block.
1138 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1139 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1140 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1141 Indexes->removeMachineInstrFromMaps(MI);
1142 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1143 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1144 OldIndex < getMBBEndIdx(MI->getParent()) &&
1145 "Cannot handle moves across basic block boundaries.");
1147 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1148 HME.updateAllRanges(MI);
1151 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1152 MachineInstr* BundleStart,
1154 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1155 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1156 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1157 HME.updateAllRanges(MI);
1160 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1161 const MachineBasicBlock::iterator End,
1162 const SlotIndex endIdx,
1163 LiveRange &LR, const unsigned Reg,
1164 const unsigned LaneMask) {
1165 LiveInterval::iterator LII = LR.find(endIdx);
1166 SlotIndex lastUseIdx;
1167 if (LII != LR.end() && LII->start < endIdx)
1168 lastUseIdx = LII->end;
1172 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1174 MachineInstr *MI = I;
1175 if (MI->isDebugValue())
1178 SlotIndex instrIdx = getInstructionIndex(MI);
1179 bool isStartValid = getInstructionFromIndex(LII->start);
1180 bool isEndValid = getInstructionFromIndex(LII->end);
1182 // FIXME: This doesn't currently handle early-clobber or multiple removed
1183 // defs inside of the region to repair.
1184 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1185 OE = MI->operands_end(); OI != OE; ++OI) {
1186 const MachineOperand &MO = *OI;
1187 if (!MO.isReg() || MO.getReg() != Reg)
1190 unsigned SubReg = MO.getSubReg();
1191 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1192 if ((Mask & LaneMask) == 0)
1196 if (!isStartValid) {
1197 if (LII->end.isDead()) {
1198 SlotIndex prevStart;
1199 if (LII != LR.begin())
1200 prevStart = std::prev(LII)->start;
1202 // FIXME: This could be more efficient if there was a
1203 // removeSegment method that returned an iterator.
1204 LR.removeSegment(*LII, true);
1205 if (prevStart.isValid())
1206 LII = LR.find(prevStart);
1210 LII->start = instrIdx.getRegSlot();
1211 LII->valno->def = instrIdx.getRegSlot();
1212 if (MO.getSubReg() && !MO.isUndef())
1213 lastUseIdx = instrIdx.getRegSlot();
1215 lastUseIdx = SlotIndex();
1220 if (!lastUseIdx.isValid()) {
1221 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1222 LiveRange::Segment S(instrIdx.getRegSlot(),
1223 instrIdx.getDeadSlot(), VNI);
1224 LII = LR.addSegment(S);
1225 } else if (LII->start != instrIdx.getRegSlot()) {
1226 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1227 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1228 LII = LR.addSegment(S);
1231 if (MO.getSubReg() && !MO.isUndef())
1232 lastUseIdx = instrIdx.getRegSlot();
1234 lastUseIdx = SlotIndex();
1235 } else if (MO.isUse()) {
1236 // FIXME: This should probably be handled outside of this branch,
1237 // either as part of the def case (for defs inside of the region) or
1238 // after the loop over the region.
1239 if (!isEndValid && !LII->end.isBlock())
1240 LII->end = instrIdx.getRegSlot();
1241 if (!lastUseIdx.isValid())
1242 lastUseIdx = instrIdx.getRegSlot();
1249 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1250 MachineBasicBlock::iterator Begin,
1251 MachineBasicBlock::iterator End,
1252 ArrayRef<unsigned> OrigRegs) {
1253 // Find anchor points, which are at the beginning/end of blocks or at
1254 // instructions that already have indexes.
1255 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1257 while (End != MBB->end() && !Indexes->hasIndex(End))
1261 if (End == MBB->end())
1262 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1264 endIdx = getInstructionIndex(End);
1266 Indexes->repairIndexesInRange(MBB, Begin, End);
1268 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1270 MachineInstr *MI = I;
1271 if (MI->isDebugValue())
1273 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1274 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1276 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1277 !hasInterval(MOI->getReg())) {
1278 createAndComputeVirtRegInterval(MOI->getReg());
1283 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1284 unsigned Reg = OrigRegs[i];
1285 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1288 LiveInterval &LI = getInterval(Reg);
1289 // FIXME: Should we support undefs that gain defs?
1290 if (!LI.hasAtLeastOneValue())
1293 for (LiveInterval::subrange_iterator S = LI.subrange_begin(),
1294 SE = LI.subrange_end(); S != SE; ++S) {
1295 repairOldRegInRange(Begin, End, endIdx, *S, Reg, S->LaneMask);
1297 repairOldRegInRange(Begin, End, endIdx, LI, Reg);