1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "LiveRangeCalc.h"
43 // Hidden options for help debugging.
44 static cl::opt<bool> DisableReMat("disable-rematerialization",
45 cl::init(false), cl::Hidden);
47 // Temporary option to enable regunit liveness.
48 static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden);
50 STATISTIC(numIntervals , "Number of original intervals");
52 char LiveIntervals::ID = 0;
53 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
54 "Live Interval Analysis", false, false)
55 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
56 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
57 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
58 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
59 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
60 "Live Interval Analysis", false, false)
62 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.addRequired<AliasAnalysis>();
65 AU.addPreserved<AliasAnalysis>();
66 AU.addRequired<LiveVariables>();
67 AU.addPreserved<LiveVariables>();
68 AU.addPreservedID(MachineLoopInfoID);
70 AU.addRequiredTransitiveID(MachineDominatorsID);
71 AU.addPreservedID(MachineDominatorsID);
72 AU.addPreserved<SlotIndexes>();
73 AU.addRequiredTransitive<SlotIndexes>();
74 MachineFunctionPass::getAnalysisUsage(AU);
77 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
78 DomTree(0), LRCalc(0) {
79 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
82 LiveIntervals::~LiveIntervals() {
86 void LiveIntervals::releaseMemory() {
87 // Free the live intervals themselves.
88 for (DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.begin(),
89 E = R2IMap.end(); I != E; ++I)
95 RegMaskBlocks.clear();
97 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
98 delete RegUnitIntervals[i];
99 RegUnitIntervals.clear();
101 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
102 VNInfoAllocator.Reset();
105 /// runOnMachineFunction - Register allocate the whole function
107 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
109 MRI = &MF->getRegInfo();
110 TM = &fn.getTarget();
111 TRI = TM->getRegisterInfo();
112 TII = TM->getInstrInfo();
113 AA = &getAnalysis<AliasAnalysis>();
114 LV = &getAnalysis<LiveVariables>();
115 Indexes = &getAnalysis<SlotIndexes>();
117 DomTree = &getAnalysis<MachineDominatorTree>();
118 if (LiveRegUnits && !LRCalc)
119 LRCalc = new LiveRangeCalc();
120 AllocatableRegs = TRI->getAllocatableSet(fn);
121 ReservedRegs = TRI->getReservedRegs(fn);
125 numIntervals += getNumIntervals();
128 computeLiveInRegUnits();
135 /// print - Implement the dump method.
136 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
137 OS << "********** INTERVALS **********\n";
139 // Dump the physregs.
140 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
141 if (const LiveInterval *LI = R2IMap.lookup(Reg)) {
146 // Dump the regunits.
147 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
148 if (LiveInterval *LI = RegUnitIntervals[i])
149 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
151 // Dump the virtregs.
152 for (unsigned Reg = 0, RegE = MRI->getNumVirtRegs(); Reg != RegE; ++Reg)
153 if (const LiveInterval *LI =
154 R2IMap.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
162 void LiveIntervals::printInstrs(raw_ostream &OS) const {
163 OS << "********** MACHINEINSTRS **********\n";
164 MF->print(OS, Indexes);
167 void LiveIntervals::dumpInstrs() const {
172 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
173 unsigned Reg = MI.getOperand(MOIdx).getReg();
174 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
175 const MachineOperand &MO = MI.getOperand(i);
178 if (MO.getReg() == Reg && MO.isDef()) {
179 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
180 MI.getOperand(MOIdx).getSubReg() &&
181 (MO.getSubReg() || MO.isImplicit()));
188 /// isPartialRedef - Return true if the specified def at the specific index is
189 /// partially re-defining the specified live interval. A common case of this is
190 /// a definition of the sub-register.
191 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
192 LiveInterval &interval) {
193 if (!MO.getSubReg() || MO.isEarlyClobber())
196 SlotIndex RedefIndex = MIIdx.getRegSlot();
197 const LiveRange *OldLR =
198 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
199 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
201 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
206 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
207 MachineBasicBlock::iterator mi,
211 LiveInterval &interval) {
212 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
214 // Virtual registers may be defined multiple times (due to phi
215 // elimination and 2-addr elimination). Much of what we do only has to be
216 // done once for the vreg. We use an empty interval to detect the first
217 // time we see a vreg.
218 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
219 if (interval.empty()) {
220 // Get the Idx of the defining instructions.
221 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
223 // Make sure the first definition is not a partial redefinition.
224 assert(!MO.readsReg() && "First def cannot also read virtual register "
225 "missing <undef> flag?");
227 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
228 assert(ValNo->id == 0 && "First value in interval is not 0?");
230 // Loop over all of the blocks that the vreg is defined in. There are
231 // two cases we have to handle here. The most common case is a vreg
232 // whose lifetime is contained within a basic block. In this case there
233 // will be a single kill, in MBB, which comes after the definition.
234 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
235 // FIXME: what about dead vars?
237 if (vi.Kills[0] != mi)
238 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
240 killIdx = defIndex.getDeadSlot();
242 // If the kill happens after the definition, we have an intra-block
244 if (killIdx > defIndex) {
245 assert(vi.AliveBlocks.empty() &&
246 "Shouldn't be alive across any blocks!");
247 LiveRange LR(defIndex, killIdx, ValNo);
248 interval.addRange(LR);
249 DEBUG(dbgs() << " +" << LR << "\n");
254 // The other case we handle is when a virtual register lives to the end
255 // of the defining block, potentially live across some blocks, then is
256 // live into some number of blocks, but gets killed. Start by adding a
257 // range that goes from this definition to the end of the defining block.
258 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
259 DEBUG(dbgs() << " +" << NewLR);
260 interval.addRange(NewLR);
262 bool PHIJoin = LV->isPHIJoin(interval.reg);
265 // A phi join register is killed at the end of the MBB and revived as a new
266 // valno in the killing blocks.
267 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
268 DEBUG(dbgs() << " phi-join");
269 ValNo->setHasPHIKill(true);
271 // Iterate over all of the blocks that the variable is completely
272 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
274 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
275 E = vi.AliveBlocks.end(); I != E; ++I) {
276 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
277 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
278 interval.addRange(LR);
279 DEBUG(dbgs() << " +" << LR);
283 // Finally, this virtual register is live from the start of any killing
284 // block to the 'use' slot of the killing instruction.
285 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
286 MachineInstr *Kill = vi.Kills[i];
287 SlotIndex Start = getMBBStartIdx(Kill->getParent());
288 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
290 // Create interval with one of a NEW value number. Note that this value
291 // number isn't actually defined by an instruction, weird huh? :)
293 assert(getInstructionFromIndex(Start) == 0 &&
294 "PHI def index points at actual instruction.");
295 ValNo = interval.getNextValue(Start, VNInfoAllocator);
296 ValNo->setIsPHIDef(true);
298 LiveRange LR(Start, killIdx, ValNo);
299 interval.addRange(LR);
300 DEBUG(dbgs() << " +" << LR);
304 if (MultipleDefsBySameMI(*mi, MOIdx))
305 // Multiple defs of the same virtual register by the same instruction.
306 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
307 // This is likely due to elimination of REG_SEQUENCE instructions. Return
308 // here since there is nothing to do.
311 // If this is the second time we see a virtual register definition, it
312 // must be due to phi elimination or two addr elimination. If this is
313 // the result of two address elimination, then the vreg is one of the
314 // def-and-use register operand.
316 // It may also be partial redef like this:
317 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
318 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
319 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
320 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
321 // If this is a two-address definition, then we have already processed
322 // the live range. The only problem is that we didn't realize there
323 // are actually two values in the live interval. Because of this we
324 // need to take the LiveRegion that defines this register and split it
326 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
328 const LiveRange *OldLR =
329 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
330 VNInfo *OldValNo = OldLR->valno;
331 SlotIndex DefIndex = OldValNo->def.getRegSlot();
333 // Delete the previous value, which should be short and continuous,
334 // because the 2-addr copy must be in the same MBB as the redef.
335 interval.removeRange(DefIndex, RedefIndex);
337 // The new value number (#1) is defined by the instruction we claimed
339 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
341 // Value#0 is now defined by the 2-addr instruction.
342 OldValNo->def = RedefIndex;
344 // Add the new live interval which replaces the range for the input copy.
345 LiveRange LR(DefIndex, RedefIndex, ValNo);
346 DEBUG(dbgs() << " replace range with " << LR);
347 interval.addRange(LR);
349 // If this redefinition is dead, we need to add a dummy unit live
350 // range covering the def slot.
352 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
356 dbgs() << " RESULT: ";
357 interval.print(dbgs(), TRI);
359 } else if (LV->isPHIJoin(interval.reg)) {
360 // In the case of PHI elimination, each variable definition is only
361 // live until the end of the block. We've already taken care of the
362 // rest of the live range.
364 SlotIndex defIndex = MIIdx.getRegSlot();
365 if (MO.isEarlyClobber())
366 defIndex = MIIdx.getRegSlot(true);
368 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
370 SlotIndex killIndex = getMBBEndIdx(mbb);
371 LiveRange LR(defIndex, killIndex, ValNo);
372 interval.addRange(LR);
373 ValNo->setHasPHIKill(true);
374 DEBUG(dbgs() << " phi-join +" << LR);
376 llvm_unreachable("Multiply defined register");
380 DEBUG(dbgs() << '\n');
383 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
384 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
385 SE = MBB->succ_end();
387 const MachineBasicBlock* succ = *SI;
388 if (succ->isLiveIn(Reg))
394 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
395 MachineBasicBlock::iterator mi,
398 LiveInterval &interval) {
399 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
401 SlotIndex baseIndex = MIIdx;
402 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
403 SlotIndex end = start;
405 // If it is not used after definition, it is considered dead at
406 // the instruction defining it. Hence its interval is:
407 // [defSlot(def), defSlot(def)+1)
408 // For earlyclobbers, the defSlot was pushed back one; the extra
409 // advance below compensates.
411 DEBUG(dbgs() << " dead");
412 end = start.getDeadSlot();
416 // If it is not dead on definition, it must be killed by a
417 // subsequent instruction. Hence its interval is:
418 // [defSlot(def), useSlot(kill)+1)
419 baseIndex = baseIndex.getNextIndex();
420 while (++mi != MBB->end()) {
422 if (mi->isDebugValue())
424 if (getInstructionFromIndex(baseIndex) == 0)
425 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
427 if (mi->killsRegister(interval.reg, TRI)) {
428 DEBUG(dbgs() << " killed");
429 end = baseIndex.getRegSlot();
432 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,TRI);
434 if (mi->isRegTiedToUseOperand(DefIdx)) {
435 // Two-address instruction.
436 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
438 // Another instruction redefines the register before it is ever read.
439 // Then the register is essentially dead at the instruction that
440 // defines it. Hence its interval is:
441 // [defSlot(def), defSlot(def)+1)
442 DEBUG(dbgs() << " dead");
443 end = start.getDeadSlot();
449 baseIndex = baseIndex.getNextIndex();
452 // If we get here the register *should* be live out.
453 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
455 // FIXME: We need saner rules for reserved regs.
456 if (isReserved(interval.reg)) {
457 end = start.getDeadSlot();
459 // Unreserved, unallocable registers like EFLAGS can be live across basic
461 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
462 "Unreserved reg not live-out?");
463 end = getMBBEndIdx(MBB);
466 assert(start < end && "did not find end of interval?");
468 // Already exists? Extend old live interval.
469 VNInfo *ValNo = interval.getVNInfoAt(start);
470 bool Extend = ValNo != 0;
472 ValNo = interval.getNextValue(start, VNInfoAllocator);
473 LiveRange LR(start, end, ValNo);
474 interval.addRange(LR);
475 DEBUG(dbgs() << " +" << LR << '\n');
478 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
479 MachineBasicBlock::iterator MI,
483 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
484 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
485 getOrCreateInterval(MO.getReg()));
487 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
488 getOrCreateInterval(MO.getReg()));
491 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
493 LiveInterval &interval) {
494 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
495 "Only physical registers can be live in.");
496 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
497 MBB->isLandingPad()) &&
498 "Allocatable live-ins only valid for entry blocks and landing pads.");
500 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, TRI));
502 // Look for kills, if it reaches a def before it's killed, then it shouldn't
503 // be considered a livein.
504 MachineBasicBlock::iterator mi = MBB->begin();
505 MachineBasicBlock::iterator E = MBB->end();
506 // Skip over DBG_VALUE at the start of the MBB.
507 if (mi != E && mi->isDebugValue()) {
508 while (++mi != E && mi->isDebugValue())
511 // MBB is empty except for DBG_VALUE's.
515 SlotIndex baseIndex = MIIdx;
516 SlotIndex start = baseIndex;
517 if (getInstructionFromIndex(baseIndex) == 0)
518 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
520 SlotIndex end = baseIndex;
521 bool SeenDefUse = false;
524 if (mi->killsRegister(interval.reg, TRI)) {
525 DEBUG(dbgs() << " killed");
526 end = baseIndex.getRegSlot();
529 } else if (mi->modifiesRegister(interval.reg, TRI)) {
530 // Another instruction redefines the register before it is ever read.
531 // Then the register is essentially dead at the instruction that defines
532 // it. Hence its interval is:
533 // [defSlot(def), defSlot(def)+1)
534 DEBUG(dbgs() << " dead");
535 end = start.getDeadSlot();
540 while (++mi != E && mi->isDebugValue())
541 // Skip over DBG_VALUE.
544 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
547 // Live-in register might not be used at all.
549 if (isAllocatable(interval.reg) ||
550 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
551 // Allocatable registers are never live through.
552 // Non-allocatable registers that aren't live into any successors also
553 // aren't live through.
554 DEBUG(dbgs() << " dead");
557 // If we get here the register is non-allocatable and live into some
558 // successor. We'll conservatively assume it's live-through.
559 DEBUG(dbgs() << " live through");
560 end = getMBBEndIdx(MBB);
564 SlotIndex defIdx = getMBBStartIdx(MBB);
565 assert(getInstructionFromIndex(defIdx) == 0 &&
566 "PHI def index points at actual instruction.");
567 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
568 vni->setIsPHIDef(true);
569 LiveRange LR(start, end, vni);
571 interval.addRange(LR);
572 DEBUG(dbgs() << " +" << LR << '\n');
575 /// computeIntervals - computes the live intervals for virtual
576 /// registers. for some ordering of the machine instructions [1,N] a
577 /// live interval is an interval [i, j) where 1 <= i <= j < N for
578 /// which a variable is live
579 void LiveIntervals::computeIntervals() {
580 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
581 << "********** Function: "
582 << ((Value*)MF->getFunction())->getName() << '\n');
584 RegMaskBlocks.resize(MF->getNumBlockIDs());
586 SmallVector<unsigned, 8> UndefUses;
587 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
589 MachineBasicBlock *MBB = MBBI;
590 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
595 // Track the index of the current machine instr.
596 SlotIndex MIIndex = getMBBStartIdx(MBB);
597 DEBUG(dbgs() << "BB#" << MBB->getNumber()
598 << ":\t\t# derived from " << MBB->getName() << "\n");
600 // Create intervals for live-ins to this BB first.
601 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
602 LE = MBB->livein_end(); LI != LE; ++LI) {
603 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
606 // Skip over empty initial indices.
607 if (getInstructionFromIndex(MIIndex) == 0)
608 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
610 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
612 DEBUG(dbgs() << MIIndex << "\t" << *MI);
613 if (MI->isDebugValue())
615 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
616 "Lost SlotIndex synchronization");
619 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
620 MachineOperand &MO = MI->getOperand(i);
622 // Collect register masks.
623 if (MO.isRegMask()) {
624 RegMaskSlots.push_back(MIIndex.getRegSlot());
625 RegMaskBits.push_back(MO.getRegMask());
629 if (!MO.isReg() || !MO.getReg())
632 // handle register defs - build intervals
634 handleRegisterDef(MBB, MI, MIIndex, MO, i);
635 else if (MO.isUndef())
636 UndefUses.push_back(MO.getReg());
639 // Move to the next instr slot.
640 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
643 // Compute the number of register mask instructions in this block.
644 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
645 RMB.second = RegMaskSlots.size() - RMB.first;;
648 // Create empty intervals for registers defined by implicit_def's (except
649 // for those implicit_def that define values which are liveout of their
651 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
652 unsigned UndefReg = UndefUses[i];
653 (void)getOrCreateInterval(UndefReg);
657 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
658 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
659 return new LiveInterval(reg, Weight);
663 //===----------------------------------------------------------------------===//
664 // Register Unit Liveness
665 //===----------------------------------------------------------------------===//
667 // Fixed interference typically comes from ABI boundaries: Function arguments
668 // and return values are passed in fixed registers, and so are exception
669 // pointers entering landing pads. Certain instructions require values to be
670 // present in specific registers. That is also represented through fixed
674 /// computeRegUnitInterval - Compute the live interval of a register unit, based
675 /// on the uses and defs of aliasing registers. The interval should be empty,
676 /// or contain only dead phi-defs from ABI blocks.
677 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
678 unsigned Unit = LI->reg;
680 assert(LRCalc && "LRCalc not initialized.");
681 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
683 // The physregs aliasing Unit are the roots and their super-registers.
684 // Create all values as dead defs before extending to uses. Note that roots
685 // may share super-registers. That's OK because createDeadDefs() is
686 // idempotent. It is very rare for a register unit to have multiple roots, so
687 // uniquing super-registers is probably not worthwhile.
688 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
689 unsigned Root = *Roots;
690 if (!MRI->reg_empty(Root))
691 LRCalc->createDeadDefs(LI, Root);
692 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
693 if (!MRI->reg_empty(*Supers))
694 LRCalc->createDeadDefs(LI, *Supers);
698 // Now extend LI to reach all uses.
699 // Ignore uses of reserved registers. We only track defs of those.
700 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
701 unsigned Root = *Roots;
702 if (!isReserved(Root) && !MRI->reg_empty(Root))
703 LRCalc->extendToUses(LI, Root);
704 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
705 unsigned Reg = *Supers;
706 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
707 LRCalc->extendToUses(LI, Reg);
713 /// computeLiveInRegUnits - Precompute the live ranges of any register units
714 /// that are live-in to an ABI block somewhere. Register values can appear
715 /// without a corresponding def when entering the entry block or a landing pad.
717 void LiveIntervals::computeLiveInRegUnits() {
718 RegUnitIntervals.resize(TRI->getNumRegUnits());
719 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
721 // Keep track of the intervals allocated.
722 SmallVector<LiveInterval*, 8> NewIntvs;
724 // Check all basic blocks for live-ins.
725 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
727 const MachineBasicBlock *MBB = MFI;
729 // We only care about ABI blocks: Entry + landing pads.
730 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
733 // Create phi-defs at Begin for all live-in registers.
734 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
735 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
736 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
737 LIE = MBB->livein_end(); LII != LIE; ++LII) {
738 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
739 unsigned Unit = *Units;
740 LiveInterval *Intv = RegUnitIntervals[Unit];
742 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
743 NewIntvs.push_back(Intv);
745 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
746 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
749 DEBUG(dbgs() << '\n');
751 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
753 // Compute the 'normal' part of the intervals.
754 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
755 computeRegUnitInterval(NewIntvs[i]);
759 /// shrinkToUses - After removing some uses of a register, shrink its live
760 /// range to just the remaining uses. This method does not compute reaching
761 /// defs for new uses, and it doesn't remove dead defs.
762 bool LiveIntervals::shrinkToUses(LiveInterval *li,
763 SmallVectorImpl<MachineInstr*> *dead) {
764 DEBUG(dbgs() << "Shrink: " << *li << '\n');
765 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
766 && "Can only shrink virtual registers");
767 // Find all the values used, including PHI kills.
768 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
770 // Blocks that have already been added to WorkList as live-out.
771 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
773 // Visit all instructions reading li->reg.
774 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
775 MachineInstr *UseMI = I.skipInstruction();) {
776 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
778 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
779 LiveRangeQuery LRQ(*li, Idx);
780 VNInfo *VNI = LRQ.valueIn();
782 // This shouldn't happen: readsVirtualRegister returns true, but there is
783 // no live value. It is likely caused by a target getting <undef> flags
785 DEBUG(dbgs() << Idx << '\t' << *UseMI
786 << "Warning: Instr claims to read non-existent value in "
790 // Special case: An early-clobber tied operand reads and writes the
791 // register one slot early.
792 if (VNInfo *DefVNI = LRQ.valueDefined())
795 WorkList.push_back(std::make_pair(Idx, VNI));
798 // Create a new live interval with only minimal live segments per def.
799 LiveInterval NewLI(li->reg, 0);
800 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
805 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
808 // Keep track of the PHIs that are in use.
809 SmallPtrSet<VNInfo*, 8> UsedPHIs;
811 // Extend intervals to reach all uses in WorkList.
812 while (!WorkList.empty()) {
813 SlotIndex Idx = WorkList.back().first;
814 VNInfo *VNI = WorkList.back().second;
816 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
817 SlotIndex BlockStart = getMBBStartIdx(MBB);
819 // Extend the live range for VNI to be live at Idx.
820 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
822 assert(ExtVNI == VNI && "Unexpected existing value number");
823 // Is this a PHIDef we haven't seen before?
824 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
826 // The PHI is live, make sure the predecessors are live-out.
827 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
828 PE = MBB->pred_end(); PI != PE; ++PI) {
829 if (!LiveOut.insert(*PI))
831 SlotIndex Stop = getMBBEndIdx(*PI);
832 // A predecessor is not required to have a live-out value for a PHI.
833 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
834 WorkList.push_back(std::make_pair(Stop, PVNI));
839 // VNI is live-in to MBB.
840 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
841 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
843 // Make sure VNI is live-out from the predecessors.
844 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
845 PE = MBB->pred_end(); PI != PE; ++PI) {
846 if (!LiveOut.insert(*PI))
848 SlotIndex Stop = getMBBEndIdx(*PI);
849 assert(li->getVNInfoBefore(Stop) == VNI &&
850 "Wrong value out of predecessor");
851 WorkList.push_back(std::make_pair(Stop, VNI));
855 // Handle dead values.
856 bool CanSeparate = false;
857 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
862 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
863 assert(LII != NewLI.end() && "Missing live range for PHI");
864 if (LII->end != VNI->def.getDeadSlot())
866 if (VNI->isPHIDef()) {
867 // This is a dead PHI. Remove it.
868 VNI->setIsUnused(true);
869 NewLI.removeRange(*LII);
870 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
873 // This is a dead def. Make sure the instruction knows.
874 MachineInstr *MI = getInstructionFromIndex(VNI->def);
875 assert(MI && "No instruction defining live value");
876 MI->addRegisterDead(li->reg, TRI);
877 if (dead && MI->allDefsAreDead()) {
878 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
884 // Move the trimmed ranges back.
885 li->ranges.swap(NewLI.ranges);
886 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
891 //===----------------------------------------------------------------------===//
892 // Register allocator hooks.
895 void LiveIntervals::addKillFlags() {
896 for (iterator I = begin(), E = end(); I != E; ++I) {
897 unsigned Reg = I->first;
898 if (TargetRegisterInfo::isPhysicalRegister(Reg))
900 if (MRI->reg_nodbg_empty(Reg))
902 LiveInterval *LI = I->second;
904 // Every instruction that kills Reg corresponds to a live range end point.
905 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
907 // A block index indicates an MBB edge.
908 if (RI->end.isBlock())
910 MachineInstr *MI = getInstructionFromIndex(RI->end);
913 MI->addRegisterKilled(Reg, NULL);
919 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
920 // A local live range must be fully contained inside the block, meaning it is
921 // defined and killed at instructions, not at block boundaries. It is not
922 // live in or or out of any block.
924 // It is technically possible to have a PHI-defined live range identical to a
925 // single block, but we are going to return false in that case.
927 SlotIndex Start = LI.beginIndex();
931 SlotIndex Stop = LI.endIndex();
935 // getMBBFromIndex doesn't need to search the MBB table when both indexes
936 // belong to proper instructions.
937 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
938 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
939 return MBB1 == MBB2 ? MBB1 : NULL;
943 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
944 // Limit the loop depth ridiculousness.
948 // The loop depth is used to roughly estimate the number of times the
949 // instruction is executed. Something like 10^d is simple, but will quickly
950 // overflow a float. This expression behaves like 10^d for small d, but is
951 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
952 // headroom before overflow.
953 // By the way, powf() might be unavailable here. For consistency,
954 // We may take pow(double,double).
955 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
957 return (isDef + isUse) * lc;
960 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
961 MachineInstr* startInst) {
962 LiveInterval& Interval = getOrCreateInterval(reg);
963 VNInfo* VN = Interval.getNextValue(
964 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
965 getVNInfoAllocator());
966 VN->setHasPHIKill(true);
968 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
969 getMBBEndIdx(startInst->getParent()), VN);
970 Interval.addRange(LR);
976 //===----------------------------------------------------------------------===//
977 // Register mask functions
978 //===----------------------------------------------------------------------===//
980 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
981 BitVector &UsableRegs) {
984 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
986 // Use a smaller arrays for local live ranges.
987 ArrayRef<SlotIndex> Slots;
988 ArrayRef<const uint32_t*> Bits;
989 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
990 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
991 Bits = getRegMaskBitsInBlock(MBB->getNumber());
993 Slots = getRegMaskSlots();
994 Bits = getRegMaskBits();
997 // We are going to enumerate all the register mask slots contained in LI.
998 // Start with a binary search of RegMaskSlots to find a starting point.
999 ArrayRef<SlotIndex>::iterator SlotI =
1000 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
1001 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
1003 // No slots in range, LI begins after the last call.
1009 assert(*SlotI >= LiveI->start);
1010 // Loop over all slots overlapping this segment.
1011 while (*SlotI < LiveI->end) {
1012 // *SlotI overlaps LI. Collect mask bits.
1014 // This is the first overlap. Initialize UsableRegs to all ones.
1016 UsableRegs.resize(TRI->getNumRegs(), true);
1019 // Remove usable registers clobbered by this mask.
1020 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1021 if (++SlotI == SlotE)
1024 // *SlotI is beyond the current LI segment.
1025 LiveI = LI.advanceTo(LiveI, *SlotI);
1028 // Advance SlotI until it overlaps.
1029 while (*SlotI < LiveI->start)
1030 if (++SlotI == SlotE)
1035 //===----------------------------------------------------------------------===//
1036 // IntervalUpdate class.
1037 //===----------------------------------------------------------------------===//
1039 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1040 class LiveIntervals::HMEditor {
1043 const MachineRegisterInfo& MRI;
1044 const TargetRegisterInfo& TRI;
1047 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1048 typedef DenseSet<IntRangePair> RangeSet;
1055 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1057 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1060 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1061 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1062 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1064 // Update intervals for all operands of MI from OldIdx to NewIdx.
1065 // This assumes that MI used to be at OldIdx, and now resides at
1067 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1068 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1070 // Collect the operands.
1071 RangeSet Entering, Internal, Exiting;
1072 bool hasRegMaskOp = false;
1073 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1075 // To keep the LiveRanges valid within an interval, move the ranges closest
1076 // to the destination first. This prevents ranges from overlapping, to that
1077 // APIs like removeRange still work.
1078 if (NewIdx < OldIdx) {
1079 moveAllEnteringFrom(OldIdx, Entering);
1080 moveAllInternalFrom(OldIdx, Internal);
1081 moveAllExitingFrom(OldIdx, Exiting);
1084 moveAllExitingFrom(OldIdx, Exiting);
1085 moveAllInternalFrom(OldIdx, Internal);
1086 moveAllEnteringFrom(OldIdx, Entering);
1090 updateRegMaskSlots(OldIdx);
1093 LIValidator validator;
1094 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1095 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1096 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1097 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1102 // Update intervals for all operands of MI to refer to BundleStart's
1104 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1105 if (MI == BundleStart)
1106 return; // Bundling instr with itself - nothing to do.
1108 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1109 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1110 "SlotIndex <-> Instruction mapping broken for MI");
1112 // Collect all ranges already in the bundle.
1113 MachineBasicBlock::instr_iterator BII(BundleStart);
1114 RangeSet Entering, Internal, Exiting;
1115 bool hasRegMaskOp = false;
1116 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1117 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1118 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1121 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1122 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1125 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1130 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1131 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1133 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1134 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1135 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1137 moveAllEnteringFromInto(OldIdx, Entering, BR);
1138 moveAllInternalFromInto(OldIdx, Internal, BR);
1139 moveAllExitingFromInto(OldIdx, Exiting, BR);
1143 LIValidator validator;
1144 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1145 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1146 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1147 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1156 DenseSet<const LiveInterval*> Checked, Bogus;
1158 void operator()(const IntRangePair& P) {
1159 const LiveInterval* LI = P.first;
1160 if (Checked.count(LI))
1165 SlotIndex LastEnd = LI->begin()->start;
1166 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1167 LRI != LRE; ++LRI) {
1168 const LiveRange& LR = *LRI;
1169 if (LastEnd > LR.start || LR.start >= LR.end)
1175 bool rangesOk() const {
1176 return Bogus.empty();
1181 // Collect IntRangePairs for all operands of MI that may need fixing.
1182 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1184 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1185 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1186 hasRegMaskOp = false;
1187 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1188 MOE = MI->operands_end();
1189 MOI != MOE; ++MOI) {
1190 const MachineOperand& MO = *MOI;
1192 if (MO.isRegMask()) {
1193 hasRegMaskOp = true;
1197 if (!MO.isReg() || MO.getReg() == 0)
1200 unsigned Reg = MO.getReg();
1202 // TODO: Currently we're skipping uses that are reserved or have no
1203 // interval, but we're not updating their kills. This should be
1205 if (!LIS.hasInterval(Reg) ||
1206 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1209 LiveInterval* LI = &LIS.getInterval(Reg);
1211 if (MO.readsReg()) {
1212 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1214 Entering.insert(std::make_pair(LI, LR));
1217 if (MO.isEarlyClobber()) {
1218 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1219 assert(LR != 0 && "No EC range?");
1220 if (LR->end > OldIdx.getDeadSlot())
1221 Exiting.insert(std::make_pair(LI, LR));
1223 Internal.insert(std::make_pair(LI, LR));
1224 } else if (MO.isDead()) {
1225 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1226 assert(LR != 0 && "No dead-def range?");
1227 Internal.insert(std::make_pair(LI, LR));
1229 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1230 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1231 "Non-dead-def should have live range exiting.");
1232 Exiting.insert(std::make_pair(LI, LR));
1238 // Collect IntRangePairs for all operands of MI that may need fixing.
1239 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1240 RangeSet& Exiting, SlotIndex MIStartIdx,
1241 SlotIndex MIEndIdx) {
1242 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1243 MOE = MI->operands_end();
1244 MOI != MOE; ++MOI) {
1245 const MachineOperand& MO = *MOI;
1246 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1247 if (!MO.isReg() || MO.getReg() == 0)
1250 unsigned Reg = MO.getReg();
1252 // TODO: Currently we're skipping uses that are reserved or have no
1253 // interval, but we're not updating their kills. This should be
1255 if (!LIS.hasInterval(Reg) ||
1256 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1259 LiveInterval* LI = &LIS.getInterval(Reg);
1261 if (MO.readsReg()) {
1262 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1264 Entering.insert(std::make_pair(LI, LR));
1267 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
1268 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1269 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1270 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1271 Exiting.insert(std::make_pair(LI, LR));
1276 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
1279 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1281 LiveInterval* LI = EI->first;
1282 LiveRange* LR = EI->second;
1283 BR[LI->reg].Use = LR;
1286 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1288 LiveInterval* LI = II->first;
1289 LiveRange* LR = II->second;
1290 if (LR->end.isDead()) {
1291 BR[LI->reg].Dead = LR;
1293 BR[LI->reg].EC = LR;
1297 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1299 LiveInterval* LI = EI->first;
1300 LiveRange* LR = EI->second;
1301 BR[LI->reg].Def = LR;
1307 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1308 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1309 if (!OldKillMI->killsRegister(reg))
1310 return; // Bail out if we don't have kill flags on the old register.
1311 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1312 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1313 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1314 OldKillMI->clearRegisterKills(reg, &TRI);
1315 NewKillMI->addRegisterKilled(reg, &TRI);
1318 void updateRegMaskSlots(SlotIndex OldIdx) {
1319 SmallVectorImpl<SlotIndex>::iterator RI =
1320 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1322 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1324 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1325 "RegSlots out of order. Did you move one call across another?");
1328 // Return the last use of reg between NewIdx and OldIdx.
1329 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1330 SlotIndex LastUse = NewIdx;
1331 for (MachineRegisterInfo::use_nodbg_iterator
1332 UI = MRI.use_nodbg_begin(Reg),
1333 UE = MRI.use_nodbg_end();
1334 UI != UE; UI.skipInstruction()) {
1335 const MachineInstr* MI = &*UI;
1336 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1337 if (InstSlot > LastUse && InstSlot < OldIdx)
1343 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1344 LiveInterval* LI = P.first;
1345 LiveRange* LR = P.second;
1346 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1349 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1350 if (LastUse != NewIdx)
1351 moveKillFlags(LI->reg, NewIdx, LastUse);
1352 LR->end = LastUse.getRegSlot();
1355 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1356 LiveInterval* LI = P.first;
1357 LiveRange* LR = P.second;
1358 // Extend the LiveRange if NewIdx is past the end.
1359 if (NewIdx > LR->end) {
1360 // Move kill flags if OldIdx was not originally the end
1361 // (otherwise LR->end points to an invalid slot).
1362 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1363 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1364 moveKillFlags(LI->reg, LR->end, NewIdx);
1366 LR->end = NewIdx.getRegSlot();
1370 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1371 bool GoingUp = NewIdx < OldIdx;
1374 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1376 moveEnteringUpFrom(OldIdx, *EI);
1378 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1380 moveEnteringDownFrom(OldIdx, *EI);
1384 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1385 LiveInterval* LI = P.first;
1386 LiveRange* LR = P.second;
1387 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1388 LR->end <= OldIdx.getDeadSlot() &&
1389 "Range should be internal to OldIdx.");
1391 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1392 Tmp.valno->def = Tmp.start;
1393 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1394 LI->removeRange(*LR);
1398 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1399 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1401 moveInternalFrom(OldIdx, *II);
1404 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1405 LiveRange* LR = P.second;
1406 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1407 "Range should start in OldIdx.");
1408 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1409 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1410 LR->start = NewStart;
1411 LR->valno->def = NewStart;
1414 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1415 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1417 moveExitingFrom(OldIdx, *EI);
1420 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1422 LiveInterval* LI = P.first;
1423 LiveRange* LR = P.second;
1424 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1426 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1427 "Def in bundle should be def range.");
1428 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1429 "If bundle has use for this reg it should be LR.");
1430 BR[LI->reg].Use = LR;
1434 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1435 moveKillFlags(LI->reg, OldIdx, LastUse);
1437 if (LR->start < NewIdx) {
1438 // Becoming a new entering range.
1439 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1440 "Bundle shouldn't be re-defining reg mid-range.");
1441 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1442 "Bundle shouldn't have different use range for same reg.");
1443 LR->end = LastUse.getRegSlot();
1444 BR[LI->reg].Use = LR;
1446 // Becoming a new Dead-def.
1447 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1448 "Live range starting at unexpected slot.");
1449 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1450 assert(BR[LI->reg].Dead == 0 &&
1451 "Can't have def and dead def of same reg in a bundle.");
1452 LR->end = LastUse.getDeadSlot();
1453 BR[LI->reg].Dead = BR[LI->reg].Def;
1454 BR[LI->reg].Def = 0;
1458 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1460 LiveInterval* LI = P.first;
1461 LiveRange* LR = P.second;
1462 if (NewIdx > LR->end) {
1463 // Range extended to bundle. Add to bundle uses.
1464 // Note: Currently adds kill flags to bundle start.
1465 assert(BR[LI->reg].Use == 0 &&
1466 "Bundle already has use range for reg.");
1467 moveKillFlags(LI->reg, LR->end, NewIdx);
1468 LR->end = NewIdx.getRegSlot();
1469 BR[LI->reg].Use = LR;
1471 assert(BR[LI->reg].Use != 0 &&
1472 "Bundle should already have a use range for reg.");
1476 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1478 bool GoingUp = NewIdx < OldIdx;
1481 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1483 moveEnteringUpFromInto(OldIdx, *EI, BR);
1485 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1487 moveEnteringDownFromInto(OldIdx, *EI, BR);
1491 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1493 // TODO: Sane rules for moving ranges into bundles.
1496 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1498 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1500 moveInternalFromInto(OldIdx, *II, BR);
1503 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1505 LiveInterval* LI = P.first;
1506 LiveRange* LR = P.second;
1508 assert(LR->start.isRegister() &&
1509 "Don't know how to merge exiting ECs into bundles yet.");
1511 if (LR->end > NewIdx.getDeadSlot()) {
1512 // This range is becoming an exiting range on the bundle.
1513 // If there was an old dead-def of this reg, delete it.
1514 if (BR[LI->reg].Dead != 0) {
1515 LI->removeRange(*BR[LI->reg].Dead);
1516 BR[LI->reg].Dead = 0;
1518 assert(BR[LI->reg].Def == 0 &&
1519 "Can't have two defs for the same variable exiting a bundle.");
1520 LR->start = NewIdx.getRegSlot();
1521 LR->valno->def = LR->start;
1522 BR[LI->reg].Def = LR;
1524 // This range is becoming internal to the bundle.
1525 assert(LR->end == NewIdx.getRegSlot() &&
1526 "Can't bundle def whose kill is before the bundle");
1527 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1528 // Already have a def for this. Just delete range.
1529 LI->removeRange(*LR);
1531 // Make range dead, record.
1532 LR->end = NewIdx.getDeadSlot();
1533 BR[LI->reg].Dead = LR;
1534 assert(BR[LI->reg].Use == LR &&
1535 "Range becoming dead should currently be use.");
1537 // In both cases the range is no longer a use on the bundle.
1538 BR[LI->reg].Use = 0;
1542 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1544 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1546 moveExitingFromInto(OldIdx, *EI, BR);
1551 void LiveIntervals::handleMove(MachineInstr* MI) {
1552 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1553 Indexes->removeMachineInstrFromMaps(MI);
1554 SlotIndex NewIndex = MI->isInsideBundle() ?
1555 Indexes->getInstructionIndex(MI) :
1556 Indexes->insertMachineInstrInMaps(MI);
1557 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1558 OldIndex < getMBBEndIdx(MI->getParent()) &&
1559 "Cannot handle moves across basic block boundaries.");
1560 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1562 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1563 HME.moveAllRangesFrom(MI, OldIndex);
1566 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
1567 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1568 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1569 HME.moveAllRangesInto(MI, BundleStart);