1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
70 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addPreserved<AliasAnalysis>();
74 // LiveVariables isn't really required by this analysis, it is only required
75 // here to make sure it is live during TwoAddressInstructionPass and
76 // PHIElimination. This is temporary.
77 AU.addRequired<LiveVariables>();
78 AU.addPreserved<LiveVariables>();
79 AU.addPreservedID(MachineLoopInfoID);
80 AU.addRequiredTransitiveID(MachineDominatorsID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreserved<SlotIndexes>();
83 AU.addRequiredTransitive<SlotIndexes>();
84 MachineFunctionPass::getAnalysisUsage(AU);
87 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
88 DomTree(nullptr), LRCalc(nullptr) {
89 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
92 LiveIntervals::~LiveIntervals() {
96 void LiveIntervals::releaseMemory() {
97 // Free the live intervals themselves.
98 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
99 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
100 VirtRegIntervals.clear();
101 RegMaskSlots.clear();
103 RegMaskBlocks.clear();
105 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
106 delete RegUnitRanges[i];
107 RegUnitRanges.clear();
109 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
110 VNInfoAllocator.Reset();
113 /// runOnMachineFunction - calculates LiveIntervals
115 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
117 MRI = &MF->getRegInfo();
118 TRI = MF->getSubtarget().getRegisterInfo();
119 TII = MF->getSubtarget().getInstrInfo();
120 AA = &getAnalysis<AliasAnalysis>();
121 Indexes = &getAnalysis<SlotIndexes>();
122 DomTree = &getAnalysis<MachineDominatorTree>();
124 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
125 MRI->enableSubRegLiveness(true);
128 LRCalc = new LiveRangeCalc();
130 // Allocate space for all virtual registers.
131 VirtRegIntervals.resize(MRI->getNumVirtRegs());
135 computeLiveInRegUnits();
137 if (EnablePrecomputePhysRegs) {
138 // For stress testing, precompute live ranges of all physical register
139 // units, including reserved registers.
140 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
147 /// print - Implement the dump method.
148 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
149 OS << "********** INTERVALS **********\n";
151 // Dump the regunits.
152 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
153 if (LiveRange *LR = RegUnitRanges[i])
154 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
156 // Dump the virtregs.
157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
158 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
159 if (hasInterval(Reg))
160 OS << getInterval(Reg) << '\n';
164 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
165 OS << ' ' << RegMaskSlots[i];
171 void LiveIntervals::printInstrs(raw_ostream &OS) const {
172 OS << "********** MACHINEINSTRS **********\n";
173 MF->print(OS, Indexes);
176 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
177 void LiveIntervals::dumpInstrs() const {
182 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
183 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
184 llvm::huge_valf : 0.0F;
185 return new LiveInterval(reg, Weight);
189 /// computeVirtRegInterval - Compute the live interval of a virtual register,
190 /// based on defs and uses.
191 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
192 assert(LRCalc && "LRCalc not initialized.");
193 assert(LI.empty() && "Should only compute empty intervals.");
194 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
195 LRCalc->createDeadDefs(LI);
196 LRCalc->extendToUses(LI);
197 computeDeadValues(LI, LI);
200 void LiveIntervals::computeVirtRegs() {
201 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
202 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
203 if (MRI->reg_nodbg_empty(Reg))
205 createAndComputeVirtRegInterval(Reg);
209 void LiveIntervals::computeRegMasks() {
210 RegMaskBlocks.resize(MF->getNumBlockIDs());
212 // Find all instructions with regmask operands.
213 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
215 MachineBasicBlock *MBB = MBBI;
216 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
217 RMB.first = RegMaskSlots.size();
218 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
220 for (MIOperands MO(MI); MO.isValid(); ++MO) {
221 if (!MO->isRegMask())
223 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
224 RegMaskBits.push_back(MO->getRegMask());
226 // Compute the number of register mask instructions in this block.
227 RMB.second = RegMaskSlots.size() - RMB.first;
231 //===----------------------------------------------------------------------===//
232 // Register Unit Liveness
233 //===----------------------------------------------------------------------===//
235 // Fixed interference typically comes from ABI boundaries: Function arguments
236 // and return values are passed in fixed registers, and so are exception
237 // pointers entering landing pads. Certain instructions require values to be
238 // present in specific registers. That is also represented through fixed
242 /// computeRegUnitInterval - Compute the live range of a register unit, based
243 /// on the uses and defs of aliasing registers. The range should be empty,
244 /// or contain only dead phi-defs from ABI blocks.
245 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
246 assert(LRCalc && "LRCalc not initialized.");
247 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
249 // The physregs aliasing Unit are the roots and their super-registers.
250 // Create all values as dead defs before extending to uses. Note that roots
251 // may share super-registers. That's OK because createDeadDefs() is
252 // idempotent. It is very rare for a register unit to have multiple roots, so
253 // uniquing super-registers is probably not worthwhile.
254 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
255 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
256 Supers.isValid(); ++Supers) {
257 if (!MRI->reg_empty(*Supers))
258 LRCalc->createDeadDefs(LR, *Supers);
262 // Now extend LR to reach all uses.
263 // Ignore uses of reserved registers. We only track defs of those.
264 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
265 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
266 Supers.isValid(); ++Supers) {
267 unsigned Reg = *Supers;
268 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
269 LRCalc->extendToUses(LR, Reg);
275 /// computeLiveInRegUnits - Precompute the live ranges of any register units
276 /// that are live-in to an ABI block somewhere. Register values can appear
277 /// without a corresponding def when entering the entry block or a landing pad.
279 void LiveIntervals::computeLiveInRegUnits() {
280 RegUnitRanges.resize(TRI->getNumRegUnits());
281 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
283 // Keep track of the live range sets allocated.
284 SmallVector<unsigned, 8> NewRanges;
286 // Check all basic blocks for live-ins.
287 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
289 const MachineBasicBlock *MBB = MFI;
291 // We only care about ABI blocks: Entry + landing pads.
292 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
295 // Create phi-defs at Begin for all live-in registers.
296 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
297 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
298 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
299 LIE = MBB->livein_end(); LII != LIE; ++LII) {
300 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
301 unsigned Unit = *Units;
302 LiveRange *LR = RegUnitRanges[Unit];
304 LR = RegUnitRanges[Unit] = new LiveRange();
305 NewRanges.push_back(Unit);
307 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
309 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
312 DEBUG(dbgs() << '\n');
314 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
316 // Compute the 'normal' part of the ranges.
317 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
318 unsigned Unit = NewRanges[i];
319 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
324 static void createSegmentsForValues(LiveRange &LR,
325 iterator_range<LiveInterval::vni_iterator> VNIs) {
326 for (auto VNI : VNIs) {
329 SlotIndex Def = VNI->def;
330 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
334 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
336 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
337 ShrinkToUsesWorkList &WorkList,
338 const LiveRange &OldRange) {
339 // Keep track of the PHIs that are in use.
340 SmallPtrSet<VNInfo*, 8> UsedPHIs;
341 // Blocks that have already been added to WorkList as live-out.
342 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
344 // Extend intervals to reach all uses in WorkList.
345 while (!WorkList.empty()) {
346 SlotIndex Idx = WorkList.back().first;
347 VNInfo *VNI = WorkList.back().second;
349 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
350 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
352 // Extend the live range for VNI to be live at Idx.
353 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
354 assert(ExtVNI == VNI && "Unexpected existing value number");
356 // Is this a PHIDef we haven't seen before?
357 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
358 !UsedPHIs.insert(VNI).second)
360 // The PHI is live, make sure the predecessors are live-out.
361 for (auto &Pred : MBB->predecessors()) {
362 if (!LiveOut.insert(Pred).second)
364 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
365 // A predecessor is not required to have a live-out value for a PHI.
366 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
367 WorkList.push_back(std::make_pair(Stop, PVNI));
372 // VNI is live-in to MBB.
373 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
374 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
376 // Make sure VNI is live-out from the predecessors.
377 for (auto &Pred : MBB->predecessors()) {
378 if (!LiveOut.insert(Pred).second)
380 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
381 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
382 "Wrong value out of predecessor");
383 WorkList.push_back(std::make_pair(Stop, VNI));
388 /// shrinkToUses - After removing some uses of a register, shrink its live
389 /// range to just the remaining uses. This method does not compute reaching
390 /// defs for new uses, and it doesn't remove dead defs.
391 bool LiveIntervals::shrinkToUses(LiveInterval *li,
392 SmallVectorImpl<MachineInstr*> *dead) {
393 DEBUG(dbgs() << "Shrink: " << *li << '\n');
394 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
395 && "Can only shrink virtual registers");
397 // Shrink subregister live ranges.
398 for (LiveInterval::SubRange &S : li->subranges()) {
399 shrinkToUses(S, li->reg);
402 // Find all the values used, including PHI kills.
403 ShrinkToUsesWorkList WorkList;
405 // Visit all instructions reading li->reg.
406 for (MachineRegisterInfo::reg_instr_iterator
407 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
409 MachineInstr *UseMI = &*(I++);
410 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
412 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
413 LiveQueryResult LRQ = li->Query(Idx);
414 VNInfo *VNI = LRQ.valueIn();
416 // This shouldn't happen: readsVirtualRegister returns true, but there is
417 // no live value. It is likely caused by a target getting <undef> flags
419 DEBUG(dbgs() << Idx << '\t' << *UseMI
420 << "Warning: Instr claims to read non-existent value in "
424 // Special case: An early-clobber tied operand reads and writes the
425 // register one slot early.
426 if (VNInfo *DefVNI = LRQ.valueDefined())
429 WorkList.push_back(std::make_pair(Idx, VNI));
432 // Create new live ranges with only minimal live segments per def.
434 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
435 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
437 // Handle dead values.
439 computeDeadValues(NewLR, *li, &CanSeparate, li->reg, dead);
441 // Move the trimmed segments back.
442 li->segments.swap(NewLR.segments);
443 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
447 void LiveIntervals::computeDeadValues(LiveRange &Segments, LiveRange &LR,
448 bool *CanSeparateRes, unsigned Reg,
449 SmallVectorImpl<MachineInstr*> *dead) {
450 bool CanSeparate = false;
451 for (auto VNI : LR.valnos) {
454 LiveRange::iterator LRI = Segments.FindSegmentContaining(VNI->def);
455 assert(LRI != Segments.end() && "Missing segment for PHI");
456 if (LRI->end != VNI->def.getDeadSlot())
458 if (VNI->isPHIDef()) {
459 // This is a dead PHI. Remove it.
461 Segments.removeSegment(LRI->start, LRI->end);
462 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
464 } else if (dead != nullptr) {
465 // This is a dead def. Make sure the instruction knows.
466 MachineInstr *MI = getInstructionFromIndex(VNI->def);
467 assert(MI && "No instruction defining live value");
468 MI->addRegisterDead(Reg, TRI);
469 if (dead && MI->allDefsAreDead()) {
470 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
475 if (CanSeparateRes != nullptr)
476 *CanSeparateRes = CanSeparate;
479 bool LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
481 DEBUG(dbgs() << "Shrink: " << SR << '\n');
482 assert(TargetRegisterInfo::isVirtualRegister(Reg)
483 && "Can only shrink virtual registers");
484 // Find all the values used, including PHI kills.
485 ShrinkToUsesWorkList WorkList;
487 // Visit all instructions reading Reg.
489 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
490 MachineInstr *UseMI = MO.getParent();
491 if (UseMI->isDebugValue())
493 // Maybe the operand is for a subregister we don't care about.
494 unsigned SubReg = MO.getSubReg();
496 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
497 if ((SubRegMask & SR.LaneMask) == 0)
500 // We only need to visit each instruction once.
501 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
506 LiveQueryResult LRQ = SR.Query(Idx);
507 VNInfo *VNI = LRQ.valueIn();
508 // For Subranges it is possible that only undef values are left in that
509 // part of the subregister, so there is no real liverange at the use
513 // Special case: An early-clobber tied operand reads and writes the
514 // register one slot early.
515 if (VNInfo *DefVNI = LRQ.valueDefined())
518 WorkList.push_back(std::make_pair(Idx, VNI));
521 // Create a new live ranges with only minimal live segments per def.
523 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
524 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
526 // Handle dead values.
528 computeDeadValues(NewLR, SR, &CanSeparate);
530 // Move the trimmed ranges back.
531 SR.segments.swap(NewLR.segments);
532 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
536 void LiveIntervals::extendToIndices(LiveRange &LR,
537 ArrayRef<SlotIndex> Indices) {
538 assert(LRCalc && "LRCalc not initialized.");
539 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
540 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
541 LRCalc->extend(LR, Indices[i]);
544 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
545 SmallVectorImpl<SlotIndex> *EndPoints) {
546 LiveQueryResult LRQ = LR.Query(Kill);
547 VNInfo *VNI = LRQ.valueOutOrDead();
551 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
552 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
554 // If VNI isn't live out from KillMBB, the value is trivially pruned.
555 if (LRQ.endPoint() < MBBEnd) {
556 LR.removeSegment(Kill, LRQ.endPoint());
557 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
561 // VNI is live out of KillMBB.
562 LR.removeSegment(Kill, MBBEnd);
563 if (EndPoints) EndPoints->push_back(MBBEnd);
565 // Find all blocks that are reachable from KillMBB without leaving VNI's live
566 // range. It is possible that KillMBB itself is reachable, so start a DFS
567 // from each successor.
568 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
570 for (MachineBasicBlock::succ_iterator
571 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
572 SuccI != SuccE; ++SuccI) {
573 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
574 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
576 MachineBasicBlock *MBB = *I;
578 // Check if VNI is live in to MBB.
579 SlotIndex MBBStart, MBBEnd;
580 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
581 LiveQueryResult LRQ = LR.Query(MBBStart);
582 if (LRQ.valueIn() != VNI) {
583 // This block isn't part of the VNI segment. Prune the search.
588 // Prune the search if VNI is killed in MBB.
589 if (LRQ.endPoint() < MBBEnd) {
590 LR.removeSegment(MBBStart, LRQ.endPoint());
591 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
596 // VNI is live through MBB.
597 LR.removeSegment(MBBStart, MBBEnd);
598 if (EndPoints) EndPoints->push_back(MBBEnd);
604 void LiveIntervals::pruneValue(LiveInterval &LI, SlotIndex Kill,
605 SmallVectorImpl<SlotIndex> *EndPoints) {
606 pruneValue((LiveRange&)LI, Kill, EndPoints);
608 for (LiveInterval::SubRange &SR : LI.subranges()) {
609 pruneValue(SR, Kill, nullptr);
613 //===----------------------------------------------------------------------===//
614 // Register allocator hooks.
617 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
618 // Keep track of regunit ranges.
619 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
621 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
622 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
623 if (MRI->reg_nodbg_empty(Reg))
625 LiveInterval *LI = &getInterval(Reg);
629 // Find the regunit intervals for the assigned register. They may overlap
630 // the virtual register live range, cancelling any kills.
632 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
634 LiveRange &RURanges = getRegUnit(*Units);
635 if (RURanges.empty())
637 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
640 // Every instruction that kills Reg corresponds to a segment range end
642 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
644 // A block index indicates an MBB edge.
645 if (RI->end.isBlock())
647 MachineInstr *MI = getInstructionFromIndex(RI->end);
651 // Check if any of the regunits are live beyond the end of RI. That could
652 // happen when a physreg is defined as a copy of a virtreg:
654 // %EAX = COPY %vreg5
655 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
658 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
659 bool CancelKill = false;
660 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
661 LiveRange &RRanges = *RU[u].first;
662 LiveRange::iterator &I = RU[u].second;
663 if (I == RRanges.end())
665 I = RRanges.advanceTo(I, RI->end);
666 if (I == RRanges.end() || I->start >= RI->end)
668 // I is overlapping RI.
673 // If an instruction writes to a subregister, a new segment starts in the
674 // LiveInterval. In this case adding Kill-Flags is incorrect if no
675 // super registers defs/uses are appended to the instruction which is
676 // what we do when subregister liveness tracking is enabled.
677 if (MRI->tracksSubRegLiveness()) {
678 // Next segment has to be adjacent in the subregister write case.
679 LiveRange::iterator N = std::next(RI);
680 if (N != LI->end() && N->start == RI->end) {
681 // See if we have a partial write operand
682 bool IsFullWrite = false;
683 for (MachineInstr::const_mop_iterator MOp = MI->operands_begin(),
684 MOpE = MI->operands_end(); MOp != MOpE; ++MOp) {
685 if (MOp->isReg() && !MOp->isDef() && MOp->getReg() == Reg
686 && MOp->getSubReg() == 0) {
697 MI->clearRegisterKills(Reg, nullptr);
699 MI->addRegisterKilled(Reg, nullptr);
705 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
706 // A local live range must be fully contained inside the block, meaning it is
707 // defined and killed at instructions, not at block boundaries. It is not
708 // live in or or out of any block.
710 // It is technically possible to have a PHI-defined live range identical to a
711 // single block, but we are going to return false in that case.
713 SlotIndex Start = LI.beginIndex();
717 SlotIndex Stop = LI.endIndex();
721 // getMBBFromIndex doesn't need to search the MBB table when both indexes
722 // belong to proper instructions.
723 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
724 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
725 return MBB1 == MBB2 ? MBB1 : nullptr;
729 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
730 for (const VNInfo *PHI : LI.valnos) {
731 if (PHI->isUnused() || !PHI->isPHIDef())
733 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
734 // Conservatively return true instead of scanning huge predecessor lists.
735 if (PHIMBB->pred_size() > 100)
737 for (MachineBasicBlock::const_pred_iterator
738 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
739 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
746 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
747 const MachineBlockFrequencyInfo *MBFI,
748 const MachineInstr *MI) {
749 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
750 const float Scale = 1.0f / MBFI->getEntryFreq();
751 return (isDef + isUse) * (Freq.getFrequency() * Scale);
755 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
756 LiveInterval& Interval = createEmptyInterval(reg);
757 VNInfo* VN = Interval.getNextValue(
758 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
759 getVNInfoAllocator());
760 LiveRange::Segment S(
761 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
762 getMBBEndIdx(startInst->getParent()), VN);
763 Interval.addSegment(S);
769 //===----------------------------------------------------------------------===//
770 // Register mask functions
771 //===----------------------------------------------------------------------===//
773 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
774 BitVector &UsableRegs) {
777 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
779 // Use a smaller arrays for local live ranges.
780 ArrayRef<SlotIndex> Slots;
781 ArrayRef<const uint32_t*> Bits;
782 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
783 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
784 Bits = getRegMaskBitsInBlock(MBB->getNumber());
786 Slots = getRegMaskSlots();
787 Bits = getRegMaskBits();
790 // We are going to enumerate all the register mask slots contained in LI.
791 // Start with a binary search of RegMaskSlots to find a starting point.
792 ArrayRef<SlotIndex>::iterator SlotI =
793 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
794 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
796 // No slots in range, LI begins after the last call.
802 assert(*SlotI >= LiveI->start);
803 // Loop over all slots overlapping this segment.
804 while (*SlotI < LiveI->end) {
805 // *SlotI overlaps LI. Collect mask bits.
807 // This is the first overlap. Initialize UsableRegs to all ones.
809 UsableRegs.resize(TRI->getNumRegs(), true);
812 // Remove usable registers clobbered by this mask.
813 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
814 if (++SlotI == SlotE)
817 // *SlotI is beyond the current LI segment.
818 LiveI = LI.advanceTo(LiveI, *SlotI);
821 // Advance SlotI until it overlaps.
822 while (*SlotI < LiveI->start)
823 if (++SlotI == SlotE)
828 //===----------------------------------------------------------------------===//
829 // IntervalUpdate class.
830 //===----------------------------------------------------------------------===//
832 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
833 class LiveIntervals::HMEditor {
836 const MachineRegisterInfo& MRI;
837 const TargetRegisterInfo& TRI;
840 SmallPtrSet<LiveRange*, 8> Updated;
844 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
845 const TargetRegisterInfo& TRI,
846 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
847 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
848 UpdateFlags(UpdateFlags) {}
850 // FIXME: UpdateFlags is a workaround that creates live intervals for all
851 // physregs, even those that aren't needed for regalloc, in order to update
852 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
853 // flags, and postRA passes will use a live register utility instead.
854 LiveRange *getRegUnitLI(unsigned Unit) {
856 return &LIS.getRegUnit(Unit);
857 return LIS.getCachedRegUnit(Unit);
860 /// Update all live ranges touched by MI, assuming a move from OldIdx to
862 void updateAllRanges(MachineInstr *MI) {
863 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
864 bool hasRegMask = false;
865 for (MIOperands MO(MI); MO.isValid(); ++MO) {
870 // Aggressively clear all kill flags.
871 // They are reinserted by VirtRegRewriter.
873 MO->setIsKill(false);
875 unsigned Reg = MO->getReg();
878 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
879 LiveInterval &LI = LIS.getInterval(Reg);
880 if (LI.hasSubRanges()) {
881 unsigned SubReg = MO->getSubReg();
882 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
883 for (LiveInterval::SubRange &S : LI.subranges()) {
884 if ((S.LaneMask & LaneMask) == 0)
886 updateRange(S, Reg, S.LaneMask);
889 updateRange(LI, Reg, 0);
893 // For physregs, only update the regunits that actually have a
894 // precomputed live range.
895 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
896 if (LiveRange *LR = getRegUnitLI(*Units))
897 updateRange(*LR, *Units, 0);
900 updateRegMaskSlots();
904 /// Update a single live range, assuming an instruction has been moved from
905 /// OldIdx to NewIdx.
906 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
907 if (!Updated.insert(&LR).second)
911 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
912 dbgs() << PrintReg(Reg);
914 dbgs() << format(" L%04X", LaneMask);
916 dbgs() << PrintRegUnit(Reg, &TRI);
918 dbgs() << ":\t" << LR << '\n';
920 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
923 handleMoveUp(LR, Reg, LaneMask);
924 DEBUG(dbgs() << " -->\t" << LR << '\n');
928 /// Update LR to reflect an instruction has been moved downwards from OldIdx
931 /// 1. Live def at OldIdx:
932 /// Move def to NewIdx, assert endpoint after NewIdx.
934 /// 2. Live def at OldIdx, killed at NewIdx:
935 /// Change to dead def at NewIdx.
936 /// (Happens when bundling def+kill together).
938 /// 3. Dead def at OldIdx:
939 /// Move def to NewIdx, possibly across another live value.
941 /// 4. Def at OldIdx AND at NewIdx:
942 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
943 /// (Happens when bundling multiple defs together).
945 /// 5. Value read at OldIdx, killed before NewIdx:
946 /// Extend kill to NewIdx.
948 void handleMoveDown(LiveRange &LR) {
949 // First look for a kill at OldIdx.
950 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
951 LiveRange::iterator E = LR.end();
952 // Is LR even live at OldIdx?
953 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
956 // Handle a live-in value.
957 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
958 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
959 // If the live-in value already extends to NewIdx, there is nothing to do.
960 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
962 // Aggressively remove all kill flags from the old kill point.
963 // Kill flags shouldn't be used while live intervals exist, they will be
964 // reinserted by VirtRegRewriter.
965 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
966 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
967 if (MO->isReg() && MO->isUse())
968 MO->setIsKill(false);
969 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
970 // overlapping ranges. Case 5 above.
971 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
972 // If this was a kill, there may also be a def. Otherwise we're done.
978 // Check for a def at OldIdx.
979 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
981 // We have a def at OldIdx.
982 VNInfo *DefVNI = I->valno;
983 assert(DefVNI->def == I->start && "Inconsistent def");
984 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
985 // If the defined value extends beyond NewIdx, just move the def down.
986 // This is case 1 above.
987 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
988 I->start = DefVNI->def;
991 // The remaining possibilities are now:
992 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
993 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
994 // In either case, it is possible that there is an existing def at NewIdx.
995 assert((I->end == OldIdx.getDeadSlot() ||
996 SlotIndex::isSameInstr(I->end, NewIdx)) &&
997 "Cannot move def below kill");
998 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
999 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1000 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1001 // coalesced into that value.
1002 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1003 LR.removeValNo(DefVNI);
1006 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1007 // If the def at OldIdx was dead, we allow it to be moved across other LR
1008 // values. The new range should be placed immediately before NewI, move any
1009 // intermediate ranges up.
1010 assert(NewI != I && "Inconsistent iterators");
1011 std::copy(std::next(I), NewI, I);
1013 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1016 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1019 /// 1. Live def at OldIdx:
1020 /// Hoist def to NewIdx.
1022 /// 2. Dead def at OldIdx:
1023 /// Hoist def+end to NewIdx, possibly move across other values.
1025 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1026 /// Remove value defined at OldIdx, coalescing it with existing value.
1028 /// 4. Live def at OldIdx AND existing def at NewIdx:
1029 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1030 /// (Happens when bundling multiple defs together).
1032 /// 5. Value killed at OldIdx:
1033 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1036 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1037 // First look for a kill at OldIdx.
1038 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1039 LiveRange::iterator E = LR.end();
1040 // Is LR even live at OldIdx?
1041 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1044 // Handle a live-in value.
1045 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1046 // If the live-in value isn't killed here, there is nothing to do.
1047 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1049 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1050 // another use, we need to search for that use. Case 5 above.
1051 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1053 // If OldIdx also defines a value, there couldn't have been another use.
1054 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1055 // No def, search for the new kill.
1056 // This can never be an early clobber kill since there is no def.
1057 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1062 // Now deal with the def at OldIdx.
1063 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1064 VNInfo *DefVNI = I->valno;
1065 assert(DefVNI->def == I->start && "Inconsistent def");
1066 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1068 // Check for an existing def at NewIdx.
1069 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1070 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1071 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1072 // There is an existing def at NewIdx.
1073 if (I->end.isDead()) {
1074 // Case 3: Remove the dead def at OldIdx.
1075 LR.removeValNo(DefVNI);
1078 // Case 4: Replace def at NewIdx with live def at OldIdx.
1079 I->start = DefVNI->def;
1080 LR.removeValNo(NewI->valno);
1084 // There is no existing def at NewIdx. Hoist DefVNI.
1085 if (!I->end.isDead()) {
1086 // Leave the end point of a live def.
1087 I->start = DefVNI->def;
1091 // DefVNI is a dead def. It may have been moved across other values in LR,
1092 // so move I up to NewI. Slide [NewI;I) down one position.
1093 std::copy_backward(NewI, I, std::next(I));
1094 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1097 void updateRegMaskSlots() {
1098 SmallVectorImpl<SlotIndex>::iterator RI =
1099 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1101 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1102 "No RegMask at OldIdx.");
1103 *RI = NewIdx.getRegSlot();
1104 assert((RI == LIS.RegMaskSlots.begin() ||
1105 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1106 "Cannot move regmask instruction above another call");
1107 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1108 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1109 "Cannot move regmask instruction below another call");
1112 // Return the last use of reg between NewIdx and OldIdx.
1113 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1115 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1116 SlotIndex LastUse = NewIdx;
1117 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1118 unsigned SubReg = MO.getSubReg();
1119 if (SubReg != 0 && LaneMask != 0
1120 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1123 const MachineInstr *MI = MO.getParent();
1124 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1125 if (InstSlot > LastUse && InstSlot < OldIdx)
1131 // This is a regunit interval, so scanning the use list could be very
1132 // expensive. Scan upwards from OldIdx instead.
1133 assert(NewIdx < OldIdx && "Expected upwards move");
1134 SlotIndexes *Indexes = LIS.getSlotIndexes();
1135 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1137 // OldIdx may not correspond to an instruction any longer, so set MII to
1138 // point to the next instruction after OldIdx, or MBB->end().
1139 MachineBasicBlock::iterator MII = MBB->end();
1140 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1141 Indexes->getNextNonNullIndex(OldIdx)))
1142 if (MI->getParent() == MBB)
1145 MachineBasicBlock::iterator Begin = MBB->begin();
1146 while (MII != Begin) {
1147 if ((--MII)->isDebugValue())
1149 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1151 // Stop searching when NewIdx is reached.
1152 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1155 // Check if MII uses Reg.
1156 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1158 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1159 TRI.hasRegUnit(MO->getReg(), Reg))
1162 // Didn't reach NewIdx. It must be the first instruction in the block.
1167 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1168 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1169 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1170 Indexes->removeMachineInstrFromMaps(MI);
1171 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1172 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1173 OldIndex < getMBBEndIdx(MI->getParent()) &&
1174 "Cannot handle moves across basic block boundaries.");
1176 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1177 HME.updateAllRanges(MI);
1180 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1181 MachineInstr* BundleStart,
1183 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1184 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1185 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1186 HME.updateAllRanges(MI);
1189 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1190 const MachineBasicBlock::iterator End,
1191 const SlotIndex endIdx,
1192 LiveRange &LR, const unsigned Reg,
1193 const unsigned LaneMask) {
1194 LiveInterval::iterator LII = LR.find(endIdx);
1195 SlotIndex lastUseIdx;
1196 if (LII != LR.end() && LII->start < endIdx)
1197 lastUseIdx = LII->end;
1201 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1203 MachineInstr *MI = I;
1204 if (MI->isDebugValue())
1207 SlotIndex instrIdx = getInstructionIndex(MI);
1208 bool isStartValid = getInstructionFromIndex(LII->start);
1209 bool isEndValid = getInstructionFromIndex(LII->end);
1211 // FIXME: This doesn't currently handle early-clobber or multiple removed
1212 // defs inside of the region to repair.
1213 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1214 OE = MI->operands_end(); OI != OE; ++OI) {
1215 const MachineOperand &MO = *OI;
1216 if (!MO.isReg() || MO.getReg() != Reg)
1219 unsigned SubReg = MO.getSubReg();
1220 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1221 if ((Mask & LaneMask) == 0)
1225 if (!isStartValid) {
1226 if (LII->end.isDead()) {
1227 SlotIndex prevStart;
1228 if (LII != LR.begin())
1229 prevStart = std::prev(LII)->start;
1231 // FIXME: This could be more efficient if there was a
1232 // removeSegment method that returned an iterator.
1233 LR.removeSegment(*LII, true);
1234 if (prevStart.isValid())
1235 LII = LR.find(prevStart);
1239 LII->start = instrIdx.getRegSlot();
1240 LII->valno->def = instrIdx.getRegSlot();
1241 if (MO.getSubReg() && !MO.isUndef())
1242 lastUseIdx = instrIdx.getRegSlot();
1244 lastUseIdx = SlotIndex();
1249 if (!lastUseIdx.isValid()) {
1250 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1251 LiveRange::Segment S(instrIdx.getRegSlot(),
1252 instrIdx.getDeadSlot(), VNI);
1253 LII = LR.addSegment(S);
1254 } else if (LII->start != instrIdx.getRegSlot()) {
1255 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1256 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1257 LII = LR.addSegment(S);
1260 if (MO.getSubReg() && !MO.isUndef())
1261 lastUseIdx = instrIdx.getRegSlot();
1263 lastUseIdx = SlotIndex();
1264 } else if (MO.isUse()) {
1265 // FIXME: This should probably be handled outside of this branch,
1266 // either as part of the def case (for defs inside of the region) or
1267 // after the loop over the region.
1268 if (!isEndValid && !LII->end.isBlock())
1269 LII->end = instrIdx.getRegSlot();
1270 if (!lastUseIdx.isValid())
1271 lastUseIdx = instrIdx.getRegSlot();
1278 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1279 MachineBasicBlock::iterator Begin,
1280 MachineBasicBlock::iterator End,
1281 ArrayRef<unsigned> OrigRegs) {
1282 // Find anchor points, which are at the beginning/end of blocks or at
1283 // instructions that already have indexes.
1284 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1286 while (End != MBB->end() && !Indexes->hasIndex(End))
1290 if (End == MBB->end())
1291 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1293 endIdx = getInstructionIndex(End);
1295 Indexes->repairIndexesInRange(MBB, Begin, End);
1297 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1299 MachineInstr *MI = I;
1300 if (MI->isDebugValue())
1302 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1303 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1305 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1306 !hasInterval(MOI->getReg())) {
1307 createAndComputeVirtRegInterval(MOI->getReg());
1312 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1313 unsigned Reg = OrigRegs[i];
1314 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1317 LiveInterval &LI = getInterval(Reg);
1318 // FIXME: Should we support undefs that gain defs?
1319 if (!LI.hasAtLeastOneValue())
1322 for (LiveInterval::SubRange &S : LI.subranges()) {
1323 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1325 repairOldRegInRange(Begin, End, endIdx, LI, Reg);