1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
37 #include "LiveRangeCalc.h"
43 // Hidden options for help debugging.
44 static cl::opt<bool> DisableReMat("disable-rematerialization",
45 cl::init(false), cl::Hidden);
47 // Temporary option to enable regunit liveness.
48 static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden);
50 STATISTIC(numIntervals , "Number of original intervals");
52 char LiveIntervals::ID = 0;
53 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
54 "Live Interval Analysis", false, false)
55 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
56 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
57 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
58 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
59 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
60 "Live Interval Analysis", false, false)
62 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
64 AU.addRequired<AliasAnalysis>();
65 AU.addPreserved<AliasAnalysis>();
66 AU.addRequired<LiveVariables>();
67 AU.addPreserved<LiveVariables>();
68 AU.addPreservedID(MachineLoopInfoID);
70 AU.addRequiredTransitiveID(MachineDominatorsID);
71 AU.addPreservedID(MachineDominatorsID);
72 AU.addPreserved<SlotIndexes>();
73 AU.addRequiredTransitive<SlotIndexes>();
74 MachineFunctionPass::getAnalysisUsage(AU);
77 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
78 DomTree(0), LRCalc(0) {
79 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
82 LiveIntervals::~LiveIntervals() {
86 void LiveIntervals::releaseMemory() {
87 // Free the live intervals themselves.
88 for (DenseMap<unsigned, LiveInterval*>::iterator I = R2IMap.begin(),
89 E = R2IMap.end(); I != E; ++I)
95 RegMaskBlocks.clear();
97 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
98 delete RegUnitIntervals[i];
99 RegUnitIntervals.clear();
101 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
102 VNInfoAllocator.Reset();
105 /// runOnMachineFunction - Register allocate the whole function
107 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
109 MRI = &MF->getRegInfo();
110 TM = &fn.getTarget();
111 TRI = TM->getRegisterInfo();
112 TII = TM->getInstrInfo();
113 AA = &getAnalysis<AliasAnalysis>();
114 LV = &getAnalysis<LiveVariables>();
115 Indexes = &getAnalysis<SlotIndexes>();
117 DomTree = &getAnalysis<MachineDominatorTree>();
118 if (LiveRegUnits && !LRCalc)
119 LRCalc = new LiveRangeCalc();
120 AllocatableRegs = TRI->getAllocatableSet(fn);
121 ReservedRegs = TRI->getReservedRegs(fn);
125 numIntervals += getNumIntervals();
128 computeLiveInRegUnits();
135 /// print - Implement the dump method.
136 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
137 OS << "********** INTERVALS **********\n";
139 // Dump the physregs.
140 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
141 if (const LiveInterval *LI = R2IMap.lookup(Reg))
142 OS << PrintReg(Reg, TRI) << '\t' << *LI << '\n';
144 // Dump the regunits.
145 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
146 if (LiveInterval *LI = RegUnitIntervals[i])
147 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
149 // Dump the virtregs.
150 for (unsigned Reg = 0, RegE = MRI->getNumVirtRegs(); Reg != RegE; ++Reg)
151 if (const LiveInterval *LI =
152 R2IMap.lookup(TargetRegisterInfo::index2VirtReg(Reg)))
153 OS << PrintReg(LI->reg) << '\t' << *LI << '\n';
158 void LiveIntervals::printInstrs(raw_ostream &OS) const {
159 OS << "********** MACHINEINSTRS **********\n";
160 MF->print(OS, Indexes);
163 void LiveIntervals::dumpInstrs() const {
168 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
169 unsigned Reg = MI.getOperand(MOIdx).getReg();
170 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
171 const MachineOperand &MO = MI.getOperand(i);
174 if (MO.getReg() == Reg && MO.isDef()) {
175 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
176 MI.getOperand(MOIdx).getSubReg() &&
177 (MO.getSubReg() || MO.isImplicit()));
184 /// isPartialRedef - Return true if the specified def at the specific index is
185 /// partially re-defining the specified live interval. A common case of this is
186 /// a definition of the sub-register.
187 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
188 LiveInterval &interval) {
189 if (!MO.getSubReg() || MO.isEarlyClobber())
192 SlotIndex RedefIndex = MIIdx.getRegSlot();
193 const LiveRange *OldLR =
194 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
195 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
197 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
202 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
203 MachineBasicBlock::iterator mi,
207 LiveInterval &interval) {
208 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
210 // Virtual registers may be defined multiple times (due to phi
211 // elimination and 2-addr elimination). Much of what we do only has to be
212 // done once for the vreg. We use an empty interval to detect the first
213 // time we see a vreg.
214 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
215 if (interval.empty()) {
216 // Get the Idx of the defining instructions.
217 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
219 // Make sure the first definition is not a partial redefinition.
220 assert(!MO.readsReg() && "First def cannot also read virtual register "
221 "missing <undef> flag?");
223 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
224 assert(ValNo->id == 0 && "First value in interval is not 0?");
226 // Loop over all of the blocks that the vreg is defined in. There are
227 // two cases we have to handle here. The most common case is a vreg
228 // whose lifetime is contained within a basic block. In this case there
229 // will be a single kill, in MBB, which comes after the definition.
230 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
231 // FIXME: what about dead vars?
233 if (vi.Kills[0] != mi)
234 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
236 killIdx = defIndex.getDeadSlot();
238 // If the kill happens after the definition, we have an intra-block
240 if (killIdx > defIndex) {
241 assert(vi.AliveBlocks.empty() &&
242 "Shouldn't be alive across any blocks!");
243 LiveRange LR(defIndex, killIdx, ValNo);
244 interval.addRange(LR);
245 DEBUG(dbgs() << " +" << LR << "\n");
250 // The other case we handle is when a virtual register lives to the end
251 // of the defining block, potentially live across some blocks, then is
252 // live into some number of blocks, but gets killed. Start by adding a
253 // range that goes from this definition to the end of the defining block.
254 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
255 DEBUG(dbgs() << " +" << NewLR);
256 interval.addRange(NewLR);
258 bool PHIJoin = LV->isPHIJoin(interval.reg);
261 // A phi join register is killed at the end of the MBB and revived as a new
262 // valno in the killing blocks.
263 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
264 DEBUG(dbgs() << " phi-join");
265 ValNo->setHasPHIKill(true);
267 // Iterate over all of the blocks that the variable is completely
268 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
270 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
271 E = vi.AliveBlocks.end(); I != E; ++I) {
272 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
273 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
274 interval.addRange(LR);
275 DEBUG(dbgs() << " +" << LR);
279 // Finally, this virtual register is live from the start of any killing
280 // block to the 'use' slot of the killing instruction.
281 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
282 MachineInstr *Kill = vi.Kills[i];
283 SlotIndex Start = getMBBStartIdx(Kill->getParent());
284 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
286 // Create interval with one of a NEW value number. Note that this value
287 // number isn't actually defined by an instruction, weird huh? :)
289 assert(getInstructionFromIndex(Start) == 0 &&
290 "PHI def index points at actual instruction.");
291 ValNo = interval.getNextValue(Start, VNInfoAllocator);
292 ValNo->setIsPHIDef(true);
294 LiveRange LR(Start, killIdx, ValNo);
295 interval.addRange(LR);
296 DEBUG(dbgs() << " +" << LR);
300 if (MultipleDefsBySameMI(*mi, MOIdx))
301 // Multiple defs of the same virtual register by the same instruction.
302 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
303 // This is likely due to elimination of REG_SEQUENCE instructions. Return
304 // here since there is nothing to do.
307 // If this is the second time we see a virtual register definition, it
308 // must be due to phi elimination or two addr elimination. If this is
309 // the result of two address elimination, then the vreg is one of the
310 // def-and-use register operand.
312 // It may also be partial redef like this:
313 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
314 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
315 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
316 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
317 // If this is a two-address definition, then we have already processed
318 // the live range. The only problem is that we didn't realize there
319 // are actually two values in the live interval. Because of this we
320 // need to take the LiveRegion that defines this register and split it
322 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
324 const LiveRange *OldLR =
325 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
326 VNInfo *OldValNo = OldLR->valno;
327 SlotIndex DefIndex = OldValNo->def.getRegSlot();
329 // Delete the previous value, which should be short and continuous,
330 // because the 2-addr copy must be in the same MBB as the redef.
331 interval.removeRange(DefIndex, RedefIndex);
333 // The new value number (#1) is defined by the instruction we claimed
335 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
337 // Value#0 is now defined by the 2-addr instruction.
338 OldValNo->def = RedefIndex;
340 // Add the new live interval which replaces the range for the input copy.
341 LiveRange LR(DefIndex, RedefIndex, ValNo);
342 DEBUG(dbgs() << " replace range with " << LR);
343 interval.addRange(LR);
345 // If this redefinition is dead, we need to add a dummy unit live
346 // range covering the def slot.
348 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
351 DEBUG(dbgs() << " RESULT: " << interval);
352 } else if (LV->isPHIJoin(interval.reg)) {
353 // In the case of PHI elimination, each variable definition is only
354 // live until the end of the block. We've already taken care of the
355 // rest of the live range.
357 SlotIndex defIndex = MIIdx.getRegSlot();
358 if (MO.isEarlyClobber())
359 defIndex = MIIdx.getRegSlot(true);
361 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
363 SlotIndex killIndex = getMBBEndIdx(mbb);
364 LiveRange LR(defIndex, killIndex, ValNo);
365 interval.addRange(LR);
366 ValNo->setHasPHIKill(true);
367 DEBUG(dbgs() << " phi-join +" << LR);
369 llvm_unreachable("Multiply defined register");
373 DEBUG(dbgs() << '\n');
376 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
377 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
378 SE = MBB->succ_end();
380 const MachineBasicBlock* succ = *SI;
381 if (succ->isLiveIn(Reg))
387 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
388 MachineBasicBlock::iterator mi,
391 LiveInterval &interval) {
392 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
394 SlotIndex baseIndex = MIIdx;
395 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
396 SlotIndex end = start;
398 // If it is not used after definition, it is considered dead at
399 // the instruction defining it. Hence its interval is:
400 // [defSlot(def), defSlot(def)+1)
401 // For earlyclobbers, the defSlot was pushed back one; the extra
402 // advance below compensates.
404 DEBUG(dbgs() << " dead");
405 end = start.getDeadSlot();
409 // If it is not dead on definition, it must be killed by a
410 // subsequent instruction. Hence its interval is:
411 // [defSlot(def), useSlot(kill)+1)
412 baseIndex = baseIndex.getNextIndex();
413 while (++mi != MBB->end()) {
415 if (mi->isDebugValue())
417 if (getInstructionFromIndex(baseIndex) == 0)
418 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
420 if (mi->killsRegister(interval.reg, TRI)) {
421 DEBUG(dbgs() << " killed");
422 end = baseIndex.getRegSlot();
425 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,TRI);
427 if (mi->isRegTiedToUseOperand(DefIdx)) {
428 // Two-address instruction.
429 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
431 // Another instruction redefines the register before it is ever read.
432 // Then the register is essentially dead at the instruction that
433 // defines it. Hence its interval is:
434 // [defSlot(def), defSlot(def)+1)
435 DEBUG(dbgs() << " dead");
436 end = start.getDeadSlot();
442 baseIndex = baseIndex.getNextIndex();
445 // If we get here the register *should* be live out.
446 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
448 // FIXME: We need saner rules for reserved regs.
449 if (isReserved(interval.reg)) {
450 end = start.getDeadSlot();
452 // Unreserved, unallocable registers like EFLAGS can be live across basic
454 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
455 "Unreserved reg not live-out?");
456 end = getMBBEndIdx(MBB);
459 assert(start < end && "did not find end of interval?");
461 // Already exists? Extend old live interval.
462 VNInfo *ValNo = interval.getVNInfoAt(start);
463 bool Extend = ValNo != 0;
465 ValNo = interval.getNextValue(start, VNInfoAllocator);
466 LiveRange LR(start, end, ValNo);
467 interval.addRange(LR);
468 DEBUG(dbgs() << " +" << LR << '\n');
471 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
472 MachineBasicBlock::iterator MI,
476 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
477 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
478 getOrCreateInterval(MO.getReg()));
480 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
481 getOrCreateInterval(MO.getReg()));
484 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
486 LiveInterval &interval) {
487 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
488 "Only physical registers can be live in.");
489 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
490 MBB->isLandingPad()) &&
491 "Allocatable live-ins only valid for entry blocks and landing pads.");
493 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, TRI));
495 // Look for kills, if it reaches a def before it's killed, then it shouldn't
496 // be considered a livein.
497 MachineBasicBlock::iterator mi = MBB->begin();
498 MachineBasicBlock::iterator E = MBB->end();
499 // Skip over DBG_VALUE at the start of the MBB.
500 if (mi != E && mi->isDebugValue()) {
501 while (++mi != E && mi->isDebugValue())
504 // MBB is empty except for DBG_VALUE's.
508 SlotIndex baseIndex = MIIdx;
509 SlotIndex start = baseIndex;
510 if (getInstructionFromIndex(baseIndex) == 0)
511 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
513 SlotIndex end = baseIndex;
514 bool SeenDefUse = false;
517 if (mi->killsRegister(interval.reg, TRI)) {
518 DEBUG(dbgs() << " killed");
519 end = baseIndex.getRegSlot();
522 } else if (mi->modifiesRegister(interval.reg, TRI)) {
523 // Another instruction redefines the register before it is ever read.
524 // Then the register is essentially dead at the instruction that defines
525 // it. Hence its interval is:
526 // [defSlot(def), defSlot(def)+1)
527 DEBUG(dbgs() << " dead");
528 end = start.getDeadSlot();
533 while (++mi != E && mi->isDebugValue())
534 // Skip over DBG_VALUE.
537 baseIndex = Indexes->getNextNonNullIndex(baseIndex);
540 // Live-in register might not be used at all.
542 if (isAllocatable(interval.reg) ||
543 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
544 // Allocatable registers are never live through.
545 // Non-allocatable registers that aren't live into any successors also
546 // aren't live through.
547 DEBUG(dbgs() << " dead");
550 // If we get here the register is non-allocatable and live into some
551 // successor. We'll conservatively assume it's live-through.
552 DEBUG(dbgs() << " live through");
553 end = getMBBEndIdx(MBB);
557 SlotIndex defIdx = getMBBStartIdx(MBB);
558 assert(getInstructionFromIndex(defIdx) == 0 &&
559 "PHI def index points at actual instruction.");
560 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
561 vni->setIsPHIDef(true);
562 LiveRange LR(start, end, vni);
564 interval.addRange(LR);
565 DEBUG(dbgs() << " +" << LR << '\n');
568 /// computeIntervals - computes the live intervals for virtual
569 /// registers. for some ordering of the machine instructions [1,N] a
570 /// live interval is an interval [i, j) where 1 <= i <= j < N for
571 /// which a variable is live
572 void LiveIntervals::computeIntervals() {
573 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
574 << "********** Function: "
575 << ((Value*)MF->getFunction())->getName() << '\n');
577 RegMaskBlocks.resize(MF->getNumBlockIDs());
579 SmallVector<unsigned, 8> UndefUses;
580 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
582 MachineBasicBlock *MBB = MBBI;
583 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
588 // Track the index of the current machine instr.
589 SlotIndex MIIndex = getMBBStartIdx(MBB);
590 DEBUG(dbgs() << "BB#" << MBB->getNumber()
591 << ":\t\t# derived from " << MBB->getName() << "\n");
593 // Create intervals for live-ins to this BB first.
594 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
595 LE = MBB->livein_end(); LI != LE; ++LI) {
596 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
599 // Skip over empty initial indices.
600 if (getInstructionFromIndex(MIIndex) == 0)
601 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
603 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
605 DEBUG(dbgs() << MIIndex << "\t" << *MI);
606 if (MI->isDebugValue())
608 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
609 "Lost SlotIndex synchronization");
612 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
613 MachineOperand &MO = MI->getOperand(i);
615 // Collect register masks.
616 if (MO.isRegMask()) {
617 RegMaskSlots.push_back(MIIndex.getRegSlot());
618 RegMaskBits.push_back(MO.getRegMask());
622 if (!MO.isReg() || !MO.getReg())
625 // handle register defs - build intervals
627 handleRegisterDef(MBB, MI, MIIndex, MO, i);
628 else if (MO.isUndef())
629 UndefUses.push_back(MO.getReg());
632 // Move to the next instr slot.
633 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
636 // Compute the number of register mask instructions in this block.
637 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
638 RMB.second = RegMaskSlots.size() - RMB.first;;
641 // Create empty intervals for registers defined by implicit_def's (except
642 // for those implicit_def that define values which are liveout of their
644 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
645 unsigned UndefReg = UndefUses[i];
646 (void)getOrCreateInterval(UndefReg);
650 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
651 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
652 return new LiveInterval(reg, Weight);
656 //===----------------------------------------------------------------------===//
657 // Register Unit Liveness
658 //===----------------------------------------------------------------------===//
660 // Fixed interference typically comes from ABI boundaries: Function arguments
661 // and return values are passed in fixed registers, and so are exception
662 // pointers entering landing pads. Certain instructions require values to be
663 // present in specific registers. That is also represented through fixed
667 /// computeRegUnitInterval - Compute the live interval of a register unit, based
668 /// on the uses and defs of aliasing registers. The interval should be empty,
669 /// or contain only dead phi-defs from ABI blocks.
670 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
671 unsigned Unit = LI->reg;
673 assert(LRCalc && "LRCalc not initialized.");
674 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
676 // The physregs aliasing Unit are the roots and their super-registers.
677 // Create all values as dead defs before extending to uses. Note that roots
678 // may share super-registers. That's OK because createDeadDefs() is
679 // idempotent. It is very rare for a register unit to have multiple roots, so
680 // uniquing super-registers is probably not worthwhile.
681 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
682 unsigned Root = *Roots;
683 if (!MRI->reg_empty(Root))
684 LRCalc->createDeadDefs(LI, Root);
685 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
686 if (!MRI->reg_empty(*Supers))
687 LRCalc->createDeadDefs(LI, *Supers);
691 // Now extend LI to reach all uses.
692 // Ignore uses of reserved registers. We only track defs of those.
693 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
694 unsigned Root = *Roots;
695 if (!isReserved(Root) && !MRI->reg_empty(Root))
696 LRCalc->extendToUses(LI, Root);
697 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
698 unsigned Reg = *Supers;
699 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
700 LRCalc->extendToUses(LI, Reg);
706 /// computeLiveInRegUnits - Precompute the live ranges of any register units
707 /// that are live-in to an ABI block somewhere. Register values can appear
708 /// without a corresponding def when entering the entry block or a landing pad.
710 void LiveIntervals::computeLiveInRegUnits() {
711 RegUnitIntervals.resize(TRI->getNumRegUnits());
712 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
714 // Keep track of the intervals allocated.
715 SmallVector<LiveInterval*, 8> NewIntvs;
717 // Check all basic blocks for live-ins.
718 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
720 const MachineBasicBlock *MBB = MFI;
722 // We only care about ABI blocks: Entry + landing pads.
723 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
726 // Create phi-defs at Begin for all live-in registers.
727 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
728 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
729 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
730 LIE = MBB->livein_end(); LII != LIE; ++LII) {
731 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
732 unsigned Unit = *Units;
733 LiveInterval *Intv = RegUnitIntervals[Unit];
735 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
736 NewIntvs.push_back(Intv);
738 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
740 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
743 DEBUG(dbgs() << '\n');
745 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
747 // Compute the 'normal' part of the intervals.
748 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
749 computeRegUnitInterval(NewIntvs[i]);
753 /// shrinkToUses - After removing some uses of a register, shrink its live
754 /// range to just the remaining uses. This method does not compute reaching
755 /// defs for new uses, and it doesn't remove dead defs.
756 bool LiveIntervals::shrinkToUses(LiveInterval *li,
757 SmallVectorImpl<MachineInstr*> *dead) {
758 DEBUG(dbgs() << "Shrink: " << *li << '\n');
759 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
760 && "Can only shrink virtual registers");
761 // Find all the values used, including PHI kills.
762 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
764 // Blocks that have already been added to WorkList as live-out.
765 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
767 // Visit all instructions reading li->reg.
768 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
769 MachineInstr *UseMI = I.skipInstruction();) {
770 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
772 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
773 LiveRangeQuery LRQ(*li, Idx);
774 VNInfo *VNI = LRQ.valueIn();
776 // This shouldn't happen: readsVirtualRegister returns true, but there is
777 // no live value. It is likely caused by a target getting <undef> flags
779 DEBUG(dbgs() << Idx << '\t' << *UseMI
780 << "Warning: Instr claims to read non-existent value in "
784 // Special case: An early-clobber tied operand reads and writes the
785 // register one slot early.
786 if (VNInfo *DefVNI = LRQ.valueDefined())
789 WorkList.push_back(std::make_pair(Idx, VNI));
792 // Create a new live interval with only minimal live segments per def.
793 LiveInterval NewLI(li->reg, 0);
794 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
799 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
802 // Keep track of the PHIs that are in use.
803 SmallPtrSet<VNInfo*, 8> UsedPHIs;
805 // Extend intervals to reach all uses in WorkList.
806 while (!WorkList.empty()) {
807 SlotIndex Idx = WorkList.back().first;
808 VNInfo *VNI = WorkList.back().second;
810 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
811 SlotIndex BlockStart = getMBBStartIdx(MBB);
813 // Extend the live range for VNI to be live at Idx.
814 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
816 assert(ExtVNI == VNI && "Unexpected existing value number");
817 // Is this a PHIDef we haven't seen before?
818 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
820 // The PHI is live, make sure the predecessors are live-out.
821 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
822 PE = MBB->pred_end(); PI != PE; ++PI) {
823 if (!LiveOut.insert(*PI))
825 SlotIndex Stop = getMBBEndIdx(*PI);
826 // A predecessor is not required to have a live-out value for a PHI.
827 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
828 WorkList.push_back(std::make_pair(Stop, PVNI));
833 // VNI is live-in to MBB.
834 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
835 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
837 // Make sure VNI is live-out from the predecessors.
838 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
839 PE = MBB->pred_end(); PI != PE; ++PI) {
840 if (!LiveOut.insert(*PI))
842 SlotIndex Stop = getMBBEndIdx(*PI);
843 assert(li->getVNInfoBefore(Stop) == VNI &&
844 "Wrong value out of predecessor");
845 WorkList.push_back(std::make_pair(Stop, VNI));
849 // Handle dead values.
850 bool CanSeparate = false;
851 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
856 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
857 assert(LII != NewLI.end() && "Missing live range for PHI");
858 if (LII->end != VNI->def.getDeadSlot())
860 if (VNI->isPHIDef()) {
861 // This is a dead PHI. Remove it.
862 VNI->setIsUnused(true);
863 NewLI.removeRange(*LII);
864 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
867 // This is a dead def. Make sure the instruction knows.
868 MachineInstr *MI = getInstructionFromIndex(VNI->def);
869 assert(MI && "No instruction defining live value");
870 MI->addRegisterDead(li->reg, TRI);
871 if (dead && MI->allDefsAreDead()) {
872 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
878 // Move the trimmed ranges back.
879 li->ranges.swap(NewLI.ranges);
880 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
885 //===----------------------------------------------------------------------===//
886 // Register allocator hooks.
889 void LiveIntervals::addKillFlags() {
890 for (iterator I = begin(), E = end(); I != E; ++I) {
891 unsigned Reg = I->first;
892 if (TargetRegisterInfo::isPhysicalRegister(Reg))
894 if (MRI->reg_nodbg_empty(Reg))
896 LiveInterval *LI = I->second;
898 // Every instruction that kills Reg corresponds to a live range end point.
899 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
901 // A block index indicates an MBB edge.
902 if (RI->end.isBlock())
904 MachineInstr *MI = getInstructionFromIndex(RI->end);
907 MI->addRegisterKilled(Reg, NULL);
913 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
914 // A local live range must be fully contained inside the block, meaning it is
915 // defined and killed at instructions, not at block boundaries. It is not
916 // live in or or out of any block.
918 // It is technically possible to have a PHI-defined live range identical to a
919 // single block, but we are going to return false in that case.
921 SlotIndex Start = LI.beginIndex();
925 SlotIndex Stop = LI.endIndex();
929 // getMBBFromIndex doesn't need to search the MBB table when both indexes
930 // belong to proper instructions.
931 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
932 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
933 return MBB1 == MBB2 ? MBB1 : NULL;
937 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
938 // Limit the loop depth ridiculousness.
942 // The loop depth is used to roughly estimate the number of times the
943 // instruction is executed. Something like 10^d is simple, but will quickly
944 // overflow a float. This expression behaves like 10^d for small d, but is
945 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
946 // headroom before overflow.
947 // By the way, powf() might be unavailable here. For consistency,
948 // We may take pow(double,double).
949 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
951 return (isDef + isUse) * lc;
954 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
955 MachineInstr* startInst) {
956 LiveInterval& Interval = getOrCreateInterval(reg);
957 VNInfo* VN = Interval.getNextValue(
958 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
959 getVNInfoAllocator());
960 VN->setHasPHIKill(true);
962 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
963 getMBBEndIdx(startInst->getParent()), VN);
964 Interval.addRange(LR);
970 //===----------------------------------------------------------------------===//
971 // Register mask functions
972 //===----------------------------------------------------------------------===//
974 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
975 BitVector &UsableRegs) {
978 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
980 // Use a smaller arrays for local live ranges.
981 ArrayRef<SlotIndex> Slots;
982 ArrayRef<const uint32_t*> Bits;
983 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
984 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
985 Bits = getRegMaskBitsInBlock(MBB->getNumber());
987 Slots = getRegMaskSlots();
988 Bits = getRegMaskBits();
991 // We are going to enumerate all the register mask slots contained in LI.
992 // Start with a binary search of RegMaskSlots to find a starting point.
993 ArrayRef<SlotIndex>::iterator SlotI =
994 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
995 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
997 // No slots in range, LI begins after the last call.
1003 assert(*SlotI >= LiveI->start);
1004 // Loop over all slots overlapping this segment.
1005 while (*SlotI < LiveI->end) {
1006 // *SlotI overlaps LI. Collect mask bits.
1008 // This is the first overlap. Initialize UsableRegs to all ones.
1010 UsableRegs.resize(TRI->getNumRegs(), true);
1013 // Remove usable registers clobbered by this mask.
1014 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1015 if (++SlotI == SlotE)
1018 // *SlotI is beyond the current LI segment.
1019 LiveI = LI.advanceTo(LiveI, *SlotI);
1022 // Advance SlotI until it overlaps.
1023 while (*SlotI < LiveI->start)
1024 if (++SlotI == SlotE)
1029 //===----------------------------------------------------------------------===//
1030 // IntervalUpdate class.
1031 //===----------------------------------------------------------------------===//
1033 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1034 class LiveIntervals::HMEditor {
1037 const MachineRegisterInfo& MRI;
1038 const TargetRegisterInfo& TRI;
1041 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1042 typedef DenseSet<IntRangePair> RangeSet;
1049 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1051 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1054 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1055 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1056 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1058 // Update intervals for all operands of MI from OldIdx to NewIdx.
1059 // This assumes that MI used to be at OldIdx, and now resides at
1061 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1062 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1064 // Collect the operands.
1065 RangeSet Entering, Internal, Exiting;
1066 bool hasRegMaskOp = false;
1067 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1069 // To keep the LiveRanges valid within an interval, move the ranges closest
1070 // to the destination first. This prevents ranges from overlapping, to that
1071 // APIs like removeRange still work.
1072 if (NewIdx < OldIdx) {
1073 moveAllEnteringFrom(OldIdx, Entering);
1074 moveAllInternalFrom(OldIdx, Internal);
1075 moveAllExitingFrom(OldIdx, Exiting);
1078 moveAllExitingFrom(OldIdx, Exiting);
1079 moveAllInternalFrom(OldIdx, Internal);
1080 moveAllEnteringFrom(OldIdx, Entering);
1084 updateRegMaskSlots(OldIdx);
1087 LIValidator validator;
1088 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1089 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1090 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1091 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1096 // Update intervals for all operands of MI to refer to BundleStart's
1098 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1099 if (MI == BundleStart)
1100 return; // Bundling instr with itself - nothing to do.
1102 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1103 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1104 "SlotIndex <-> Instruction mapping broken for MI");
1106 // Collect all ranges already in the bundle.
1107 MachineBasicBlock::instr_iterator BII(BundleStart);
1108 RangeSet Entering, Internal, Exiting;
1109 bool hasRegMaskOp = false;
1110 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1111 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1112 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1115 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1116 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1119 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1124 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1125 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1127 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1128 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1129 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1131 moveAllEnteringFromInto(OldIdx, Entering, BR);
1132 moveAllInternalFromInto(OldIdx, Internal, BR);
1133 moveAllExitingFromInto(OldIdx, Exiting, BR);
1137 LIValidator validator;
1138 validator = std::for_each(Entering.begin(), Entering.end(), validator);
1139 validator = std::for_each(Internal.begin(), Internal.end(), validator);
1140 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
1141 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1150 DenseSet<const LiveInterval*> Checked, Bogus;
1152 void operator()(const IntRangePair& P) {
1153 const LiveInterval* LI = P.first;
1154 if (Checked.count(LI))
1159 SlotIndex LastEnd = LI->begin()->start;
1160 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1161 LRI != LRE; ++LRI) {
1162 const LiveRange& LR = *LRI;
1163 if (LastEnd > LR.start || LR.start >= LR.end)
1169 bool rangesOk() const {
1170 return Bogus.empty();
1175 // Collect IntRangePairs for all operands of MI that may need fixing.
1176 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1178 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1179 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1180 hasRegMaskOp = false;
1181 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1182 MOE = MI->operands_end();
1183 MOI != MOE; ++MOI) {
1184 const MachineOperand& MO = *MOI;
1186 if (MO.isRegMask()) {
1187 hasRegMaskOp = true;
1191 if (!MO.isReg() || MO.getReg() == 0)
1194 unsigned Reg = MO.getReg();
1196 // TODO: Currently we're skipping uses that are reserved or have no
1197 // interval, but we're not updating their kills. This should be
1199 if (!LIS.hasInterval(Reg) ||
1200 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1203 LiveInterval* LI = &LIS.getInterval(Reg);
1205 if (MO.readsReg()) {
1206 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1208 Entering.insert(std::make_pair(LI, LR));
1211 if (MO.isEarlyClobber()) {
1212 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1213 assert(LR != 0 && "No EC range?");
1214 if (LR->end > OldIdx.getDeadSlot())
1215 Exiting.insert(std::make_pair(LI, LR));
1217 Internal.insert(std::make_pair(LI, LR));
1218 } else if (MO.isDead()) {
1219 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1220 assert(LR != 0 && "No dead-def range?");
1221 Internal.insert(std::make_pair(LI, LR));
1223 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1224 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1225 "Non-dead-def should have live range exiting.");
1226 Exiting.insert(std::make_pair(LI, LR));
1232 // Collect IntRangePairs for all operands of MI that may need fixing.
1233 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1234 RangeSet& Exiting, SlotIndex MIStartIdx,
1235 SlotIndex MIEndIdx) {
1236 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1237 MOE = MI->operands_end();
1238 MOI != MOE; ++MOI) {
1239 const MachineOperand& MO = *MOI;
1240 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1241 if (!MO.isReg() || MO.getReg() == 0)
1244 unsigned Reg = MO.getReg();
1246 // TODO: Currently we're skipping uses that are reserved or have no
1247 // interval, but we're not updating their kills. This should be
1249 if (!LIS.hasInterval(Reg) ||
1250 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1253 LiveInterval* LI = &LIS.getInterval(Reg);
1255 if (MO.readsReg()) {
1256 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1258 Entering.insert(std::make_pair(LI, LR));
1261 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
1262 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1263 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1264 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1265 Exiting.insert(std::make_pair(LI, LR));
1270 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
1273 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1275 LiveInterval* LI = EI->first;
1276 LiveRange* LR = EI->second;
1277 BR[LI->reg].Use = LR;
1280 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1282 LiveInterval* LI = II->first;
1283 LiveRange* LR = II->second;
1284 if (LR->end.isDead()) {
1285 BR[LI->reg].Dead = LR;
1287 BR[LI->reg].EC = LR;
1291 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1293 LiveInterval* LI = EI->first;
1294 LiveRange* LR = EI->second;
1295 BR[LI->reg].Def = LR;
1301 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1302 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1303 if (!OldKillMI->killsRegister(reg))
1304 return; // Bail out if we don't have kill flags on the old register.
1305 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1306 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1307 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1308 OldKillMI->clearRegisterKills(reg, &TRI);
1309 NewKillMI->addRegisterKilled(reg, &TRI);
1312 void updateRegMaskSlots(SlotIndex OldIdx) {
1313 SmallVectorImpl<SlotIndex>::iterator RI =
1314 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1316 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1318 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1319 "RegSlots out of order. Did you move one call across another?");
1322 // Return the last use of reg between NewIdx and OldIdx.
1323 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1324 SlotIndex LastUse = NewIdx;
1325 for (MachineRegisterInfo::use_nodbg_iterator
1326 UI = MRI.use_nodbg_begin(Reg),
1327 UE = MRI.use_nodbg_end();
1328 UI != UE; UI.skipInstruction()) {
1329 const MachineInstr* MI = &*UI;
1330 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1331 if (InstSlot > LastUse && InstSlot < OldIdx)
1337 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1338 LiveInterval* LI = P.first;
1339 LiveRange* LR = P.second;
1340 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1343 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1344 if (LastUse != NewIdx)
1345 moveKillFlags(LI->reg, NewIdx, LastUse);
1346 LR->end = LastUse.getRegSlot();
1349 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1350 LiveInterval* LI = P.first;
1351 LiveRange* LR = P.second;
1352 // Extend the LiveRange if NewIdx is past the end.
1353 if (NewIdx > LR->end) {
1354 // Move kill flags if OldIdx was not originally the end
1355 // (otherwise LR->end points to an invalid slot).
1356 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1357 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1358 moveKillFlags(LI->reg, LR->end, NewIdx);
1360 LR->end = NewIdx.getRegSlot();
1364 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1365 bool GoingUp = NewIdx < OldIdx;
1368 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1370 moveEnteringUpFrom(OldIdx, *EI);
1372 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1374 moveEnteringDownFrom(OldIdx, *EI);
1378 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1379 LiveInterval* LI = P.first;
1380 LiveRange* LR = P.second;
1381 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1382 LR->end <= OldIdx.getDeadSlot() &&
1383 "Range should be internal to OldIdx.");
1385 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1386 Tmp.valno->def = Tmp.start;
1387 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1388 LI->removeRange(*LR);
1392 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1393 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1395 moveInternalFrom(OldIdx, *II);
1398 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1399 LiveRange* LR = P.second;
1400 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1401 "Range should start in OldIdx.");
1402 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1403 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1404 LR->start = NewStart;
1405 LR->valno->def = NewStart;
1408 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1409 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1411 moveExitingFrom(OldIdx, *EI);
1414 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1416 LiveInterval* LI = P.first;
1417 LiveRange* LR = P.second;
1418 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1420 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1421 "Def in bundle should be def range.");
1422 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1423 "If bundle has use for this reg it should be LR.");
1424 BR[LI->reg].Use = LR;
1428 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1429 moveKillFlags(LI->reg, OldIdx, LastUse);
1431 if (LR->start < NewIdx) {
1432 // Becoming a new entering range.
1433 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1434 "Bundle shouldn't be re-defining reg mid-range.");
1435 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1436 "Bundle shouldn't have different use range for same reg.");
1437 LR->end = LastUse.getRegSlot();
1438 BR[LI->reg].Use = LR;
1440 // Becoming a new Dead-def.
1441 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1442 "Live range starting at unexpected slot.");
1443 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1444 assert(BR[LI->reg].Dead == 0 &&
1445 "Can't have def and dead def of same reg in a bundle.");
1446 LR->end = LastUse.getDeadSlot();
1447 BR[LI->reg].Dead = BR[LI->reg].Def;
1448 BR[LI->reg].Def = 0;
1452 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1454 LiveInterval* LI = P.first;
1455 LiveRange* LR = P.second;
1456 if (NewIdx > LR->end) {
1457 // Range extended to bundle. Add to bundle uses.
1458 // Note: Currently adds kill flags to bundle start.
1459 assert(BR[LI->reg].Use == 0 &&
1460 "Bundle already has use range for reg.");
1461 moveKillFlags(LI->reg, LR->end, NewIdx);
1462 LR->end = NewIdx.getRegSlot();
1463 BR[LI->reg].Use = LR;
1465 assert(BR[LI->reg].Use != 0 &&
1466 "Bundle should already have a use range for reg.");
1470 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1472 bool GoingUp = NewIdx < OldIdx;
1475 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1477 moveEnteringUpFromInto(OldIdx, *EI, BR);
1479 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1481 moveEnteringDownFromInto(OldIdx, *EI, BR);
1485 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1487 // TODO: Sane rules for moving ranges into bundles.
1490 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1492 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1494 moveInternalFromInto(OldIdx, *II, BR);
1497 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1499 LiveInterval* LI = P.first;
1500 LiveRange* LR = P.second;
1502 assert(LR->start.isRegister() &&
1503 "Don't know how to merge exiting ECs into bundles yet.");
1505 if (LR->end > NewIdx.getDeadSlot()) {
1506 // This range is becoming an exiting range on the bundle.
1507 // If there was an old dead-def of this reg, delete it.
1508 if (BR[LI->reg].Dead != 0) {
1509 LI->removeRange(*BR[LI->reg].Dead);
1510 BR[LI->reg].Dead = 0;
1512 assert(BR[LI->reg].Def == 0 &&
1513 "Can't have two defs for the same variable exiting a bundle.");
1514 LR->start = NewIdx.getRegSlot();
1515 LR->valno->def = LR->start;
1516 BR[LI->reg].Def = LR;
1518 // This range is becoming internal to the bundle.
1519 assert(LR->end == NewIdx.getRegSlot() &&
1520 "Can't bundle def whose kill is before the bundle");
1521 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1522 // Already have a def for this. Just delete range.
1523 LI->removeRange(*LR);
1525 // Make range dead, record.
1526 LR->end = NewIdx.getDeadSlot();
1527 BR[LI->reg].Dead = LR;
1528 assert(BR[LI->reg].Use == LR &&
1529 "Range becoming dead should currently be use.");
1531 // In both cases the range is no longer a use on the bundle.
1532 BR[LI->reg].Use = 0;
1536 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1538 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1540 moveExitingFromInto(OldIdx, *EI, BR);
1545 void LiveIntervals::handleMove(MachineInstr* MI) {
1546 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1547 Indexes->removeMachineInstrFromMaps(MI);
1548 SlotIndex NewIndex = MI->isInsideBundle() ?
1549 Indexes->getInstructionIndex(MI) :
1550 Indexes->insertMachineInstrInMaps(MI);
1551 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1552 OldIndex < getMBBEndIdx(MI->getParent()) &&
1553 "Cannot handle moves across basic block boundaries.");
1554 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1556 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1557 HME.moveAllRangesFrom(MI, OldIndex);
1560 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
1561 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1562 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1563 HME.moveAllRangesInto(MI, BundleStart);