1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/Analysis/Verifier.h"
18 #include "llvm/Assembly/PrintModulePass.h"
19 #include "llvm/CodeGen/AsmPrinter.h"
20 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/GCStrategy.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSubtargetInfo.h"
30 #include "llvm/Target/TargetData.h"
31 #include "llvm/Target/TargetInstrInfo.h"
32 #include "llvm/Target/TargetLowering.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
35 #include "llvm/Target/TargetSubtargetInfo.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include "llvm/ADT/OwningPtr.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/FormattedStream.h"
41 #include "llvm/Support/TargetRegistry.h"
44 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
45 cl::desc("Disable Post Regalloc"));
46 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
47 cl::desc("Disable branch folding"));
48 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
49 cl::desc("Disable tail duplication"));
50 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
51 cl::desc("Disable pre-register allocation tail duplication"));
52 static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
53 cl::Hidden, cl::desc("Enable probability-driven block placement"));
54 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
55 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
56 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
57 cl::desc("Disable code placement"));
58 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
59 cl::desc("Disable Stack Slot Coloring"));
60 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
61 cl::desc("Disable Machine Dead Code Elimination"));
62 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
63 cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
65 cl::desc("Disable Machine Common Subexpression Elimination"));
66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
68 cl::desc("Disable Machine LICM"));
69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70 cl::desc("Disable Machine Sinking"));
71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72 cl::desc("Disable Loop Strength Reduction Pass"));
73 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
74 cl::desc("Disable Codegen Prepare"));
75 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
76 cl::desc("Disable Copy Propagation pass"));
77 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
78 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
79 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
80 cl::desc("Print LLVM IR input to isel pass"));
81 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
82 cl::desc("Dump garbage collector data"));
83 static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
84 cl::desc("Show encoding in .s output"));
85 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
86 cl::desc("Show instruction structure in .s output"));
87 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
88 cl::desc("Verify generated machine code"),
89 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
91 static cl::opt<cl::boolOrDefault>
92 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
93 cl::init(cl::BOU_UNSET));
95 static bool getVerboseAsm() {
97 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
98 case cl::BOU_TRUE: return true;
99 case cl::BOU_FALSE: return false;
101 llvm_unreachable("Invalid verbose asm state");
104 // Enable or disable FastISel. Both options are needed, because
105 // FastISel is enabled by default with -fast, and we wish to be
106 // able to enable or disable fast-isel independently from -O0.
107 static cl::opt<cl::boolOrDefault>
108 EnableFastISelOption("fast-isel", cl::Hidden,
109 cl::desc("Enable the \"fast\" instruction selector"));
111 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
112 StringRef CPU, StringRef FS,
113 TargetOptions Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL)
116 : TargetMachine(T, Triple, CPU, FS, Options) {
117 CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
118 AsmInfo = T.createMCAsmInfo(Triple);
119 // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
120 // and if the old one gets included then MCAsmInfo will be NULL and
121 // we'll crash later.
122 // Provide the user with a useful error message about what's wrong.
123 assert(AsmInfo && "MCAsmInfo not initialized."
124 "Make sure you include the correct TargetSelect.h"
125 "and that InitializeAllTargetMCs() is being invoked!");
128 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
129 formatted_raw_ostream &Out,
130 CodeGenFileType FileType,
131 bool DisableVerify) {
132 // Add common CodeGen passes.
133 MCContext *Context = 0;
134 TargetPassConfig *PassConfig = createPassConfig(PM, DisableVerify);
136 if (PassConfig->addCodeGenPasses(Context))
138 assert(Context != 0 && "Failed to get MCContext");
140 if (hasMCSaveTempLabels())
141 Context->setAllowTemporaryLabels(false);
143 const MCAsmInfo &MAI = *getMCAsmInfo();
144 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
145 OwningPtr<MCStreamer> AsmStreamer;
148 case CGFT_AssemblyFile: {
149 MCInstPrinter *InstPrinter =
150 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
152 // Create a code emitter if asked to show the encoding.
153 MCCodeEmitter *MCE = 0;
154 MCAsmBackend *MAB = 0;
155 if (ShowMCEncoding) {
156 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
157 MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
158 MAB = getTarget().createMCAsmBackend(getTargetTriple());
161 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
165 hasMCUseDwarfDirectory(),
169 AsmStreamer.reset(S);
172 case CGFT_ObjectFile: {
173 // Create the code emitter for the target if it exists. If not, .o file
175 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
177 MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
178 if (MCE == 0 || MAB == 0)
181 AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
183 MCE, hasMCRelaxAll(),
184 hasMCNoExecStack()));
185 AsmStreamer.get()->InitSections();
189 // The Null output is intended for use for performance analysis and testing,
191 AsmStreamer.reset(createNullStreamer(*Context));
195 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
196 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
200 // If successful, createAsmPrinter took ownership of AsmStreamer.
205 PM.add(createGCInfoDeleter());
209 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
210 /// get machine code emitted. This uses a JITCodeEmitter object to handle
211 /// actually outputting the machine code and resolving things like the address
212 /// of functions. This method should returns true if machine code emission is
215 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
217 bool DisableVerify) {
218 // Add common CodeGen passes.
220 OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
221 if (PassConfig->addCodeGenPasses(Ctx))
224 addCodeEmitter(PM, JCE);
225 PM.add(createGCInfoDeleter());
227 return false; // success!
230 /// addPassesToEmitMC - Add passes to the specified pass manager to get
231 /// machine code emitted with the MCJIT. This method returns true if machine
232 /// code is not supported. It fills the MCContext Ctx pointer which can be
233 /// used to build custom MCStreamer.
235 bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
238 bool DisableVerify) {
239 // Add common CodeGen passes.
240 OwningPtr<TargetPassConfig> PassConfig(createPassConfig(PM, DisableVerify));
241 if (PassConfig->addCodeGenPasses(Ctx))
244 if (hasMCSaveTempLabels())
245 Ctx->setAllowTemporaryLabels(false);
247 // Create the code emitter for the target if it exists. If not, .o file
249 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
250 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
251 MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
252 if (MCE == 0 || MAB == 0)
255 OwningPtr<MCStreamer> AsmStreamer;
256 AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
259 hasMCNoExecStack()));
260 AsmStreamer.get()->InitSections();
262 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
263 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
267 // If successful, createAsmPrinter took ownership of AsmStreamer.
272 return false; // success!
275 void TargetPassConfig::printNoVerify(const char *Banner) const {
276 if (TM->shouldPrintMachineCode())
277 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
280 void TargetPassConfig::printAndVerify(const char *Banner) const {
281 if (TM->shouldPrintMachineCode())
282 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
284 if (VerifyMachineCode)
285 PM.add(createMachineVerifierPass(Banner));
288 /// addCodeGenPasses - Add standard LLVM codegen passes used for both
289 /// emitting to assembly files or machine code output.
291 bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
292 // Standard LLVM-Level Passes.
294 // Basic AliasAnalysis support.
295 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
296 // BasicAliasAnalysis wins if they disagree. This is intended to help
297 // support "obvious" type-punning idioms.
298 PM.add(createTypeBasedAliasAnalysisPass());
299 PM.add(createBasicAliasAnalysisPass());
301 // Before running any passes, run the verifier to determine if the input
302 // coming from the front-end and/or optimizer is valid.
304 PM.add(createVerifierPass());
306 // Run loop strength reduction before anything else.
307 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
308 PM.add(createLoopStrengthReducePass(getTargetLowering()));
310 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
313 PM.add(createGCLoweringPass());
315 // Make sure that no unreachable blocks are instruction selected.
316 PM.add(createUnreachableBlockEliminationPass());
318 // Turn exception handling constructs into something the code generators can
320 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
321 case ExceptionHandling::SjLj:
322 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
323 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
324 // catch info can get misplaced when a selector ends up more than one block
325 // removed from the parent invoke(s). This could happen when a landing
326 // pad is shared by multiple invokes and is also a target of a normal
327 // edge from elsewhere.
328 PM.add(createSjLjEHPass(getTargetLowering()));
330 case ExceptionHandling::DwarfCFI:
331 case ExceptionHandling::ARM:
332 case ExceptionHandling::Win64:
333 PM.add(createDwarfEHPass(TM));
335 case ExceptionHandling::None:
336 PM.add(createLowerInvokePass(getTargetLowering()));
338 // The lower invoke pass may create unreachable code. Remove it.
339 PM.add(createUnreachableBlockEliminationPass());
343 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
344 PM.add(createCodeGenPreparePass(getTargetLowering()));
346 PM.add(createStackProtectorPass(getTargetLowering()));
351 PM.add(createPrintFunctionPass("\n\n"
352 "*** Final LLVM Code input to ISel ***\n",
355 // All passes which modify the LLVM IR are now complete; run the verifier
356 // to ensure that the IR is valid.
358 PM.add(createVerifierPass());
360 // Standard Lower-Level Passes.
362 // Install a MachineModuleInfo class, which is an immutable pass that holds
363 // all the per-module stuff we're generating, including MCContext.
364 MachineModuleInfo *MMI =
365 new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
366 &getTargetLowering()->getObjFileLowering());
368 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
370 // Set up a MachineFunction for the rest of CodeGen to work on.
371 PM.add(new MachineFunctionAnalysis(*TM));
373 // Enable FastISel with -fast, but allow that to be overridden.
374 if (EnableFastISelOption == cl::BOU_TRUE ||
375 (getOptLevel() == CodeGenOpt::None &&
376 EnableFastISelOption != cl::BOU_FALSE))
377 TM->setFastISel(true);
379 // Ask the target for an isel.
380 if (addInstSelector())
383 // Print the instruction selected machine code...
384 printAndVerify("After Instruction Selection");
386 // Expand pseudo-instructions emitted by ISel.
387 PM.add(createExpandISelPseudosPass());
389 // Pre-ra tail duplication.
390 if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
391 PM.add(createTailDuplicatePass(true));
392 printAndVerify("After Pre-RegAlloc TailDuplicate");
395 // Optimize PHIs before DCE: removing dead PHI cycles may make more
396 // instructions dead.
397 if (getOptLevel() != CodeGenOpt::None)
398 PM.add(createOptimizePHIsPass());
400 // If the target requests it, assign local variables to stack slots relative
401 // to one another and simplify frame index references where possible.
402 PM.add(createLocalStackSlotAllocationPass());
404 if (getOptLevel() != CodeGenOpt::None) {
405 // With optimization, dead code should already be eliminated. However
406 // there is one known exception: lowered code for arguments that are only
407 // used by tail calls, where the tail calls reuse the incoming stack
408 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
409 if (!DisableMachineDCE)
410 PM.add(createDeadMachineInstructionElimPass());
411 printAndVerify("After codegen DCE pass");
413 if (!DisableMachineLICM)
414 PM.add(createMachineLICMPass());
415 if (!DisableMachineCSE)
416 PM.add(createMachineCSEPass());
417 if (!DisableMachineSink)
418 PM.add(createMachineSinkingPass());
419 printAndVerify("After Machine LICM, CSE and Sinking passes");
421 PM.add(createPeepholeOptimizerPass());
422 printAndVerify("After codegen peephole optimization pass");
425 // Run pre-ra passes.
426 if (addPreRegAlloc())
427 printAndVerify("After PreRegAlloc passes");
429 // Perform register allocation.
430 PM.add(createRegisterAllocator(getOptLevel()));
431 printAndVerify("After Register Allocation");
433 // Perform stack slot coloring and post-ra machine LICM.
434 if (getOptLevel() != CodeGenOpt::None) {
435 // FIXME: Re-enable coloring with register when it's capable of adding
438 PM.add(createStackSlotColoringPass(false));
440 // Run post-ra machine LICM to hoist reloads / remats.
441 if (!DisablePostRAMachineLICM)
442 PM.add(createMachineLICMPass(false));
444 printAndVerify("After StackSlotColoring and postra Machine LICM");
447 // Run post-ra passes.
448 if (addPostRegAlloc())
449 printAndVerify("After PostRegAlloc passes");
451 // Insert prolog/epilog code. Eliminate abstract frame index references...
452 PM.add(createPrologEpilogCodeInserter());
453 printAndVerify("After PrologEpilogCodeInserter");
455 // Branch folding must be run after regalloc and prolog/epilog insertion.
456 if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
457 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
458 printNoVerify("After BranchFolding");
462 if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
463 PM.add(createTailDuplicatePass(false));
464 printNoVerify("After TailDuplicate");
468 if (getOptLevel() != CodeGenOpt::None && !DisableCopyProp) {
469 PM.add(createMachineCopyPropagationPass());
470 printNoVerify("After copy propagation pass");
473 // Expand pseudo instructions before second scheduling pass.
474 PM.add(createExpandPostRAPseudosPass());
475 printNoVerify("After ExpandPostRAPseudos");
477 // Run pre-sched2 passes.
479 printNoVerify("After PreSched2 passes");
481 // Second pass scheduler.
482 if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
483 PM.add(createPostRAScheduler(getOptLevel()));
484 printNoVerify("After PostRAScheduler");
487 PM.add(createGCMachineCodeAnalysisPass());
490 PM.add(createGCInfoPrinter(dbgs()));
492 if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
493 if (EnableBlockPlacement) {
494 // MachineBlockPlacement is an experimental pass which is disabled by
495 // default currently. Eventually it should subsume CodePlacementOpt, so
496 // when enabled, the other is disabled.
497 PM.add(createMachineBlockPlacementPass());
498 printNoVerify("After MachineBlockPlacement");
500 PM.add(createCodePlacementOptPass());
501 printNoVerify("After CodePlacementOpt");
504 // Run a separate pass to collect block placement statistics.
505 if (EnableBlockPlacementStats) {
506 PM.add(createMachineBlockPlacementStatsPass());
507 printNoVerify("After MachineBlockPlacementStats");
511 if (addPreEmitPass())
512 printNoVerify("After PreEmit passes");