1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/FormattedStream.h"
32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35 cl::desc("Print LLVM IR input to isel pass"));
36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37 cl::desc("Dump emitter generated instructions as assembly"));
38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39 cl::desc("Dump garbage collector data"));
40 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
41 cl::desc("Verify generated machine code"),
42 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
44 // When this works it will be on by default.
46 DisablePostRAScheduler("disable-post-RA-scheduler",
47 cl::desc("Disable scheduling after register allocation"),
50 // Enable or disable FastISel. Both options are needed, because
51 // FastISel is enabled by default with -fast, and we wish to be
52 // able to enable or disable fast-isel independently from -fast.
53 static cl::opt<cl::boolOrDefault>
54 EnableFastISelOption("fast-isel", cl::Hidden,
55 cl::desc("Enable the experimental \"fast\" instruction selector"));
58 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
59 formatted_raw_ostream &Out,
60 CodeGenFileType FileType,
61 CodeGenOpt::Level OptLevel) {
62 // Add common CodeGen passes.
63 if (addCommonCodeGenPasses(PM, OptLevel))
64 return FileModel::Error;
66 // Fold redundant debug labels.
67 PM.add(createDebugLabelFoldingPass());
70 PM.add(createMachineFunctionPrinterPass(cerr));
72 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
73 PM.add(createMachineFunctionPrinterPass(cerr));
75 if (OptLevel != CodeGenOpt::None)
76 PM.add(createCodePlacementOptPass());
81 case TargetMachine::AssemblyFile:
82 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
83 return FileModel::Error;
84 return FileModel::AsmFile;
85 case TargetMachine::ObjectFile:
86 if (getMachOWriterInfo())
87 return FileModel::MachOFile;
88 else if (getELFWriterInfo())
89 return FileModel::ElfFile;
92 return FileModel::Error;
95 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
96 /// be split up (e.g., to add an object writer pass), this method can be used to
97 /// finish up adding passes to emit the file, if necessary.
98 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
99 MachineCodeEmitter *MCE,
100 CodeGenOpt::Level OptLevel) {
102 addSimpleCodeEmitter(PM, OptLevel, *MCE);
104 addAssemblyEmitter(PM, OptLevel, true, ferrs());
106 PM.add(createGCInfoDeleter());
108 // Delete machine code for this function
109 PM.add(createMachineCodeDeleter());
111 return false; // success!
114 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
115 /// be split up (e.g., to add an object writer pass), this method can be used to
116 /// finish up adding passes to emit the file, if necessary.
117 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
119 CodeGenOpt::Level OptLevel) {
121 addSimpleCodeEmitter(PM, OptLevel, *JCE);
123 addAssemblyEmitter(PM, OptLevel, true, ferrs());
125 PM.add(createGCInfoDeleter());
127 // Delete machine code for this function
128 PM.add(createMachineCodeDeleter());
130 return false; // success!
133 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
134 /// be split up (e.g., to add an object writer pass), this method can be used to
135 /// finish up adding passes to emit the file, if necessary.
136 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
137 ObjectCodeEmitter *OCE,
138 CodeGenOpt::Level OptLevel) {
140 addSimpleCodeEmitter(PM, OptLevel, *OCE);
142 addAssemblyEmitter(PM, OptLevel, true, ferrs());
144 PM.add(createGCInfoDeleter());
146 // Delete machine code for this function
147 PM.add(createMachineCodeDeleter());
149 return false; // success!
152 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
153 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
154 /// actually outputting the machine code and resolving things like the address
155 /// of functions. This method should returns true if machine code emission is
158 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
159 MachineCodeEmitter &MCE,
160 CodeGenOpt::Level OptLevel) {
161 // Add common CodeGen passes.
162 if (addCommonCodeGenPasses(PM, OptLevel))
165 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
166 PM.add(createMachineFunctionPrinterPass(cerr));
168 addCodeEmitter(PM, OptLevel, MCE);
170 addAssemblyEmitter(PM, OptLevel, true, ferrs());
172 PM.add(createGCInfoDeleter());
174 // Delete machine code for this function
175 PM.add(createMachineCodeDeleter());
177 return false; // success!
180 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
181 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
182 /// actually outputting the machine code and resolving things like the address
183 /// of functions. This method should returns true if machine code emission is
186 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
188 CodeGenOpt::Level OptLevel) {
189 // Add common CodeGen passes.
190 if (addCommonCodeGenPasses(PM, OptLevel))
193 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
194 PM.add(createMachineFunctionPrinterPass(cerr));
196 addCodeEmitter(PM, OptLevel, JCE);
198 addAssemblyEmitter(PM, OptLevel, true, ferrs());
200 PM.add(createGCInfoDeleter());
202 // Delete machine code for this function
203 PM.add(createMachineCodeDeleter());
205 return false; // success!
208 static void printAndVerify(PassManagerBase &PM,
209 bool allowDoubleDefs = false) {
210 if (PrintMachineCode)
211 PM.add(createMachineFunctionPrinterPass(cerr));
213 if (VerifyMachineCode)
214 PM.add(createMachineVerifierPass(allowDoubleDefs));
217 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
218 /// emitting to assembly files or machine code output.
220 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
221 CodeGenOpt::Level OptLevel) {
222 // Standard LLVM-Level Passes.
224 // Run loop strength reduction before anything else.
225 if (OptLevel != CodeGenOpt::None) {
226 PM.add(createLoopStrengthReducePass(getTargetLowering()));
228 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
231 // Turn exception handling constructs into something the code generators can
233 if (!getTargetAsmInfo()->doesSupportExceptionHandling())
234 PM.add(createLowerInvokePass(getTargetLowering()));
236 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
238 PM.add(createGCLoweringPass());
240 // Make sure that no unreachable blocks are instruction selected.
241 PM.add(createUnreachableBlockEliminationPass());
243 if (OptLevel != CodeGenOpt::None)
244 PM.add(createCodeGenPreparePass(getTargetLowering()));
246 PM.add(createStackProtectorPass(getTargetLowering()));
249 PM.add(createPrintFunctionPass("\n\n"
250 "*** Final LLVM Code input to ISel ***\n",
253 // Standard Lower-Level Passes.
255 // Enable FastISel with -fast, but allow that to be overridden.
256 if (EnableFastISelOption == cl::BOU_TRUE ||
257 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
258 EnableFastISel = true;
260 // Ask the target for an isel.
261 if (addInstSelector(PM, OptLevel))
264 // Print the instruction selected machine code...
265 printAndVerify(PM, /* allowDoubleDefs= */ true);
267 if (OptLevel != CodeGenOpt::None) {
268 PM.add(createMachineLICMPass());
269 PM.add(createMachineSinkingPass());
270 printAndVerify(PM, /* allowDoubleDefs= */ true);
273 // Run pre-ra passes.
274 if (addPreRegAlloc(PM, OptLevel))
277 // Perform register allocation.
278 PM.add(createRegisterAllocator());
280 // Perform stack slot coloring.
281 if (OptLevel != CodeGenOpt::None)
282 PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
284 printAndVerify(PM); // Print the register-allocated code
286 // Run post-ra passes.
287 if (addPostRegAlloc(PM, OptLevel))
290 PM.add(createLowerSubregsPass());
293 // Insert prolog/epilog code. Eliminate abstract frame index references...
294 PM.add(createPrologEpilogCodeInserter());
297 // Second pass scheduler.
298 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
299 PM.add(createPostRAScheduler());
303 // Branch folding must be run after regalloc and prolog/epilog insertion.
304 if (OptLevel != CodeGenOpt::None) {
305 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
309 PM.add(createGCMachineCodeAnalysisPass());
313 PM.add(createGCInfoPrinter(*cerr));