1 //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The inline spiller modifies the machine function directly instead of
11 // inserting spills and restores in VirtRegMap.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/TinyPtrVector.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
22 #include "llvm/CodeGen/LiveRangeEdit.h"
23 #include "llvm/CodeGen/LiveStackAnalysis.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineInstrBundle.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/VirtRegMap.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
40 STATISTIC(NumSpilledRanges, "Number of spilled live ranges");
41 STATISTIC(NumSnippets, "Number of spilled snippets");
42 STATISTIC(NumSpills, "Number of spills inserted");
43 STATISTIC(NumSpillsRemoved, "Number of spills removed");
44 STATISTIC(NumReloads, "Number of reloads inserted");
45 STATISTIC(NumReloadsRemoved, "Number of reloads removed");
46 STATISTIC(NumFolded, "Number of folded stack accesses");
47 STATISTIC(NumFoldedLoads, "Number of folded loads");
48 STATISTIC(NumRemats, "Number of rematerialized defs for spilling");
49 STATISTIC(NumOmitReloadSpill, "Number of omitted spills of reloads");
50 STATISTIC(NumHoists, "Number of hoisted spills");
52 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
53 cl::desc("Disable inline spill hoisting"));
56 class InlineSpiller : public Spiller {
61 MachineDominatorTree &MDT;
62 MachineLoopInfo &Loops;
64 MachineFrameInfo &MFI;
65 MachineRegisterInfo &MRI;
66 const TargetInstrInfo &TII;
67 const TargetRegisterInfo &TRI;
69 // Variables that are valid during spill(), but used by multiple methods.
71 LiveInterval *StackInt;
75 // All registers to spill to StackSlot, including the main register.
76 SmallVector<unsigned, 8> RegsToSpill;
78 // All COPY instructions to/from snippets.
79 // They are ignored since both operands refer to the same stack slot.
80 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
82 // Values that failed to remat at some point.
83 SmallPtrSet<VNInfo*, 8> UsedValues;
86 // Information about a value that was defined by a copy from a sibling
89 // True when all reaching defs were reloads: No spill is necessary.
90 bool AllDefsAreReloads;
92 // True when value is defined by an original PHI not from splitting.
95 // True when the COPY defining this value killed its source.
98 // The preferred register to spill.
101 // The value of SpillReg that should be spilled.
104 // The block where SpillVNI should be spilled. Currently, this must be the
105 // block containing SpillVNI->def.
106 MachineBasicBlock *SpillMBB;
108 // A defining instruction that is not a sibling copy or a reload, or NULL.
109 // This can be used as a template for rematerialization.
112 // List of values that depend on this one. These values are actually the
113 // same, but live range splitting has placed them in different registers,
114 // or SSA update needed to insert PHI-defs to preserve SSA form. This is
115 // copies of the current value and phi-kills. Usually only phi-kills cause
116 // more than one dependent value.
117 TinyPtrVector<VNInfo*> Deps;
119 SibValueInfo(unsigned Reg, VNInfo *VNI)
120 : AllDefsAreReloads(true), DefByOrigPHI(false), KillsSource(false),
121 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {}
123 // Returns true when a def has been found.
124 bool hasDef() const { return DefByOrigPHI || DefMI; }
128 // Values in RegsToSpill defined by sibling copies.
129 typedef DenseMap<VNInfo*, SibValueInfo> SibValueMap;
130 SibValueMap SibValues;
132 // Dead defs generated during spilling.
133 SmallVector<MachineInstr*, 8> DeadDefs;
138 InlineSpiller(MachineFunctionPass &pass,
142 LIS(pass.getAnalysis<LiveIntervals>()),
143 LSS(pass.getAnalysis<LiveStacks>()),
144 AA(&pass.getAnalysis<AliasAnalysis>()),
145 MDT(pass.getAnalysis<MachineDominatorTree>()),
146 Loops(pass.getAnalysis<MachineLoopInfo>()),
148 MFI(*mf.getFrameInfo()),
149 MRI(mf.getRegInfo()),
150 TII(*mf.getTarget().getInstrInfo()),
151 TRI(*mf.getTarget().getRegisterInfo()) {}
153 void spill(LiveRangeEdit &);
156 bool isSnippet(const LiveInterval &SnipLI);
157 void collectRegsToSpill();
159 bool isRegToSpill(unsigned Reg) {
160 return std::find(RegsToSpill.begin(),
161 RegsToSpill.end(), Reg) != RegsToSpill.end();
164 bool isSibling(unsigned Reg);
165 MachineInstr *traceSiblingValue(unsigned, VNInfo*, VNInfo*);
166 void propagateSiblingValue(SibValueMap::iterator, VNInfo *VNI = 0);
167 void analyzeSiblingValues();
169 bool hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI);
170 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
172 void markValueUsed(LiveInterval*, VNInfo*);
173 bool reMaterializeFor(LiveInterval&, MachineBasicBlock::iterator MI);
174 void reMaterializeAll();
176 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
177 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
178 MachineInstr *LoadMI = 0);
179 void insertReload(LiveInterval &NewLI, SlotIndex,
180 MachineBasicBlock::iterator MI);
181 void insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
182 SlotIndex, MachineBasicBlock::iterator MI);
184 void spillAroundUses(unsigned Reg);
190 Spiller *createInlineSpiller(MachineFunctionPass &pass,
193 return new InlineSpiller(pass, mf, vrm);
197 //===----------------------------------------------------------------------===//
199 //===----------------------------------------------------------------------===//
201 // When spilling a virtual register, we also spill any snippets it is connected
202 // to. The snippets are small live ranges that only have a single real use,
203 // leftovers from live range splitting. Spilling them enables memory operand
204 // folding or tightens the live range around the single use.
206 // This minimizes register pressure and maximizes the store-to-load distance for
207 // spill slots which can be important in tight loops.
209 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
210 /// otherwise return 0.
211 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
212 if (!MI->isFullCopy())
214 if (MI->getOperand(0).getReg() == Reg)
215 return MI->getOperand(1).getReg();
216 if (MI->getOperand(1).getReg() == Reg)
217 return MI->getOperand(0).getReg();
221 /// isSnippet - Identify if a live interval is a snippet that should be spilled.
222 /// It is assumed that SnipLI is a virtual register with the same original as
224 bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
225 unsigned Reg = Edit->getReg();
227 // A snippet is a tiny live range with only a single instruction using it
228 // besides copies to/from Reg or spills/fills. We accept:
230 // %snip = COPY %Reg / FILL fi#
232 // %Reg = COPY %snip / SPILL %snip, fi#
234 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
237 MachineInstr *UseMI = 0;
239 // Check that all uses satisfy our criteria.
240 for (MachineRegisterInfo::reg_nodbg_iterator
241 RI = MRI.reg_nodbg_begin(SnipLI.reg);
242 MachineInstr *MI = RI.skipInstruction();) {
244 // Allow copies to/from Reg.
245 if (isFullCopyOf(MI, Reg))
248 // Allow stack slot loads.
250 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
253 // Allow stack slot stores.
254 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
257 // Allow a single additional instruction.
258 if (UseMI && MI != UseMI)
265 /// collectRegsToSpill - Collect live range snippets that only have a single
267 void InlineSpiller::collectRegsToSpill() {
268 unsigned Reg = Edit->getReg();
270 // Main register always spills.
271 RegsToSpill.assign(1, Reg);
272 SnippetCopies.clear();
274 // Snippets all have the same original, so there can't be any for an original
279 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Reg);
280 MachineInstr *MI = RI.skipInstruction();) {
281 unsigned SnipReg = isFullCopyOf(MI, Reg);
282 if (!isSibling(SnipReg))
284 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
285 if (!isSnippet(SnipLI))
287 SnippetCopies.insert(MI);
288 if (isRegToSpill(SnipReg))
290 RegsToSpill.push_back(SnipReg);
291 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 // After live range splitting, some values to be spilled may be defined by
302 // copies from sibling registers. We trace the sibling copies back to the
303 // original value if it still exists. We need it for rematerialization.
305 // Even when the value can't be rematerialized, we still want to determine if
306 // the value has already been spilled, or we may want to hoist the spill from a
309 bool InlineSpiller::isSibling(unsigned Reg) {
310 return TargetRegisterInfo::isVirtualRegister(Reg) &&
311 VRM.getOriginal(Reg) == Original;
315 static raw_ostream &operator<<(raw_ostream &OS,
316 const InlineSpiller::SibValueInfo &SVI) {
317 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
318 << SVI.SpillVNI->id << '@' << SVI.SpillVNI->def;
320 OS << " in BB#" << SVI.SpillMBB->getNumber();
321 if (SVI.AllDefsAreReloads)
322 OS << " all-reloads";
323 if (SVI.DefByOrigPHI)
328 for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
329 OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
332 OS << " def: " << *SVI.DefMI;
339 /// propagateSiblingValue - Propagate the value in SVI to dependents if it is
340 /// known. Otherwise remember the dependency for later.
342 /// @param SVIIter SibValues entry to propagate.
343 /// @param VNI Dependent value, or NULL to propagate to all saved dependents.
344 void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVIIter,
346 SibValueMap::value_type *SVI = &*SVIIter;
348 // When VNI is non-NULL, add it to SVI's deps, and only propagate to that.
349 TinyPtrVector<VNInfo*> FirstDeps;
351 FirstDeps.push_back(VNI);
352 SVI->second.Deps.push_back(VNI);
355 // Has the value been completely determined yet? If not, defer propagation.
356 if (!SVI->second.hasDef())
359 // Work list of values to propagate.
360 SmallSetVector<SibValueMap::value_type *, 8> WorkList;
361 WorkList.insert(SVI);
364 SVI = WorkList.pop_back_val();
365 TinyPtrVector<VNInfo*> *Deps = VNI ? &FirstDeps : &SVI->second.Deps;
368 SibValueInfo &SV = SVI->second;
370 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
372 DEBUG(dbgs() << " prop to " << Deps->size() << ": "
373 << SVI->first->id << '@' << SVI->first->def << ":\t" << SV);
375 assert(SV.hasDef() && "Propagating undefined value");
377 // Should this value be propagated as a preferred spill candidate? We don't
378 // propagate values of registers that are about to spill.
379 bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
380 unsigned SpillDepth = ~0u;
382 for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
383 DepE = Deps->end(); DepI != DepE; ++DepI) {
384 SibValueMap::iterator DepSVI = SibValues.find(*DepI);
385 assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
386 SibValueInfo &DepSV = DepSVI->second;
388 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
390 bool Changed = false;
392 // Propagate defining instruction.
393 if (!DepSV.hasDef()) {
395 DepSV.DefMI = SV.DefMI;
396 DepSV.DefByOrigPHI = SV.DefByOrigPHI;
399 // Propagate AllDefsAreReloads. For PHI values, this computes an AND of
401 if (!SV.AllDefsAreReloads && DepSV.AllDefsAreReloads) {
403 DepSV.AllDefsAreReloads = false;
406 // Propagate best spill value.
407 if (PropSpill && SV.SpillVNI != DepSV.SpillVNI) {
408 if (SV.SpillMBB == DepSV.SpillMBB) {
409 // DepSV is in the same block. Hoist when dominated.
410 if (DepSV.KillsSource && SV.SpillVNI->def < DepSV.SpillVNI->def) {
411 // This is an alternative def earlier in the same MBB.
412 // Hoist the spill as far as possible in SpillMBB. This can ease
413 // register pressure:
419 // Hoisting the spill of s to immediately after the def removes the
420 // interference between x and y:
426 // This hoist only helps when the DepSV copy kills its source.
428 DepSV.SpillReg = SV.SpillReg;
429 DepSV.SpillVNI = SV.SpillVNI;
430 DepSV.SpillMBB = SV.SpillMBB;
433 // DepSV is in a different block.
434 if (SpillDepth == ~0u)
435 SpillDepth = Loops.getLoopDepth(SV.SpillMBB);
437 // Also hoist spills to blocks with smaller loop depth, but make sure
438 // that the new value dominates. Non-phi dependents are always
439 // dominated, phis need checking.
440 if ((Loops.getLoopDepth(DepSV.SpillMBB) > SpillDepth) &&
441 (!DepSVI->first->isPHIDef() ||
442 MDT.dominates(SV.SpillMBB, DepSV.SpillMBB))) {
444 DepSV.SpillReg = SV.SpillReg;
445 DepSV.SpillVNI = SV.SpillVNI;
446 DepSV.SpillMBB = SV.SpillMBB;
454 // Something changed in DepSVI. Propagate to dependents.
455 WorkList.insert(&*DepSVI);
457 DEBUG(dbgs() << " update " << DepSVI->first->id << '@'
458 << DepSVI->first->def << " to:\t" << DepSV);
460 } while (!WorkList.empty());
463 /// traceSiblingValue - Trace a value that is about to be spilled back to the
464 /// real defining instructions by looking through sibling copies. Always stay
465 /// within the range of OrigVNI so the registers are known to carry the same
468 /// Determine if the value is defined by all reloads, so spilling isn't
469 /// necessary - the value is already in the stack slot.
471 /// Return a defining instruction that may be a candidate for rematerialization.
473 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
475 // Check if a cached value already exists.
476 SibValueMap::iterator SVI;
479 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI)));
481 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
482 << UseVNI->id << '@' << UseVNI->def << ' ' << SVI->second);
483 return SVI->second.DefMI;
486 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
487 << UseVNI->id << '@' << UseVNI->def << '\n');
489 // List of (Reg, VNI) that have been inserted into SibValues, but need to be
491 SmallVector<std::pair<unsigned, VNInfo*>, 8> WorkList;
492 WorkList.push_back(std::make_pair(UseReg, UseVNI));
497 tie(Reg, VNI) = WorkList.pop_back_val();
498 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
501 // First check if this value has already been computed.
502 SVI = SibValues.find(VNI);
503 assert(SVI != SibValues.end() && "Missing SibValues entry");
505 // Trace through PHI-defs created by live range splitting.
506 if (VNI->isPHIDef()) {
507 // Stop at original PHIs. We don't know the value at the predecessors.
508 if (VNI->def == OrigVNI->def) {
509 DEBUG(dbgs() << "orig phi value\n");
510 SVI->second.DefByOrigPHI = true;
511 SVI->second.AllDefsAreReloads = false;
512 propagateSiblingValue(SVI);
516 // This is a PHI inserted by live range splitting. We could trace the
517 // live-out value from predecessor blocks, but that search can be very
518 // expensive if there are many predecessors and many more PHIs as
519 // generated by tail-dup when it sees an indirectbr. Instead, look at
520 // all the non-PHI defs that have the same value as OrigVNI. They must
521 // jointly dominate VNI->def. This is not optimal since VNI may actually
522 // be jointly dominated by a smaller subset of defs, so there is a change
523 // we will miss a AllDefsAreReloads optimization.
525 // Separate all values dominated by OrigVNI into PHIs and non-PHIs.
526 SmallVector<VNInfo*, 8> PHIs, NonPHIs;
527 LiveInterval &LI = LIS.getInterval(Reg);
528 LiveInterval &OrigLI = LIS.getInterval(Original);
530 for (LiveInterval::vni_iterator VI = LI.vni_begin(), VE = LI.vni_end();
533 if (VNI2->isUnused())
535 if (!OrigLI.containsOneValue() &&
536 OrigLI.getVNInfoAt(VNI2->def) != OrigVNI)
538 if (VNI2->isPHIDef() && VNI2->def != OrigVNI->def)
539 PHIs.push_back(VNI2);
541 NonPHIs.push_back(VNI2);
543 DEBUG(dbgs() << "split phi value, checking " << PHIs.size()
544 << " phi-defs, and " << NonPHIs.size()
545 << " non-phi/orig defs\n");
547 // Create entries for all the PHIs. Don't add them to the worklist, we
548 // are processing all of them in one go here.
549 for (unsigned i = 0, e = PHIs.size(); i != e; ++i)
550 SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
552 // Add every PHI as a dependent of all the non-PHIs.
553 for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) {
554 VNInfo *NonPHI = NonPHIs[i];
555 // Known value? Try an insertion.
557 SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
558 // Add all the PHIs as dependents of NonPHI.
559 for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi)
560 SVI->second.Deps.push_back(PHIs[pi]);
561 // This is the first time we see NonPHI, add it to the worklist.
563 WorkList.push_back(std::make_pair(Reg, NonPHI));
565 // Propagate to all inserted PHIs, not just VNI.
566 propagateSiblingValue(SVI);
569 // Next work list item.
573 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
574 assert(MI && "Missing def");
576 // Trace through sibling copies.
577 if (unsigned SrcReg = isFullCopyOf(MI, Reg)) {
578 if (isSibling(SrcReg)) {
579 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
580 LiveRangeQuery SrcQ(SrcLI, VNI->def);
581 assert(SrcQ.valueIn() && "Copy from non-existing value");
582 // Check if this COPY kills its source.
583 SVI->second.KillsSource = SrcQ.isKill();
584 VNInfo *SrcVNI = SrcQ.valueIn();
585 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
586 << SrcVNI->id << '@' << SrcVNI->def
587 << " kill=" << unsigned(SVI->second.KillsSource) << '\n');
588 // Known sibling source value? Try an insertion.
589 tie(SVI, Inserted) = SibValues.insert(std::make_pair(SrcVNI,
590 SibValueInfo(SrcReg, SrcVNI)));
591 // This is the first time we see Src, add it to the worklist.
593 WorkList.push_back(std::make_pair(SrcReg, SrcVNI));
594 propagateSiblingValue(SVI, VNI);
595 // Next work list item.
600 // Track reachable reloads.
601 SVI->second.DefMI = MI;
602 SVI->second.SpillMBB = MI->getParent();
604 if (Reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) {
605 DEBUG(dbgs() << "reload\n");
606 propagateSiblingValue(SVI);
607 // Next work list item.
611 // Potential remat candidate.
612 DEBUG(dbgs() << "def " << *MI);
613 SVI->second.AllDefsAreReloads = false;
614 propagateSiblingValue(SVI);
615 } while (!WorkList.empty());
617 // Look up the value we were looking for. We already did this lookup at the
618 // top of the function, but SibValues may have been invalidated.
619 SVI = SibValues.find(UseVNI);
620 assert(SVI != SibValues.end() && "Didn't compute requested info");
621 DEBUG(dbgs() << " traced to:\t" << SVI->second);
622 return SVI->second.DefMI;
625 /// analyzeSiblingValues - Trace values defined by sibling copies back to
626 /// something that isn't a sibling copy.
628 /// Keep track of values that may be rematerializable.
629 void InlineSpiller::analyzeSiblingValues() {
632 // No siblings at all?
633 if (Edit->getReg() == Original)
636 LiveInterval &OrigLI = LIS.getInterval(Original);
637 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
638 unsigned Reg = RegsToSpill[i];
639 LiveInterval &LI = LIS.getInterval(Reg);
640 for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
641 VE = LI.vni_end(); VI != VE; ++VI) {
645 MachineInstr *DefMI = 0;
646 if (!VNI->isPHIDef()) {
647 DefMI = LIS.getInstructionFromIndex(VNI->def);
648 assert(DefMI && "No defining instruction");
650 // Check possible sibling copies.
651 if (VNI->isPHIDef() || DefMI->isCopy()) {
652 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
653 assert(OrigVNI && "Def outside original live range");
654 if (OrigVNI->def != VNI->def)
655 DefMI = traceSiblingValue(Reg, VNI, OrigVNI);
657 if (DefMI && Edit->checkRematerializable(VNI, DefMI, AA)) {
658 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
659 << VNI->def << " may remat from " << *DefMI);
665 /// hoistSpill - Given a sibling copy that defines a value to be spilled, insert
666 /// a spill at a better location.
667 bool InlineSpiller::hoistSpill(LiveInterval &SpillLI, MachineInstr *CopyMI) {
668 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
669 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
670 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
671 SibValueMap::iterator I = SibValues.find(VNI);
672 if (I == SibValues.end())
675 const SibValueInfo &SVI = I->second;
677 // Let the normal folding code deal with the boring case.
678 if (!SVI.AllDefsAreReloads && SVI.SpillVNI == VNI)
681 // SpillReg may have been deleted by remat and DCE.
682 if (!LIS.hasInterval(SVI.SpillReg)) {
683 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
688 LiveInterval &SibLI = LIS.getInterval(SVI.SpillReg);
689 if (!SibLI.containsValue(SVI.SpillVNI)) {
690 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
695 // Conservatively extend the stack slot range to the range of the original
696 // value. We may be able to do better with stack slot coloring by being more
698 assert(StackInt && "No stack slot assigned yet.");
699 LiveInterval &OrigLI = LIS.getInterval(Original);
700 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
701 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
702 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
703 << *StackInt << '\n');
705 // Already spilled everywhere.
706 if (SVI.AllDefsAreReloads) {
707 DEBUG(dbgs() << "\tno spill needed: " << SVI);
708 ++NumOmitReloadSpill;
711 // We are going to spill SVI.SpillVNI immediately after its def, so clear out
712 // any later spills of the same value.
713 eliminateRedundantSpills(SibLI, SVI.SpillVNI);
715 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
716 MachineBasicBlock::iterator MII;
717 if (SVI.SpillVNI->isPHIDef())
718 MII = MBB->SkipPHIsAndLabels(MBB->begin());
720 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def);
721 assert(DefMI && "Defining instruction disappeared");
725 // Insert spill without kill flag immediately after def.
726 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
727 MRI.getRegClass(SVI.SpillReg), &TRI);
728 --MII; // Point to store instruction.
729 LIS.InsertMachineInstrInMaps(MII);
730 DEBUG(dbgs() << "\thoisted: " << SVI.SpillVNI->def << '\t' << *MII);
737 /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
738 /// redundant spills of this value in SLI.reg and sibling copies.
739 void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
740 assert(VNI && "Missing value");
741 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
742 WorkList.push_back(std::make_pair(&SLI, VNI));
743 assert(StackInt && "No stack slot assigned yet.");
747 tie(LI, VNI) = WorkList.pop_back_val();
748 unsigned Reg = LI->reg;
749 DEBUG(dbgs() << "Checking redundant spills for "
750 << VNI->id << '@' << VNI->def << " in " << *LI << '\n');
752 // Regs to spill are taken care of.
753 if (isRegToSpill(Reg))
756 // Add all of VNI's live range to StackInt.
757 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
758 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
760 // Find all spills and copies of VNI.
761 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI.use_nodbg_begin(Reg);
762 MachineInstr *MI = UI.skipInstruction();) {
763 if (!MI->isCopy() && !MI->mayStore())
765 SlotIndex Idx = LIS.getInstructionIndex(MI);
766 if (LI->getVNInfoAt(Idx) != VNI)
769 // Follow sibling copies down the dominator tree.
770 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
771 if (isSibling(DstReg)) {
772 LiveInterval &DstLI = LIS.getInterval(DstReg);
773 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
774 assert(DstVNI && "Missing defined value");
775 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
776 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
783 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
784 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << *MI);
785 // eliminateDeadDefs won't normally remove stores, so switch opcode.
786 MI->setDesc(TII.get(TargetOpcode::KILL));
787 DeadDefs.push_back(MI);
792 } while (!WorkList.empty());
796 //===----------------------------------------------------------------------===//
798 //===----------------------------------------------------------------------===//
800 /// markValueUsed - Remember that VNI failed to rematerialize, so its defining
801 /// instruction cannot be eliminated. See through snippet copies
802 void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
803 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
804 WorkList.push_back(std::make_pair(LI, VNI));
806 tie(LI, VNI) = WorkList.pop_back_val();
807 if (!UsedValues.insert(VNI))
810 if (VNI->isPHIDef()) {
811 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
812 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
813 PE = MBB->pred_end(); PI != PE; ++PI) {
814 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI));
816 WorkList.push_back(std::make_pair(LI, PVNI));
821 // Follow snippet copies.
822 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
823 if (!SnippetCopies.count(MI))
825 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
826 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy");
827 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
828 assert(SnipVNI && "Snippet undefined before copy");
829 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
830 } while (!WorkList.empty());
833 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
834 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
835 MachineBasicBlock::iterator MI) {
836 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
840 DEBUG(dbgs() << "\tadding <undef> flags: ");
841 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
842 MachineOperand &MO = MI->getOperand(i);
843 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
846 DEBUG(dbgs() << UseIdx << '\t' << *MI);
850 if (SnippetCopies.count(MI))
853 // Use an OrigVNI from traceSiblingValue when ParentVNI is a sibling copy.
854 LiveRangeEdit::Remat RM(ParentVNI);
855 SibValueMap::const_iterator SibI = SibValues.find(ParentVNI);
856 if (SibI != SibValues.end())
857 RM.OrigMI = SibI->second.DefMI;
858 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
859 markValueUsed(&VirtReg, ParentVNI);
860 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
864 // If the instruction also writes VirtReg.reg, it had better not require the
865 // same register for uses and defs.
866 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
867 MIBundleOperands::VirtRegInfo RI =
868 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
870 markValueUsed(&VirtReg, ParentVNI);
871 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
875 // Before rematerializing into a register for a single instruction, try to
876 // fold a load into the instruction. That avoids allocating a new register.
877 if (RM.OrigMI->canFoldAsLoad() &&
878 foldMemoryOperand(Ops, RM.OrigMI)) {
879 Edit->markRematerialized(RM.ParentVNI);
884 // Alocate a new register for the remat.
885 LiveInterval &NewLI = Edit->createFrom(Original);
886 NewLI.markNotSpillable();
888 // Finally we can rematerialize OrigMI before MI.
889 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
891 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
892 << *LIS.getInstructionFromIndex(DefIdx));
895 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
896 MachineOperand &MO = MI->getOperand(Ops[i].second);
897 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
898 MO.setReg(NewLI.reg);
902 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
904 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, LIS.getVNInfoAllocator());
905 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
906 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
911 /// reMaterializeAll - Try to rematerialize as many uses as possible,
912 /// and trim the live ranges after.
913 void InlineSpiller::reMaterializeAll() {
914 // analyzeSiblingValues has already tested all relevant defining instructions.
915 if (!Edit->anyRematerializable(AA))
920 // Try to remat before all uses of snippets.
921 bool anyRemat = false;
922 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
923 unsigned Reg = RegsToSpill[i];
924 LiveInterval &LI = LIS.getInterval(Reg);
925 for (MachineRegisterInfo::use_nodbg_iterator
926 RI = MRI.use_nodbg_begin(Reg);
927 MachineInstr *MI = RI.skipBundle();)
928 anyRemat |= reMaterializeFor(LI, MI);
933 // Remove any values that were completely rematted.
934 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
935 unsigned Reg = RegsToSpill[i];
936 LiveInterval &LI = LIS.getInterval(Reg);
937 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
940 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
942 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
943 MI->addRegisterDead(Reg, &TRI);
944 if (!MI->allDefsAreDead())
946 DEBUG(dbgs() << "All defs dead: " << *MI);
947 DeadDefs.push_back(MI);
951 // Eliminate dead code after remat. Note that some snippet copies may be
953 if (DeadDefs.empty())
955 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
956 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
958 // Get rid of deleted and empty intervals.
959 unsigned ResultPos = 0;
960 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
961 unsigned Reg = RegsToSpill[i];
962 if (!LIS.hasInterval(Reg))
965 LiveInterval &LI = LIS.getInterval(Reg);
967 Edit->eraseVirtReg(Reg);
971 RegsToSpill[ResultPos++] = Reg;
973 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
974 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
978 //===----------------------------------------------------------------------===//
980 //===----------------------------------------------------------------------===//
982 /// If MI is a load or store of StackSlot, it can be removed.
983 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
985 unsigned InstrReg = TII.isLoadFromStackSlot(MI, FI);
986 bool IsLoad = InstrReg;
988 InstrReg = TII.isStoreToStackSlot(MI, FI);
990 // We have a stack access. Is it the right register and slot?
991 if (InstrReg != Reg || FI != StackSlot)
994 DEBUG(dbgs() << "Coalescing stack access: " << *MI);
995 LIS.RemoveMachineInstrFromMaps(MI);
996 MI->eraseFromParent();
1009 /// foldMemoryOperand - Try folding stack slot references in Ops into their
1012 /// @param Ops Operand indices from analyzeVirtReg().
1013 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
1014 /// @return True on success.
1015 bool InlineSpiller::
1016 foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
1017 MachineInstr *LoadMI) {
1020 // Don't attempt folding in bundles.
1021 MachineInstr *MI = Ops.front().first;
1022 if (Ops.back().first != MI || MI->isBundled())
1025 bool WasCopy = MI->isCopy();
1026 unsigned ImpReg = 0;
1028 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
1030 SmallVector<unsigned, 8> FoldOps;
1031 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1032 unsigned Idx = Ops[i].second;
1033 MachineOperand &MO = MI->getOperand(Idx);
1034 if (MO.isImplicit()) {
1035 ImpReg = MO.getReg();
1038 // FIXME: Teach targets to deal with subregs.
1041 // We cannot fold a load instruction into a def.
1042 if (LoadMI && MO.isDef())
1044 // Tied use operands should not be passed to foldMemoryOperand.
1045 if (!MI->isRegTiedToDefOperand(Idx))
1046 FoldOps.push_back(Idx);
1049 MachineInstr *FoldMI =
1050 LoadMI ? TII.foldMemoryOperand(MI, FoldOps, LoadMI)
1051 : TII.foldMemoryOperand(MI, FoldOps, StackSlot);
1054 LIS.ReplaceMachineInstrInMaps(MI, FoldMI);
1055 MI->eraseFromParent();
1057 // TII.foldMemoryOperand may have left some implicit operands on the
1058 // instruction. Strip them.
1060 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
1061 MachineOperand &MO = FoldMI->getOperand(i - 1);
1062 if (!MO.isReg() || !MO.isImplicit())
1064 if (MO.getReg() == ImpReg)
1065 FoldMI->RemoveOperand(i - 1);
1068 DEBUG(dbgs() << "\tfolded: " << LIS.getInstructionIndex(FoldMI) << '\t'
1072 else if (Ops.front().second == 0)
1079 /// insertReload - Insert a reload of NewLI.reg before MI.
1080 void InlineSpiller::insertReload(LiveInterval &NewLI,
1082 MachineBasicBlock::iterator MI) {
1083 MachineBasicBlock &MBB = *MI->getParent();
1084 TII.loadRegFromStackSlot(MBB, MI, NewLI.reg, StackSlot,
1085 MRI.getRegClass(NewLI.reg), &TRI);
1086 --MI; // Point to load instruction.
1087 SlotIndex LoadIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
1088 // Some (out-of-tree) targets have EC reload instructions.
1089 if (MachineOperand *MO = MI->findRegisterDefOperand(NewLI.reg))
1090 if (MO->isEarlyClobber())
1091 LoadIdx = LoadIdx.getRegSlot(true);
1092 DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
1093 VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, LIS.getVNInfoAllocator());
1094 NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
1098 /// insertSpill - Insert a spill of NewLI.reg after MI.
1099 void InlineSpiller::insertSpill(LiveInterval &NewLI, const LiveInterval &OldLI,
1100 SlotIndex Idx, MachineBasicBlock::iterator MI) {
1101 MachineBasicBlock &MBB = *MI->getParent();
1102 TII.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, StackSlot,
1103 MRI.getRegClass(NewLI.reg), &TRI);
1104 --MI; // Point to store instruction.
1105 SlotIndex StoreIdx = LIS.InsertMachineInstrInMaps(MI).getRegSlot();
1106 DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
1107 VNInfo *StoreVNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
1108 NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
1112 /// spillAroundUses - insert spill code around each use of Reg.
1113 void InlineSpiller::spillAroundUses(unsigned Reg) {
1114 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
1115 LiveInterval &OldLI = LIS.getInterval(Reg);
1117 // Iterate over instructions using Reg.
1118 for (MachineRegisterInfo::reg_iterator RegI = MRI.reg_begin(Reg);
1119 MachineInstr *MI = RegI.skipBundle();) {
1121 // Debug values are not allowed to affect codegen.
1122 if (MI->isDebugValue()) {
1123 // Modify DBG_VALUE now that the value is in a spill slot.
1124 uint64_t Offset = MI->getOperand(1).getImm();
1125 const MDNode *MDPtr = MI->getOperand(2).getMetadata();
1126 DebugLoc DL = MI->getDebugLoc();
1127 DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
1128 MachineBasicBlock *MBB = MI->getParent();
1129 BuildMI(*MBB, MBB->erase(MI), DL, TII.get(TargetOpcode::DBG_VALUE))
1130 .addFrameIndex(StackSlot).addImm(Offset).addMetadata(MDPtr);
1134 // Ignore copies to/from snippets. We'll delete them.
1135 if (SnippetCopies.count(MI))
1138 // Stack slot accesses may coalesce away.
1139 if (coalesceStackAccess(MI, Reg))
1142 // Analyze instruction.
1143 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
1144 MIBundleOperands::VirtRegInfo RI =
1145 MIBundleOperands(MI).analyzeVirtReg(Reg, &Ops);
1147 // Find the slot index where this instruction reads and writes OldLI.
1148 // This is usually the def slot, except for tied early clobbers.
1149 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
1150 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1151 if (SlotIndex::isSameInstr(Idx, VNI->def))
1154 // Check for a sibling copy.
1155 unsigned SibReg = isFullCopyOf(MI, Reg);
1156 if (SibReg && isSibling(SibReg)) {
1157 // This may actually be a copy between snippets.
1158 if (isRegToSpill(SibReg)) {
1159 DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1160 SnippetCopies.insert(MI);
1164 // Hoist the spill of a sib-reg copy.
1165 if (hoistSpill(OldLI, MI)) {
1166 // This COPY is now dead, the value is already in the stack slot.
1167 MI->getOperand(0).setIsDead();
1168 DeadDefs.push_back(MI);
1172 // This is a reload for a sib-reg copy. Drop spills downstream.
1173 LiveInterval &SibLI = LIS.getInterval(SibReg);
1174 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
1175 // The COPY will fold to a reload below.
1179 // Attempt to fold memory ops.
1180 if (foldMemoryOperand(Ops))
1183 // Allocate interval around instruction.
1184 // FIXME: Infer regclass from instruction alone.
1185 LiveInterval &NewLI = Edit->createFrom(Reg);
1186 NewLI.markNotSpillable();
1189 insertReload(NewLI, Idx, MI);
1191 // Rewrite instruction operands.
1192 bool hasLiveDef = false;
1193 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1194 MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
1195 MO.setReg(NewLI.reg);
1197 if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second))
1204 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
1206 // FIXME: Use a second vreg if instruction has no tied ops.
1209 insertSpill(NewLI, OldLI, Idx, MI);
1211 // This instruction defines a dead value. We don't need to spill it,
1212 // but do create a live range for the dead value.
1213 VNInfo *VNI = NewLI.getNextValue(Idx, LIS.getVNInfoAllocator());
1214 NewLI.addRange(LiveRange(Idx, Idx.getDeadSlot(), VNI));
1218 DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
1222 /// spillAll - Spill all registers remaining after rematerialization.
1223 void InlineSpiller::spillAll() {
1224 // Update LiveStacks now that we are committed to spilling.
1225 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1226 StackSlot = VRM.assignVirt2StackSlot(Original);
1227 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1228 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1230 StackInt = &LSS.getInterval(StackSlot);
1232 if (Original != Edit->getReg())
1233 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1235 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
1236 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1237 StackInt->MergeRangesInAsValue(LIS.getInterval(RegsToSpill[i]),
1238 StackInt->getValNumInfo(0));
1239 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
1241 // Spill around uses of all RegsToSpill.
1242 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1243 spillAroundUses(RegsToSpill[i]);
1245 // Hoisted spills may cause dead code.
1246 if (!DeadDefs.empty()) {
1247 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
1248 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill);
1251 // Finally delete the SnippetCopies.
1252 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
1253 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(RegsToSpill[i]);
1254 MachineInstr *MI = RI.skipInstruction();) {
1255 assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
1256 // FIXME: Do this with a LiveRangeEdit callback.
1257 LIS.RemoveMachineInstrFromMaps(MI);
1258 MI->eraseFromParent();
1262 // Delete all spilled registers.
1263 for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
1264 Edit->eraseVirtReg(RegsToSpill[i]);
1267 void InlineSpiller::spill(LiveRangeEdit &edit) {
1270 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())
1271 && "Trying to spill a stack slot.");
1272 // Share a stack slot among all descendants of Original.
1273 Original = VRM.getOriginal(edit.getReg());
1274 StackSlot = VRM.getStackSlot(Original);
1277 DEBUG(dbgs() << "Inline spilling "
1278 << MRI.getRegClass(edit.getReg())->getName()
1279 << ':' << PrintReg(edit.getReg()) << ' ' << edit.getParent()
1280 << "\nFrom original " << LIS.getInterval(Original) << '\n');
1281 assert(edit.getParent().isSpillable() &&
1282 "Attempting to spill already spilled value.");
1283 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
1285 collectRegsToSpill();
1286 analyzeSiblingValues();
1289 // Remat may handle everything.
1290 if (!RegsToSpill.empty())
1293 Edit->calculateRegClassAndHint(MF, Loops);