1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "llvm/ADT/SmallBitVector.h"
16 #include "llvm/Support/Dwarf.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
24 void DwarfExpression::AddReg(int DwarfReg, const char* Comment) {
25 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
29 EmitOp(dwarf::DW_OP_regx, Comment);
30 EmitUnsigned(DwarfReg);
34 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
35 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
39 EmitOp(dwarf::DW_OP_bregx);
40 EmitUnsigned(DwarfReg);
44 EmitOp(dwarf::DW_OP_deref);
47 void DwarfExpression::AddOpPiece(unsigned SizeInBits,
48 unsigned OffsetInBits) {
49 assert(SizeInBits > 0 && "piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
53 EmitUnsigned(SizeInBits);
54 EmitUnsigned(OffsetInBits);
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
58 EmitUnsigned(ByteSize);
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63 EmitOp(dwarf::DW_OP_constu);
64 EmitUnsigned(ShiftBy);
65 EmitOp(dwarf::DW_OP_shr);
68 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
69 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
70 int DwarfReg = TRI->getDwarfRegNum(MachineReg, false);
74 if (MachineReg == getFrameRegister()) {
75 // If variable offset is based in frame register then use fbreg.
76 EmitOp(dwarf::DW_OP_fbreg);
79 AddRegIndirect(DwarfReg, Offset);
84 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
85 unsigned PieceSizeInBits,
86 unsigned PieceOffsetInBits) {
87 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
88 int Reg = TRI->getDwarfRegNum(MachineReg, false);
90 // If this is a valid register number, emit it.
94 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
98 // Walk up the super-register chain until we find a valid number.
99 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
100 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
101 Reg = TRI->getDwarfRegNum(*SR, false);
103 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
104 unsigned Size = TRI->getSubRegIdxSize(Idx);
105 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
106 AddReg(Reg, "super-register");
107 if (PieceOffsetInBits == RegOffset) {
108 AddOpPiece(Size, RegOffset);
110 // If this is part of a variable in a sub-register at a
111 // non-zero offset, we need to manually shift the value into
112 // place, since the DW_OP_piece describes the part of the
113 // variable, not the position of the subregister.
116 AddOpPiece(Size, PieceOffsetInBits);
122 // Otherwise, attempt to find a covering set of sub-register numbers.
123 // For example, Q0 on ARM is a composition of D0+D1.
125 // Keep track of the current position so we can emit the more
126 // efficient DW_OP_piece.
127 unsigned CurPos = PieceOffsetInBits;
128 // The size of the register in bits, assuming 8 bits per byte.
129 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
130 // Keep track of the bits in the register we already emitted, so we
131 // can avoid emitting redundant aliasing subregs.
132 SmallBitVector Coverage(RegSize, false);
133 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
134 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
135 unsigned Size = TRI->getSubRegIdxSize(Idx);
136 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
137 Reg = TRI->getDwarfRegNum(*SR, false);
139 // Intersection between the bits we already emitted and the bits
140 // covered by this subregister.
141 SmallBitVector Intersection(RegSize, false);
142 Intersection.set(Offset, Offset + Size);
143 Intersection ^= Coverage;
145 // If this sub-register has a DWARF number and we haven't covered
146 // its range, emit a DWARF piece for it.
147 if (Reg >= 0 && Intersection.any()) {
148 AddReg(Reg, "sub-register");
149 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
150 CurPos = Offset + Size;
152 // Mark it as emitted.
153 Coverage.set(Offset, Offset + Size);
157 if (CurPos == PieceOffsetInBits)
158 // FIXME: We have no reasonable way of handling errors in here.
159 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");