1 //=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
18 #define LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
20 #include "AntiDepBreaker.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/Target/TargetSubtarget.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/SmallSet.h"
33 class TargetRegisterInfo;
34 /// Class AggressiveAntiDepState
35 /// Contains all the state necessary for anti-dep breaking.
36 class AggressiveAntiDepState {
38 /// RegisterReference - Information about a register reference
39 /// within a liverange
41 /// Operand - The registers operand
42 MachineOperand *Operand;
43 /// RC - The register class
44 const TargetRegisterClass *RC;
48 /// NumTargetRegs - Number of non-virtual target registers
49 /// (i.e. TRI->getNumRegs()).
50 const unsigned NumTargetRegs;
52 /// GroupNodes - Implements a disjoint-union data structure to
53 /// form register groups. A node is represented by an index into
54 /// the vector. A node can "point to" itself to indicate that it
55 /// is the parent of a group, or point to another node to indicate
56 /// that it is a member of the same group as that node.
57 std::vector<unsigned> GroupNodes;
59 /// GroupNodeIndices - For each register, the index of the GroupNode
60 /// currently representing the group that the register belongs to.
61 /// Register 0 is always represented by the 0 group, a group
62 /// composed of registers that are not eligible for anti-aliasing.
63 std::vector<unsigned> GroupNodeIndices;
65 /// RegRefs - Map registers to all their references within a live range.
66 std::multimap<unsigned, RegisterReference> RegRefs;
68 /// KillIndices - The index of the most recent kill (proceding bottom-up),
69 /// or ~0u if the register is not live.
70 std::vector<unsigned> KillIndices;
72 /// DefIndices - The index of the most recent complete def (proceding bottom
73 /// up), or ~0u if the register is live.
74 std::vector<unsigned> DefIndices;
77 AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB);
79 /// GetKillIndices - Return the kill indices.
80 std::vector<unsigned> &GetKillIndices() { return KillIndices; }
82 /// GetDefIndices - Return the define indices.
83 std::vector<unsigned> &GetDefIndices() { return DefIndices; }
85 /// GetRegRefs - Return the RegRefs map.
86 std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; }
88 // GetGroup - Get the group for a register. The returned value is
89 // the index of the GroupNode representing the group.
90 unsigned GetGroup(unsigned Reg);
92 // GetGroupRegs - Return a vector of the registers belonging to a
93 // group. If RegRefs is non-NULL then only included referenced registers.
96 std::vector<unsigned> &Regs,
97 std::multimap<unsigned,
98 AggressiveAntiDepState::RegisterReference> *RegRefs);
100 // UnionGroups - Union Reg1's and Reg2's groups to form a new
101 // group. Return the index of the GroupNode representing the
103 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
105 // LeaveGroup - Remove a register from its current group and place
106 // it alone in its own group. Return the index of the GroupNode
107 // representing the registers new group.
108 unsigned LeaveGroup(unsigned Reg);
110 /// IsLive - Return true if Reg is live
111 bool IsLive(unsigned Reg);
115 /// Class AggressiveAntiDepBreaker
116 class AggressiveAntiDepBreaker : public AntiDepBreaker {
118 MachineRegisterInfo &MRI;
119 const TargetInstrInfo *TII;
120 const TargetRegisterInfo *TRI;
122 /// AllocatableSet - The set of allocatable registers.
123 /// We'll be ignoring anti-dependencies on non-allocatable registers,
124 /// because they may not be safe to break.
125 const BitVector AllocatableSet;
127 /// CriticalPathSet - The set of registers that should only be
128 /// renamed if they are on the critical path.
129 BitVector CriticalPathSet;
131 /// State - The state used to identify and rename anti-dependence
133 AggressiveAntiDepState *State;
136 AggressiveAntiDepBreaker(MachineFunction& MFi,
137 TargetSubtarget::RegClassVector& CriticalPathRCs);
138 ~AggressiveAntiDepBreaker();
140 /// Start - Initialize anti-dep breaking for a new basic block.
141 void StartBlock(MachineBasicBlock *BB);
143 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical
145 /// of the ScheduleDAG and break them by renaming registers.
147 unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
148 MachineBasicBlock::iterator Begin,
149 MachineBasicBlock::iterator End,
150 unsigned InsertPosIndex);
152 /// Observe - Update liveness information to account for the current
153 /// instruction, which will not be scheduled.
155 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
157 /// Finish - Finish anti-dep breaking for a basic block.
161 typedef std::map<const TargetRegisterClass *,
162 TargetRegisterClass::const_iterator> RenameOrderType;
164 /// IsImplicitDefUse - Return true if MO represents a register
165 /// that is both implicitly used and defined in MI
166 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
168 /// GetPassthruRegs - If MI implicitly def/uses a register, then
169 /// return that register and all subregisters.
170 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
172 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag,
173 const char *header =NULL, const char *footer =NULL);
175 void PrescanInstruction(MachineInstr *MI, unsigned Count,
176 std::set<unsigned>& PassthruRegs);
177 void ScanInstruction(MachineInstr *MI, unsigned Count);
178 BitVector GetRenameRegisters(unsigned Reg);
179 bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex,
180 RenameOrderType& RenameOrder,
181 std::map<unsigned, unsigned> &RenameMap);