1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
17 #include "llvm/Codegen/TargetSchedule.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/CodeGen.h"
25 class TargetRegisterClass;
26 template <typename T> class SmallVectorImpl;
28 //===----------------------------------------------------------------------===//
30 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
31 /// Target-specific options that control code generation and printing should
32 /// be exposed through a TargetSubtargetInfo-derived class.
34 class TargetSubtargetInfo : public MCSubtargetInfo {
35 TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
36 void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
37 protected: // Can only create subclasses...
38 TargetSubtargetInfo();
40 // AntiDepBreakMode - Type of anti-dependence breaking that should
41 // be performed before post-RA scheduling.
42 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
43 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
45 virtual ~TargetSubtargetInfo();
47 /// Initialize a copy of the scheduling model for this subtarget.
48 /// TargetSchedModel provides the interface for the subtarget's
49 /// instruction scheduling information.
50 void initSchedModel(TargetSchedModel &SchedModel,
51 const TargetInstrInfo *TII) const {
52 // CPUSchedModel is initialized to a static instance by InitMCSubtargetInfo.
53 SchedModel.init(*getSchedModel(), this, TII);
56 /// getSpecialAddressLatency - For targets where it is beneficial to
57 /// backschedule instructions that compute addresses, return a value
58 /// indicating the number of scheduling cycles of backscheduling that
59 /// should be attempted.
60 virtual unsigned getSpecialAddressLatency() const { return 0; }
62 // enablePostRAScheduler - If the target can benefit from post-regalloc
63 // scheduling and the specified optimization level meets the requirement
64 // return true to enable post-register-allocation scheduling. In
65 // CriticalPathRCs return any register classes that should only be broken
66 // if on the critical path.
67 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
68 AntiDepBreakMode& Mode,
69 RegClassVector& CriticalPathRCs) const;
70 // adjustSchedDependency - Perform target specific adjustments to
71 // the latency of a schedule dependency.
72 virtual void adjustSchedDependency(SUnit *def, SUnit *use,
76 } // End llvm namespace