1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 // SDTCVecEltisVT - The specified operand is vector type with element type
73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
77 // SDTCisSameNumEltsAs - The two specified operands have identical number
79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
80 int OtherOperandNum = OtherOp;
83 //===----------------------------------------------------------------------===//
84 // Selection DAG Type Profile definitions.
86 // These use the constraints defined above to describe the type requirements of
87 // the various nodes. These are not hard coded into tblgen, allowing targets to
88 // add their own if needed.
91 // SDTypeProfile - This profile describes the type requirements of a Selection
93 class SDTypeProfile<int numresults, int numoperands,
94 list<SDTypeConstraint> constraints> {
95 int NumResults = numresults;
96 int NumOperands = numoperands;
97 list<SDTypeConstraint> Constraints = constraints;
101 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
102 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
103 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
104 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
105 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
106 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
108 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
109 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
111 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
112 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
114 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
115 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
118 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
121 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
122 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
124 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
127 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
128 SDTCisSameAs<0, 1>, SDTCisInt<0>
130 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
131 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
134 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
136 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
137 SDTCisSameAs<0, 1>, SDTCisFP<0>
139 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
140 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
142 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
143 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
145 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
146 SDTCisFP<0>, SDTCisInt<1>
148 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
149 SDTCisInt<0>, SDTCisFP<1>
151 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
152 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
153 SDTCisVTSmallerThanOp<2, 1>
156 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
157 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
160 def SDTSelect : SDTypeProfile<1, 3, [ // select
161 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
164 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
165 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
168 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
169 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
173 def SDTBr : SDTypeProfile<0, 1, [ // br
177 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
178 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
181 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
182 SDTCisInt<0>, SDTCisVT<1, OtherVT>
185 def SDTBrind : SDTypeProfile<0, 1, [ // brind
189 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret
190 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
193 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
195 def SDTLoad : SDTypeProfile<1, 1, [ // load
199 def SDTStore : SDTypeProfile<0, 2, [ // store
203 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
204 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
207 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
208 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2>
211 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
212 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,
213 SDTCisSameNumEltsAs<0, 2>
216 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
217 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
218 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
221 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
222 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
223 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
226 def SDTVecShuffle : SDTypeProfile<1, 2, [
227 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
229 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
230 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
232 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
233 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
236 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
237 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
239 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
240 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
243 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
244 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
247 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
248 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
251 def SDTAtomicFence : SDTypeProfile<0, 2, [
252 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
254 def SDTAtomic3 : SDTypeProfile<1, 3, [
255 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
257 def SDTAtomic2 : SDTypeProfile<1, 2, [
258 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
260 def SDTAtomicStore : SDTypeProfile<0, 2, [
261 SDTCisPtrTy<0>, SDTCisInt<1>
263 def SDTAtomicLoad : SDTypeProfile<1, 1, [
264 SDTCisInt<0>, SDTCisPtrTy<1>
267 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
268 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
271 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
272 SDTypeProfile<0, 1, constraints>;
273 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
274 SDTypeProfile<0, 2, constraints>;
276 //===----------------------------------------------------------------------===//
277 // Selection DAG Node Properties.
279 // Note: These are hard coded into tblgen.
281 class SDNodeProperty;
282 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
283 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
284 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
285 def SDNPOutGlue : SDNodeProperty; // Write a flag result
286 def SDNPInGlue : SDNodeProperty; // Read a flag operand
287 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
288 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
289 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
290 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
291 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
292 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
293 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
294 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
296 //===----------------------------------------------------------------------===//
297 // Selection DAG Pattern Operations
298 class SDPatternOperator;
300 //===----------------------------------------------------------------------===//
301 // Selection DAG Node definitions.
303 class SDNode<string opcode, SDTypeProfile typeprof,
304 list<SDNodeProperty> props = [], string sdclass = "SDNode">
305 : SDPatternOperator {
306 string Opcode = opcode;
307 string SDClass = sdclass;
308 list<SDNodeProperty> Properties = props;
309 SDTypeProfile TypeProfile = typeprof;
312 // Special TableGen-recognized dag nodes
318 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
319 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
320 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
321 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
322 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
323 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
324 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
325 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
326 "GlobalAddressSDNode">;
327 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
328 "GlobalAddressSDNode">;
329 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
330 "GlobalAddressSDNode">;
331 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
332 "GlobalAddressSDNode">;
333 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
334 "ConstantPoolSDNode">;
335 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
336 "ConstantPoolSDNode">;
337 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
339 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
341 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
343 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
345 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
346 "ExternalSymbolSDNode">;
347 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
348 "ExternalSymbolSDNode">;
349 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
350 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
351 "BlockAddressSDNode">;
352 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
353 "BlockAddressSDNode">;
355 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
356 [SDNPCommutative, SDNPAssociative]>;
357 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
358 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
359 [SDNPCommutative, SDNPAssociative]>;
360 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
361 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
362 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
363 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
364 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
365 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
366 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
367 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
368 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
369 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
370 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
371 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
372 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
373 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
374 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
375 def and : SDNode<"ISD::AND" , SDTIntBinOp,
376 [SDNPCommutative, SDNPAssociative]>;
377 def or : SDNode<"ISD::OR" , SDTIntBinOp,
378 [SDNPCommutative, SDNPAssociative]>;
379 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
380 [SDNPCommutative, SDNPAssociative]>;
381 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
382 [SDNPCommutative, SDNPOutGlue]>;
383 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
384 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
385 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
387 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
388 [SDNPOutGlue, SDNPInGlue]>;
389 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp>;
390 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>;
391 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;
392 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
394 def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
395 def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
396 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
397 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
398 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
399 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
400 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
401 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
402 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
403 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
404 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
405 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
406 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
407 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
408 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
409 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
410 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
411 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
413 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
414 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
415 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
416 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
417 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
418 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
419 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
420 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
421 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
422 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
423 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
424 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
425 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
426 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
427 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
428 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
429 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
430 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
431 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
432 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
433 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
434 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
435 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
436 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
437 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
438 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
440 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
441 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
442 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
444 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
445 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
446 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
447 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
448 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
449 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
451 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
452 def select : SDNode<"ISD::SELECT" , SDTSelect>;
453 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
454 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
456 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
457 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
458 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
459 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
460 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret,
461 [SDNPHasChain, SDNPSideEffect]>;
462 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>;
463 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone,
464 [SDNPHasChain, SDNPSideEffect]>;
466 def trap : SDNode<"ISD::TRAP" , SDTNone,
467 [SDNPHasChain, SDNPSideEffect]>;
468 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
469 [SDNPHasChain, SDNPSideEffect]>;
471 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
472 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
475 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
476 [SDNPHasChain, SDNPSideEffect]>;
478 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
479 [SDNPHasChain, SDNPSideEffect]>;
481 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
482 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
483 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
484 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
485 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
486 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
487 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
488 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
489 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
490 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
491 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
492 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
493 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
494 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
495 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
496 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
497 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
498 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
499 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
500 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
501 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
502 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
503 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
504 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
505 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
506 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
507 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
508 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
510 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
511 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
512 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
513 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
514 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
515 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
516 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
517 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
519 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
520 // and truncst (see below).
521 def ld : SDNode<"ISD::LOAD" , SDTLoad,
522 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
523 def st : SDNode<"ISD::STORE" , SDTStore,
524 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
525 def ist : SDNode<"ISD::STORE" , SDTIStore,
526 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
528 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
529 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
530 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
532 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
533 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
534 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
535 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
536 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
537 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
539 // This operator does not do subvector type checking. The ARM
540 // backend, at least, needs it.
541 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
542 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
545 // This operator does subvector type checking.
546 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
547 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
549 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
550 // these internally. Don't reference these directly.
551 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
552 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
554 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
555 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
557 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
558 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
560 // Do not use cvt directly. Use cvt forms below
561 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
563 def SDT_assertext : SDTypeProfile<1, 1,
564 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
565 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
566 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
569 //===----------------------------------------------------------------------===//
570 // Selection DAG Condition Codes
572 class CondCode; // ISD::CondCode enums
573 def SETOEQ : CondCode; def SETOGT : CondCode;
574 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
575 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
576 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
577 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
579 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
580 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
583 //===----------------------------------------------------------------------===//
584 // Selection DAG Node Transformation Functions.
586 // This mechanism allows targets to manipulate nodes in the output DAG once a
587 // match has been formed. This is typically used to manipulate immediate
590 class SDNodeXForm<SDNode opc, code xformFunction> {
592 code XFormFunction = xformFunction;
595 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
597 //===----------------------------------------------------------------------===//
598 // PatPred Subclasses.
600 // These allow specifying different sorts of predicates that control whether a
605 class CodePatPred<code predicate> : PatPred {
606 code PredicateCode = predicate;
610 //===----------------------------------------------------------------------===//
611 // Selection DAG Pattern Fragments.
613 // Pattern fragments are reusable chunks of dags that match specific things.
614 // They can take arguments and have C++ predicates that control whether they
615 // match. They are intended to make the patterns for common instructions more
616 // compact and readable.
619 /// PatFrag - Represents a pattern fragment. This can match something on the
620 /// DAG, from a single node to multiple nested other fragments.
622 class PatFrag<dag ops, dag frag, code pred = [{}],
623 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
626 code PredicateCode = pred;
627 code ImmediateCode = [{}];
628 SDNodeXForm OperandTransform = xform;
631 // OutPatFrag is a pattern fragment that is used as part of an output pattern
632 // (not an input pattern). These do not have predicates or transforms, but are
633 // used to avoid repeated subexpressions in output patterns.
634 class OutPatFrag<dag ops, dag frag>
635 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
637 // PatLeaf's are pattern fragments that have no operands. This is just a helper
638 // to define immediates and other common things concisely.
639 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
640 : PatFrag<(ops), frag, pred, xform>;
643 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
644 // constraint is a function that is run on the immediate (always with the value
645 // sign extended out to an int64_t) as Imm. For example:
647 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
649 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
650 // is preferred over using PatLeaf because it allows the code generator to
651 // reason more about the constraint.
653 // If FastIsel should ignore all instructions that have an operand of this type,
654 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
655 // the code size of the generated fast instruction selector.
656 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
657 : PatFrag<(ops), (vt imm), [{}], xform> {
658 let ImmediateCode = pred;
659 bit FastIselShouldIgnore = 0;
665 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
666 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
668 def immAllOnesV: PatLeaf<(build_vector), [{
669 return ISD::isBuildVectorAllOnes(N);
671 def immAllZerosV: PatLeaf<(build_vector), [{
672 return ISD::isBuildVectorAllZeros(N);
677 // Other helper fragments.
678 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
679 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
680 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
682 // null_frag - The null pattern operator is used in multiclass instantiations
683 // which accept an SDPatternOperator for use in matching patterns for internal
684 // definitions. When expanding a pattern, if the null fragment is referenced
685 // in the expansion, the pattern is discarded and it is as-if '[]' had been
686 // specified. This allows multiclasses to have the isel patterns be optional.
687 def null_frag : SDPatternOperator;
690 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
691 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
693 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
694 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
697 // extending load fragments.
698 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
699 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
701 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
702 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
704 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
705 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
708 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
709 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
711 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
712 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
714 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
715 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
717 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
718 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
720 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
721 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
723 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
724 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
727 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
728 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
730 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
731 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
733 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
734 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
736 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
737 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
740 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
741 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
743 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
744 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
746 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
747 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
749 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
750 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
753 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
754 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
756 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
757 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
759 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
760 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
762 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
763 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
765 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
766 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
768 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
769 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
772 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
773 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
775 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
776 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
778 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
779 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
781 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
782 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
785 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
786 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
788 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
789 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
791 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
792 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
794 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
795 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
799 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
800 (st node:$val, node:$ptr), [{
801 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
803 def store : PatFrag<(ops node:$val, node:$ptr),
804 (unindexedstore node:$val, node:$ptr), [{
805 return !cast<StoreSDNode>(N)->isTruncatingStore();
808 // truncstore fragments.
809 def truncstore : PatFrag<(ops node:$val, node:$ptr),
810 (unindexedstore node:$val, node:$ptr), [{
811 return cast<StoreSDNode>(N)->isTruncatingStore();
813 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
814 (truncstore node:$val, node:$ptr), [{
815 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
817 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
818 (truncstore node:$val, node:$ptr), [{
819 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
821 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
822 (truncstore node:$val, node:$ptr), [{
823 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
825 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
826 (truncstore node:$val, node:$ptr), [{
827 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
829 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
830 (truncstore node:$val, node:$ptr), [{
831 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
834 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
835 (truncstore node:$val, node:$ptr), [{
836 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
839 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
840 (truncstore node:$val, node:$ptr), [{
841 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
844 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
845 (truncstore node:$val, node:$ptr), [{
846 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
849 // indexed store fragments.
850 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
851 (ist node:$val, node:$base, node:$offset), [{
852 return !cast<StoreSDNode>(N)->isTruncatingStore();
855 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
856 (istore node:$val, node:$base, node:$offset), [{
857 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
858 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
861 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
862 (ist node:$val, node:$base, node:$offset), [{
863 return cast<StoreSDNode>(N)->isTruncatingStore();
865 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
866 (itruncstore node:$val, node:$base, node:$offset), [{
867 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
868 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
870 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
871 (pre_truncst node:$val, node:$base, node:$offset), [{
872 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
874 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
875 (pre_truncst node:$val, node:$base, node:$offset), [{
876 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
878 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
879 (pre_truncst node:$val, node:$base, node:$offset), [{
880 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
882 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
883 (pre_truncst node:$val, node:$base, node:$offset), [{
884 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
886 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
887 (pre_truncst node:$val, node:$base, node:$offset), [{
888 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
891 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
892 (istore node:$val, node:$ptr, node:$offset), [{
893 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
894 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
897 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
898 (itruncstore node:$val, node:$base, node:$offset), [{
899 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
900 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
902 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
903 (post_truncst node:$val, node:$base, node:$offset), [{
904 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
906 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
907 (post_truncst node:$val, node:$base, node:$offset), [{
908 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
910 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
911 (post_truncst node:$val, node:$base, node:$offset), [{
912 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
914 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
915 (post_truncst node:$val, node:$base, node:$offset), [{
916 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
918 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
919 (post_truncst node:$val, node:$base, node:$offset), [{
920 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
923 // nontemporal store fragments.
924 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
925 (store node:$val, node:$ptr), [{
926 return cast<StoreSDNode>(N)->isNonTemporal();
929 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
930 (nontemporalstore node:$val, node:$ptr), [{
931 StoreSDNode *St = cast<StoreSDNode>(N);
932 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
935 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
936 (nontemporalstore node:$val, node:$ptr), [{
937 StoreSDNode *St = cast<StoreSDNode>(N);
938 return St->getAlignment() < St->getMemoryVT().getStoreSize();
941 // setcc convenience fragments.
942 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
943 (setcc node:$lhs, node:$rhs, SETOEQ)>;
944 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
945 (setcc node:$lhs, node:$rhs, SETOGT)>;
946 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
947 (setcc node:$lhs, node:$rhs, SETOGE)>;
948 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
949 (setcc node:$lhs, node:$rhs, SETOLT)>;
950 def setole : PatFrag<(ops node:$lhs, node:$rhs),
951 (setcc node:$lhs, node:$rhs, SETOLE)>;
952 def setone : PatFrag<(ops node:$lhs, node:$rhs),
953 (setcc node:$lhs, node:$rhs, SETONE)>;
954 def seto : PatFrag<(ops node:$lhs, node:$rhs),
955 (setcc node:$lhs, node:$rhs, SETO)>;
956 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
957 (setcc node:$lhs, node:$rhs, SETUO)>;
958 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
959 (setcc node:$lhs, node:$rhs, SETUEQ)>;
960 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
961 (setcc node:$lhs, node:$rhs, SETUGT)>;
962 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
963 (setcc node:$lhs, node:$rhs, SETUGE)>;
964 def setult : PatFrag<(ops node:$lhs, node:$rhs),
965 (setcc node:$lhs, node:$rhs, SETULT)>;
966 def setule : PatFrag<(ops node:$lhs, node:$rhs),
967 (setcc node:$lhs, node:$rhs, SETULE)>;
968 def setune : PatFrag<(ops node:$lhs, node:$rhs),
969 (setcc node:$lhs, node:$rhs, SETUNE)>;
970 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
971 (setcc node:$lhs, node:$rhs, SETEQ)>;
972 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
973 (setcc node:$lhs, node:$rhs, SETGT)>;
974 def setge : PatFrag<(ops node:$lhs, node:$rhs),
975 (setcc node:$lhs, node:$rhs, SETGE)>;
976 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
977 (setcc node:$lhs, node:$rhs, SETLT)>;
978 def setle : PatFrag<(ops node:$lhs, node:$rhs),
979 (setcc node:$lhs, node:$rhs, SETLE)>;
980 def setne : PatFrag<(ops node:$lhs, node:$rhs),
981 (setcc node:$lhs, node:$rhs, SETNE)>;
983 def atomic_cmp_swap_8 :
984 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
985 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
986 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
988 def atomic_cmp_swap_16 :
989 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
990 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
991 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
993 def atomic_cmp_swap_32 :
994 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
995 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
996 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
998 def atomic_cmp_swap_64 :
999 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
1000 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
1001 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1004 multiclass binary_atomic_op<SDNode atomic_op> {
1005 def _8 : PatFrag<(ops node:$ptr, node:$val),
1006 (atomic_op node:$ptr, node:$val), [{
1007 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1009 def _16 : PatFrag<(ops node:$ptr, node:$val),
1010 (atomic_op node:$ptr, node:$val), [{
1011 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1013 def _32 : PatFrag<(ops node:$ptr, node:$val),
1014 (atomic_op node:$ptr, node:$val), [{
1015 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1017 def _64 : PatFrag<(ops node:$ptr, node:$val),
1018 (atomic_op node:$ptr, node:$val), [{
1019 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1023 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
1024 defm atomic_swap : binary_atomic_op<atomic_swap>;
1025 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
1026 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
1027 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
1028 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
1029 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1030 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1031 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1032 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1033 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1034 defm atomic_store : binary_atomic_op<atomic_store>;
1037 PatFrag<(ops node:$ptr),
1038 (atomic_load node:$ptr), [{
1039 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1041 def atomic_load_16 :
1042 PatFrag<(ops node:$ptr),
1043 (atomic_load node:$ptr), [{
1044 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1046 def atomic_load_32 :
1047 PatFrag<(ops node:$ptr),
1048 (atomic_load node:$ptr), [{
1049 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1051 def atomic_load_64 :
1052 PatFrag<(ops node:$ptr),
1053 (atomic_load node:$ptr), [{
1054 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1057 //===----------------------------------------------------------------------===//
1058 // Selection DAG CONVERT_RNDSAT patterns
1060 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1061 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1062 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
1065 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1066 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1067 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
1070 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1071 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1072 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
1075 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1076 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1077 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
1080 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1081 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1082 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
1085 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1086 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1087 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
1090 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1091 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1092 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1095 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1096 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1097 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1100 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1101 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1102 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1105 //===----------------------------------------------------------------------===//
1106 // Selection DAG Pattern Support.
1108 // Patterns are what are actually matched against by the target-flavored
1109 // instruction selection DAG. Instructions defined by the target implicitly
1110 // define patterns in most cases, but patterns can also be explicitly added when
1111 // an operation is defined by a sequence of instructions (e.g. loading a large
1112 // immediate value on RISC targets that do not support immediates as large as
1116 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1117 dag PatternToMatch = patternToMatch;
1118 list<dag> ResultInstrs = resultInstrs;
1119 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1120 int AddedComplexity = 0; // See class Instruction in Target.td.
1123 // Pat - A simple (but common) form of a pattern, which produces a simple result
1124 // not needing a full list.
1125 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1127 //===----------------------------------------------------------------------===//
1128 // Complex pattern definitions.
1131 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1132 // in C++. NumOperands is the number of operands returned by the select function;
1133 // SelectFunc is the name of the function used to pattern match the max. pattern;
1134 // RootNodes are the list of possible root nodes of the sub-dags to match.
1135 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1137 class ComplexPattern<ValueType ty, int numops, string fn,
1138 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1140 int NumOperands = numops;
1141 string SelectFunc = fn;
1142 list<SDNode> RootNodes = roots;
1143 list<SDNodeProperty> Properties = props;