1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
156 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
161 def SDTBr : SDTypeProfile<0, 1, [ // br
165 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
166 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
169 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
170 SDTCisInt<0>, SDTCisVT<1, OtherVT>
173 def SDTBrind : SDTypeProfile<0, 1, [ // brind
177 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
179 def SDTLoad : SDTypeProfile<1, 1, [ // load
183 def SDTStore : SDTypeProfile<0, 2, [ // store
187 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
188 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
191 def SDTVecShuffle : SDTypeProfile<1, 2, [
192 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
194 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
195 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
197 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
198 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
201 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
202 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
204 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
205 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
208 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
209 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
212 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
213 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
216 def SDTAtomicFence : SDTypeProfile<0, 2, [
217 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
219 def SDTAtomic3 : SDTypeProfile<1, 3, [
220 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
222 def SDTAtomic2 : SDTypeProfile<1, 2, [
223 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
225 def SDTAtomicStore : SDTypeProfile<0, 2, [
226 SDTCisPtrTy<0>, SDTCisInt<1>
228 def SDTAtomicLoad : SDTypeProfile<1, 1, [
229 SDTCisInt<0>, SDTCisPtrTy<1>
232 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
233 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
236 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
237 SDTypeProfile<0, 1, constraints>;
238 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
239 SDTypeProfile<0, 2, constraints>;
241 //===----------------------------------------------------------------------===//
242 // Selection DAG Node Properties.
244 // Note: These are hard coded into tblgen.
246 class SDNodeProperty;
247 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
248 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
249 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
250 def SDNPOutGlue : SDNodeProperty; // Write a flag result
251 def SDNPInGlue : SDNodeProperty; // Read a flag operand
252 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
253 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
254 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
255 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
256 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
257 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
258 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
259 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
261 //===----------------------------------------------------------------------===//
262 // Selection DAG Pattern Operations
263 class SDPatternOperator;
265 //===----------------------------------------------------------------------===//
266 // Selection DAG Node definitions.
268 class SDNode<string opcode, SDTypeProfile typeprof,
269 list<SDNodeProperty> props = [], string sdclass = "SDNode">
270 : SDPatternOperator {
271 string Opcode = opcode;
272 string SDClass = sdclass;
273 list<SDNodeProperty> Properties = props;
274 SDTypeProfile TypeProfile = typeprof;
277 // Special TableGen-recognized dag nodes
283 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
284 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
285 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
286 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
287 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
288 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
289 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
290 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
291 "GlobalAddressSDNode">;
292 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
293 "GlobalAddressSDNode">;
294 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
295 "GlobalAddressSDNode">;
296 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
297 "GlobalAddressSDNode">;
298 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
299 "ConstantPoolSDNode">;
300 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
301 "ConstantPoolSDNode">;
302 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
304 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
306 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
308 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
310 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
311 "ExternalSymbolSDNode">;
312 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
313 "ExternalSymbolSDNode">;
314 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
315 "BlockAddressSDNode">;
316 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
317 "BlockAddressSDNode">;
319 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
320 [SDNPCommutative, SDNPAssociative]>;
321 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
322 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
323 [SDNPCommutative, SDNPAssociative]>;
324 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
325 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
326 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
327 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
328 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
329 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
330 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
331 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
332 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
333 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
334 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
335 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
336 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
337 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
338 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
339 def and : SDNode<"ISD::AND" , SDTIntBinOp,
340 [SDNPCommutative, SDNPAssociative]>;
341 def or : SDNode<"ISD::OR" , SDTIntBinOp,
342 [SDNPCommutative, SDNPAssociative]>;
343 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
344 [SDNPCommutative, SDNPAssociative]>;
345 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
346 [SDNPCommutative, SDNPOutGlue]>;
347 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
348 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
349 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
351 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
352 [SDNPOutGlue, SDNPInGlue]>;
354 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
355 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
356 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
357 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
358 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
359 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
360 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
361 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
362 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
363 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
364 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
365 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
366 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
367 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
369 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
370 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
371 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
372 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
373 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
374 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
375 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
376 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
377 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
378 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
379 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
380 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
381 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
382 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
383 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
384 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
385 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
386 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
387 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
388 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
389 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
390 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
391 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
393 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
394 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
395 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
397 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
398 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
399 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
400 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
401 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
402 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
404 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
405 def select : SDNode<"ISD::SELECT" , SDTSelect>;
406 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
407 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
409 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
410 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
411 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
412 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
413 def trap : SDNode<"ISD::TRAP" , SDTNone,
414 [SDNPHasChain, SDNPSideEffect]>;
415 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
416 [SDNPHasChain, SDNPSideEffect]>;
418 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
419 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
422 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
423 [SDNPHasChain, SDNPSideEffect]>;
425 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
426 [SDNPHasChain, SDNPSideEffect]>;
428 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
430 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
432 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
434 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
436 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
438 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
440 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
442 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
444 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
446 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
447 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
448 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
449 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
450 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
451 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
452 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
453 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
454 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
455 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
457 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
458 // and truncst (see below).
459 def ld : SDNode<"ISD::LOAD" , SDTLoad,
460 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
461 def st : SDNode<"ISD::STORE" , SDTStore,
462 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
463 def ist : SDNode<"ISD::STORE" , SDTIStore,
464 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
466 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
467 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
468 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
470 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
471 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
472 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
473 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
474 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
475 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
477 // This operator does not do subvector type checking. The ARM
478 // backend, at least, needs it.
479 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
480 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
483 // This operator does subvector type checking.
484 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
485 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
487 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
488 // these internally. Don't reference these directly.
489 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
490 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
492 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
493 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
495 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
496 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
498 // Do not use cvt directly. Use cvt forms below
499 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
501 def SDT_assertext : SDTypeProfile<1, 1,
502 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
503 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
504 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
507 //===----------------------------------------------------------------------===//
508 // Selection DAG Condition Codes
510 class CondCode; // ISD::CondCode enums
511 def SETOEQ : CondCode; def SETOGT : CondCode;
512 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
513 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
514 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
515 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
517 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
518 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
521 //===----------------------------------------------------------------------===//
522 // Selection DAG Node Transformation Functions.
524 // This mechanism allows targets to manipulate nodes in the output DAG once a
525 // match has been formed. This is typically used to manipulate immediate
528 class SDNodeXForm<SDNode opc, code xformFunction> {
530 code XFormFunction = xformFunction;
533 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
535 //===----------------------------------------------------------------------===//
536 // PatPred Subclasses.
538 // These allow specifying different sorts of predicates that control whether a
543 class CodePatPred<code predicate> : PatPred {
544 code PredicateCode = predicate;
548 //===----------------------------------------------------------------------===//
549 // Selection DAG Pattern Fragments.
551 // Pattern fragments are reusable chunks of dags that match specific things.
552 // They can take arguments and have C++ predicates that control whether they
553 // match. They are intended to make the patterns for common instructions more
554 // compact and readable.
557 /// PatFrag - Represents a pattern fragment. This can match something on the
558 /// DAG, from a single node to multiple nested other fragments.
560 class PatFrag<dag ops, dag frag, code pred = [{}],
561 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
564 code PredicateCode = pred;
565 code ImmediateCode = [{}];
566 SDNodeXForm OperandTransform = xform;
569 // OutPatFrag is a pattern fragment that is used as part of an output pattern
570 // (not an input pattern). These do not have predicates or transforms, but are
571 // used to avoid repeated subexpressions in output patterns.
572 class OutPatFrag<dag ops, dag frag>
573 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
575 // PatLeaf's are pattern fragments that have no operands. This is just a helper
576 // to define immediates and other common things concisely.
577 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
578 : PatFrag<(ops), frag, pred, xform>;
581 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
582 // constraint is a function that is run on the immediate (always with the value
583 // sign extended out to an int64_t) as Imm. For example:
585 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
587 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
588 // is preferred over using PatLeaf because it allows the code generator to
589 // reason more about the constraint.
591 // If FastIsel should ignore all instructions that have an operand of this type,
592 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
593 // the code size of the generated fast instruction selector.
594 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
595 : PatFrag<(ops), (vt imm), [{}], xform> {
596 let ImmediateCode = pred;
597 bit FastIselShouldIgnore = 0;
603 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
604 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
606 def immAllOnesV: PatLeaf<(build_vector), [{
607 return ISD::isBuildVectorAllOnes(N);
609 def immAllZerosV: PatLeaf<(build_vector), [{
610 return ISD::isBuildVectorAllZeros(N);
615 // Other helper fragments.
616 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
617 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
618 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
620 // null_frag - The null pattern operator is used in multiclass instantiations
621 // which accept an SDPatternOperator for use in matching patterns for internal
622 // definitions. When expanding a pattern, if the null fragment is referenced
623 // in the expansion, the pattern is discarded and it is as-if '[]' had been
624 // specified. This allows multiclasses to have the isel patterns be optional.
625 def null_frag : SDPatternOperator;
628 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
629 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
631 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
632 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
635 // extending load fragments.
636 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
637 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
639 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
640 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
642 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
643 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
646 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
647 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
649 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
650 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
652 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
653 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
655 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
656 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
658 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
659 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
661 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
662 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
665 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
666 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
668 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
669 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
671 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
672 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
674 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
675 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
678 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
679 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
681 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
682 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
684 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
685 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
687 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
688 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
691 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
692 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
694 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
695 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
697 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
698 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
700 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
701 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
703 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
704 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
706 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
707 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
710 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
711 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
713 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
714 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
716 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
717 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
719 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
720 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
723 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
724 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
726 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
727 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
729 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
730 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
732 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
733 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
737 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
738 (st node:$val, node:$ptr), [{
739 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
741 def store : PatFrag<(ops node:$val, node:$ptr),
742 (unindexedstore node:$val, node:$ptr), [{
743 return !cast<StoreSDNode>(N)->isTruncatingStore();
746 // truncstore fragments.
747 def truncstore : PatFrag<(ops node:$val, node:$ptr),
748 (unindexedstore node:$val, node:$ptr), [{
749 return cast<StoreSDNode>(N)->isTruncatingStore();
751 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
752 (truncstore node:$val, node:$ptr), [{
753 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
755 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
756 (truncstore node:$val, node:$ptr), [{
757 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
759 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
760 (truncstore node:$val, node:$ptr), [{
761 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
763 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
764 (truncstore node:$val, node:$ptr), [{
765 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
767 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
768 (truncstore node:$val, node:$ptr), [{
769 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
772 // indexed store fragments.
773 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
774 (ist node:$val, node:$base, node:$offset), [{
775 return !cast<StoreSDNode>(N)->isTruncatingStore();
778 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
779 (istore node:$val, node:$base, node:$offset), [{
780 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
781 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
784 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
785 (ist node:$val, node:$base, node:$offset), [{
786 return cast<StoreSDNode>(N)->isTruncatingStore();
788 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
789 (itruncstore node:$val, node:$base, node:$offset), [{
790 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
791 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
793 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
794 (pre_truncst node:$val, node:$base, node:$offset), [{
795 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
797 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
798 (pre_truncst node:$val, node:$base, node:$offset), [{
799 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
801 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
802 (pre_truncst node:$val, node:$base, node:$offset), [{
803 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
805 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
806 (pre_truncst node:$val, node:$base, node:$offset), [{
807 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
809 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
810 (pre_truncst node:$val, node:$base, node:$offset), [{
811 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
814 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
815 (istore node:$val, node:$ptr, node:$offset), [{
816 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
817 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
820 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
821 (itruncstore node:$val, node:$base, node:$offset), [{
822 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
823 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
825 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
826 (post_truncst node:$val, node:$base, node:$offset), [{
827 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
829 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
830 (post_truncst node:$val, node:$base, node:$offset), [{
831 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
833 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
834 (post_truncst node:$val, node:$base, node:$offset), [{
835 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
837 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
838 (post_truncst node:$val, node:$base, node:$offset), [{
839 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
841 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
842 (post_truncst node:$val, node:$base, node:$offset), [{
843 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
846 // setcc convenience fragments.
847 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
848 (setcc node:$lhs, node:$rhs, SETOEQ)>;
849 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
850 (setcc node:$lhs, node:$rhs, SETOGT)>;
851 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
852 (setcc node:$lhs, node:$rhs, SETOGE)>;
853 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
854 (setcc node:$lhs, node:$rhs, SETOLT)>;
855 def setole : PatFrag<(ops node:$lhs, node:$rhs),
856 (setcc node:$lhs, node:$rhs, SETOLE)>;
857 def setone : PatFrag<(ops node:$lhs, node:$rhs),
858 (setcc node:$lhs, node:$rhs, SETONE)>;
859 def seto : PatFrag<(ops node:$lhs, node:$rhs),
860 (setcc node:$lhs, node:$rhs, SETO)>;
861 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
862 (setcc node:$lhs, node:$rhs, SETUO)>;
863 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
864 (setcc node:$lhs, node:$rhs, SETUEQ)>;
865 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
866 (setcc node:$lhs, node:$rhs, SETUGT)>;
867 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
868 (setcc node:$lhs, node:$rhs, SETUGE)>;
869 def setult : PatFrag<(ops node:$lhs, node:$rhs),
870 (setcc node:$lhs, node:$rhs, SETULT)>;
871 def setule : PatFrag<(ops node:$lhs, node:$rhs),
872 (setcc node:$lhs, node:$rhs, SETULE)>;
873 def setune : PatFrag<(ops node:$lhs, node:$rhs),
874 (setcc node:$lhs, node:$rhs, SETUNE)>;
875 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
876 (setcc node:$lhs, node:$rhs, SETEQ)>;
877 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
878 (setcc node:$lhs, node:$rhs, SETGT)>;
879 def setge : PatFrag<(ops node:$lhs, node:$rhs),
880 (setcc node:$lhs, node:$rhs, SETGE)>;
881 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
882 (setcc node:$lhs, node:$rhs, SETLT)>;
883 def setle : PatFrag<(ops node:$lhs, node:$rhs),
884 (setcc node:$lhs, node:$rhs, SETLE)>;
885 def setne : PatFrag<(ops node:$lhs, node:$rhs),
886 (setcc node:$lhs, node:$rhs, SETNE)>;
888 def atomic_cmp_swap_8 :
889 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
890 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
891 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
893 def atomic_cmp_swap_16 :
894 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
895 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
896 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
898 def atomic_cmp_swap_32 :
899 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
900 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
901 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
903 def atomic_cmp_swap_64 :
904 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
905 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
906 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
909 multiclass binary_atomic_op<SDNode atomic_op> {
910 def _8 : PatFrag<(ops node:$ptr, node:$val),
911 (atomic_op node:$ptr, node:$val), [{
912 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
914 def _16 : PatFrag<(ops node:$ptr, node:$val),
915 (atomic_op node:$ptr, node:$val), [{
916 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
918 def _32 : PatFrag<(ops node:$ptr, node:$val),
919 (atomic_op node:$ptr, node:$val), [{
920 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
922 def _64 : PatFrag<(ops node:$ptr, node:$val),
923 (atomic_op node:$ptr, node:$val), [{
924 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
928 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
929 defm atomic_swap : binary_atomic_op<atomic_swap>;
930 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
931 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
932 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
933 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
934 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
935 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
936 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
937 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
938 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
939 defm atomic_store : binary_atomic_op<atomic_store>;
942 PatFrag<(ops node:$ptr),
943 (atomic_load node:$ptr), [{
944 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
947 PatFrag<(ops node:$ptr),
948 (atomic_load node:$ptr), [{
949 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
952 PatFrag<(ops node:$ptr),
953 (atomic_load node:$ptr), [{
954 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
957 PatFrag<(ops node:$ptr),
958 (atomic_load node:$ptr), [{
959 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
962 //===----------------------------------------------------------------------===//
963 // Selection DAG CONVERT_RNDSAT patterns
965 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
966 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
967 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
970 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
971 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
972 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
975 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
976 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
977 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
980 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
981 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
982 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
985 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
986 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
987 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
990 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
991 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
992 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
995 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
996 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
997 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1000 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1001 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1002 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1005 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1006 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1007 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1010 //===----------------------------------------------------------------------===//
1011 // Selection DAG Pattern Support.
1013 // Patterns are what are actually matched against by the target-flavored
1014 // instruction selection DAG. Instructions defined by the target implicitly
1015 // define patterns in most cases, but patterns can also be explicitly added when
1016 // an operation is defined by a sequence of instructions (e.g. loading a large
1017 // immediate value on RISC targets that do not support immediates as large as
1021 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1022 dag PatternToMatch = patternToMatch;
1023 list<dag> ResultInstrs = resultInstrs;
1024 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1025 int AddedComplexity = 0; // See class Instruction in Target.td.
1028 // Pat - A simple (but common) form of a pattern, which produces a simple result
1029 // not needing a full list.
1030 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1032 //===----------------------------------------------------------------------===//
1033 // Complex pattern definitions.
1036 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1037 // in C++. NumOperands is the number of operands returned by the select function;
1038 // SelectFunc is the name of the function used to pattern match the max. pattern;
1039 // RootNodes are the list of possible root nodes of the sub-dags to match.
1040 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1042 class ComplexPattern<ValueType ty, int numops, string fn,
1043 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1045 int NumOperands = numops;
1046 string SelectFunc = fn;
1047 list<SDNode> RootNodes = roots;
1048 list<SDNodeProperty> Properties = props;