1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
29 class MachineMemOperand;
31 template<class T> class SmallVectorImpl;
34 //---------------------------------------------------------------------------
36 /// TargetInstrInfo - Interface to description of machine instruction set
38 class TargetInstrInfo {
39 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
40 unsigned NumOpcodes; // Number of entries in the desc array
42 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
43 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
45 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
46 virtual ~TargetInstrInfo();
48 // Invariant opcodes: All instruction sets have these as their low opcodes.
56 /// KILL - This instruction is a noop that is used only to adjust the liveness
57 /// of registers. This can be useful when dealing with sub-registers.
60 /// EXTRACT_SUBREG - This instruction takes two operands: a register
61 /// that has subregisters, and a subregister index. It returns the
62 /// extracted subregister value. This is commonly used to implement
63 /// truncation operations on target architectures which support it.
66 /// INSERT_SUBREG - This instruction takes three operands: a register
67 /// that has subregisters, a register providing an insert value, and a
68 /// subregister index. It returns the value of the first register with
69 /// the value of the second register inserted. The first register is
70 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
71 /// anyext operations on target architectures which support it.
74 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
77 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
78 /// that the first operand is an immediate integer constant. This constant
79 /// is often zero, as is commonly used to implement zext operations on
80 /// target architectures which support it, such as with x86-64 (with
81 /// zext from i32 to i64 via implicit zero-extension).
84 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
85 /// register-to-register copy into a specific register class. This is only
86 /// used between instruction selection and MachineInstr creation, before
87 /// virtual registers have been created for all the instructions, and it's
88 /// only needed in cases where the register classes implied by the
89 /// instructions are insufficient. The actual MachineInstrs to perform
90 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
94 unsigned getNumOpcodes() const { return NumOpcodes; }
96 /// get - Return the machine instruction descriptor that corresponds to the
97 /// specified instruction opcode.
99 const TargetInstrDesc &get(unsigned Opcode) const {
100 assert(Opcode < NumOpcodes && "Invalid opcode!");
101 return Descriptors[Opcode];
104 /// isTriviallyReMaterializable - Return true if the instruction is trivially
105 /// rematerializable, meaning it has no side effects and requires no operands
106 /// that aren't always available.
107 bool isTriviallyReMaterializable(const MachineInstr *MI,
108 AliasAnalysis *AA = 0) const {
109 return MI->getOpcode() == IMPLICIT_DEF ||
110 (MI->getDesc().isRematerializable() &&
111 (isReallyTriviallyReMaterializable(MI, AA) ||
112 isReallyTriviallyReMaterializableGeneric(MI, AA)));
116 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
117 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
118 /// specify whether the instruction is actually trivially rematerializable,
119 /// taking into consideration its operands. This predicate must return false
120 /// if the instruction has any side effects other than producing a value, or
121 /// if it requres any address registers that are not always available.
122 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
123 AliasAnalysis *AA) const {
128 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
129 /// for which the M_REMATERIALIZABLE flag is set and the target hook
130 /// isReallyTriviallyReMaterializable returns false, this function does
131 /// target-independent tests to determine if the instruction is really
132 /// trivially rematerializable.
133 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
134 AliasAnalysis *AA) const;
137 /// isMoveInstr - Return true if the instruction is a register to register
138 /// move and return the source and dest operands and their sub-register
139 /// indices by reference.
140 virtual bool isMoveInstr(const MachineInstr& MI,
141 unsigned& SrcReg, unsigned& DstReg,
142 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
146 /// isIdentityCopy - Return true if the instruction is a copy (or
147 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
148 /// destination registers are the same.
149 bool isIdentityCopy(const MachineInstr &MI) const {
150 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
151 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
155 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
156 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
159 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
160 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
161 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
166 /// isLoadFromStackSlot - If the specified machine instruction is a direct
167 /// load from a stack slot, return the virtual or physical register number of
168 /// the destination along with the FrameIndex of the loaded stack slot. If
169 /// not, return 0. This predicate must return 0 if the instruction has
170 /// any side effects other than loading from the stack slot.
171 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
172 int &FrameIndex) const {
176 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
177 /// stack locations as well. This uses a heuristic so it isn't
178 /// reliable for correctness.
179 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
180 int &FrameIndex) const {
184 /// hasLoadFromStackSlot - If the specified machine instruction has
185 /// a load from a stack slot, return true along with the FrameIndex
186 /// of the loaded stack slot and the machine mem operand containing
187 /// the reference. If not, return false. Unlike
188 /// isLoadFromStackSlot, this returns true for any instructions that
189 /// loads from the stack. This is just a hint, as some cases may be
191 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
192 const MachineMemOperand *&MMO,
193 int &FrameIndex) const {
197 /// isStoreToStackSlot - If the specified machine instruction is a direct
198 /// store to a stack slot, return the virtual or physical register number of
199 /// the source reg along with the FrameIndex of the loaded stack slot. If
200 /// not, return 0. This predicate must return 0 if the instruction has
201 /// any side effects other than storing to the stack slot.
202 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
203 int &FrameIndex) const {
207 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
208 /// stack locations as well. This uses a heuristic so it isn't
209 /// reliable for correctness.
210 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
211 int &FrameIndex) const {
215 /// hasStoreToStackSlot - If the specified machine instruction has a
216 /// store to a stack slot, return true along with the FrameIndex of
217 /// the loaded stack slot and the machine mem operand containing the
218 /// reference. If not, return false. Unlike isStoreToStackSlot,
219 /// this returns true for any instructions that loads from the
220 /// stack. This is just a hint, as some cases may be missed.
221 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
222 const MachineMemOperand *&MMO,
223 int &FrameIndex) const {
227 /// reMaterialize - Re-issue the specified 'original' instruction at the
228 /// specific location targeting a new destination register.
229 virtual void reMaterialize(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator MI,
231 unsigned DestReg, unsigned SubIdx,
232 const MachineInstr *Orig,
233 const TargetRegisterInfo *TRI) const = 0;
235 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
236 /// MachineFunction::CloneMachineInstr(), but the target may update operands
237 /// that are required to be unique.
238 virtual MachineInstr *duplicate(MachineInstr *Orig,
239 MachineFunction &MF) const = 0;
241 /// convertToThreeAddress - This method must be implemented by targets that
242 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
243 /// may be able to convert a two-address instruction into one or more true
244 /// three-address instructions on demand. This allows the X86 target (for
245 /// example) to convert ADD and SHL instructions into LEA instructions if they
246 /// would require register copies due to two-addressness.
248 /// This method returns a null pointer if the transformation cannot be
249 /// performed, otherwise it returns the last new instruction.
251 virtual MachineInstr *
252 convertToThreeAddress(MachineFunction::iterator &MFI,
253 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
257 /// commuteInstruction - If a target has any instructions that are commutable,
258 /// but require converting to a different instruction or making non-trivial
259 /// changes to commute them, this method can overloaded to do this. The
260 /// default implementation of this method simply swaps the first two operands
261 /// of MI and returns it.
263 /// If a target wants to make more aggressive changes, they can construct and
264 /// return a new machine instruction. If an instruction cannot commute, it
265 /// can also return null.
267 /// If NewMI is true, then a new machine instruction must be created.
269 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
270 bool NewMI = false) const = 0;
272 /// findCommutedOpIndices - If specified MI is commutable, return the two
273 /// operand indices that would swap value. Return true if the instruction
274 /// is not in a form which this routine understands.
275 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
276 unsigned &SrcOpIdx2) const = 0;
278 /// isIdentical - Return true if two instructions are identical. This differs
279 /// from MachineInstr::isIdenticalTo() in that it does not require the
280 /// virtual destination registers to be the same. This is used by MachineLICM
281 /// and other MI passes to perform CSE.
282 virtual bool isIdentical(const MachineInstr *MI,
283 const MachineInstr *Other,
284 const MachineRegisterInfo *MRI) const = 0;
286 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
287 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
288 /// implemented for a target). Upon success, this returns false and returns
289 /// with the following information in various cases:
291 /// 1. If this block ends with no branches (it just falls through to its succ)
292 /// just return false, leaving TBB/FBB null.
293 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
294 /// the destination block.
295 /// 3. If this block ends with a conditional branch and it falls through to a
296 /// successor block, it sets TBB to be the branch destination block and a
297 /// list of operands that evaluate the condition. These operands can be
298 /// passed to other TargetInstrInfo methods to create new branches.
299 /// 4. If this block ends with a conditional branch followed by an
300 /// unconditional branch, it returns the 'true' destination in TBB, the
301 /// 'false' destination in FBB, and a list of operands that evaluate the
302 /// condition. These operands can be passed to other TargetInstrInfo
303 /// methods to create new branches.
305 /// Note that RemoveBranch and InsertBranch must be implemented to support
306 /// cases where this method returns success.
308 /// If AllowModify is true, then this routine is allowed to modify the basic
309 /// block (e.g. delete instructions after the unconditional branch).
311 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
312 MachineBasicBlock *&FBB,
313 SmallVectorImpl<MachineOperand> &Cond,
314 bool AllowModify = false) const {
318 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
319 /// This is only invoked in cases where AnalyzeBranch returns success. It
320 /// returns the number of instructions that were removed.
321 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
322 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
326 /// InsertBranch - Insert branch code into the end of the specified
327 /// MachineBasicBlock. The operands to this method are the same as those
328 /// returned by AnalyzeBranch. This is only invoked in cases where
329 /// AnalyzeBranch returns success. It returns the number of instructions
332 /// It is also invoked by tail merging to add unconditional branches in
333 /// cases where AnalyzeBranch doesn't apply because there was no original
334 /// branch to analyze. At least this much must be implemented, else tail
335 /// merging needs to be disabled.
336 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
337 MachineBasicBlock *FBB,
338 const SmallVectorImpl<MachineOperand> &Cond) const {
339 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
343 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
344 /// returns false if the target does not how to copy between the specified
346 virtual bool copyRegToReg(MachineBasicBlock &MBB,
347 MachineBasicBlock::iterator MI,
348 unsigned DestReg, unsigned SrcReg,
349 const TargetRegisterClass *DestRC,
350 const TargetRegisterClass *SrcRC) const {
351 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
355 /// storeRegToStackSlot - Store the specified register of the given register
356 /// class to the specified stack frame index. The store instruction is to be
357 /// added to the given machine basic block before the specified machine
358 /// instruction. If isKill is true, the register operand is the last use and
359 /// must be marked kill.
360 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
361 MachineBasicBlock::iterator MI,
362 unsigned SrcReg, bool isKill, int FrameIndex,
363 const TargetRegisterClass *RC) const {
364 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
367 /// loadRegFromStackSlot - Load the specified register of the given register
368 /// class from the specified stack frame index. The load instruction is to be
369 /// added to the given machine basic block before the specified machine
371 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
372 MachineBasicBlock::iterator MI,
373 unsigned DestReg, int FrameIndex,
374 const TargetRegisterClass *RC) const {
375 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
378 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
379 /// saved registers and returns true if it isn't possible / profitable to do
380 /// so by issuing a series of store instructions via
381 /// storeRegToStackSlot(). Returns false otherwise.
382 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MI,
384 const std::vector<CalleeSavedInfo> &CSI) const {
388 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
389 /// saved registers and returns true if it isn't possible / profitable to do
390 /// so by issuing a series of load instructions via loadRegToStackSlot().
391 /// Returns false otherwise.
392 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MI,
394 const std::vector<CalleeSavedInfo> &CSI) const {
398 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
399 /// slot into the specified machine instruction for the specified operand(s).
400 /// If this is possible, a new instruction is returned with the specified
401 /// operand folded, otherwise NULL is returned. The client is responsible for
402 /// removing the old instruction and adding the new one in the instruction
404 MachineInstr* foldMemoryOperand(MachineFunction &MF,
406 const SmallVectorImpl<unsigned> &Ops,
407 int FrameIndex) const;
409 /// foldMemoryOperand - Same as the previous version except it allows folding
410 /// of any load and store from / to any address, not just from a specific
412 MachineInstr* foldMemoryOperand(MachineFunction &MF,
414 const SmallVectorImpl<unsigned> &Ops,
415 MachineInstr* LoadMI) const;
418 /// foldMemoryOperandImpl - Target-dependent implementation for
419 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
420 /// take care of adding a MachineMemOperand to the newly created instruction.
421 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
423 const SmallVectorImpl<unsigned> &Ops,
424 int FrameIndex) const {
428 /// foldMemoryOperandImpl - Target-dependent implementation for
429 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
430 /// take care of adding a MachineMemOperand to the newly created instruction.
431 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
433 const SmallVectorImpl<unsigned> &Ops,
434 MachineInstr* LoadMI) const {
439 /// canFoldMemoryOperand - Returns true for the specified load / store if
440 /// folding is possible.
442 bool canFoldMemoryOperand(const MachineInstr *MI,
443 const SmallVectorImpl<unsigned> &Ops) const {
447 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
448 /// a store or a load and a store into two or more instruction. If this is
449 /// possible, returns true as well as the new instructions by reference.
450 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
451 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
452 SmallVectorImpl<MachineInstr*> &NewMIs) const{
456 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
457 SmallVectorImpl<SDNode*> &NewNodes) const {
461 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
462 /// instruction after load / store are unfolded from an instruction of the
463 /// specified opcode. It returns zero if the specified unfolding is not
464 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
465 /// index of the operand which will hold the register holding the loaded
467 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
468 bool UnfoldLoad, bool UnfoldStore,
469 unsigned *LoadRegIndex = 0) const {
473 /// ReverseBranchCondition - Reverses the branch condition of the specified
474 /// condition list, returning false on success and true if it cannot be
477 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
481 /// insertNoop - Insert a noop into the instruction stream at the specified
483 virtual void insertNoop(MachineBasicBlock &MBB,
484 MachineBasicBlock::iterator MI) const;
486 /// isPredicated - Returns true if the instruction is already predicated.
488 virtual bool isPredicated(const MachineInstr *MI) const {
492 /// isUnpredicatedTerminator - Returns true if the instruction is a
493 /// terminator instruction that has not been predicated.
494 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
496 /// PredicateInstruction - Convert the instruction into a predicated
497 /// instruction. It returns true if the operation was successful.
499 bool PredicateInstruction(MachineInstr *MI,
500 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
502 /// SubsumesPredicate - Returns true if the first specified predicate
503 /// subsumes the second, e.g. GE subsumes GT.
505 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
506 const SmallVectorImpl<MachineOperand> &Pred2) const {
510 /// DefinesPredicate - If the specified instruction defines any predicate
511 /// or condition code register(s) used for predication, returns true as well
512 /// as the definition predicate(s) by reference.
513 virtual bool DefinesPredicate(MachineInstr *MI,
514 std::vector<MachineOperand> &Pred) const {
518 /// isPredicable - Return true if the specified instruction can be predicated.
519 /// By default, this returns true for every instruction with a
520 /// PredicateOperand.
521 virtual bool isPredicable(MachineInstr *MI) const {
522 return MI->getDesc().isPredicable();
525 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
526 /// instruction that defines the specified register class.
527 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
531 /// GetInstSize - Returns the size of the specified Instruction.
533 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
534 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
538 /// GetFunctionSizeInBytes - Returns the size of the specified
541 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
543 /// Measure the specified inline asm to determine an approximation of its
545 virtual unsigned getInlineAsmLength(const char *Str,
546 const MCAsmInfo &MAI) const;
549 /// TargetInstrInfoImpl - This is the default implementation of
550 /// TargetInstrInfo, which just provides a couple of default implementations
551 /// for various methods. This separated out because it is implemented in
552 /// libcodegen, not in libtarget.
553 class TargetInstrInfoImpl : public TargetInstrInfo {
555 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
556 : TargetInstrInfo(desc, NumOpcodes) {}
558 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
559 bool NewMI = false) const;
560 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
561 unsigned &SrcOpIdx2) const;
562 virtual bool PredicateInstruction(MachineInstr *MI,
563 const SmallVectorImpl<MachineOperand> &Pred) const;
564 virtual void reMaterialize(MachineBasicBlock &MBB,
565 MachineBasicBlock::iterator MI,
566 unsigned DestReg, unsigned SubReg,
567 const MachineInstr *Orig,
568 const TargetRegisterInfo *TRI) const;
569 virtual MachineInstr *duplicate(MachineInstr *Orig,
570 MachineFunction &MF) const;
571 virtual bool isIdentical(const MachineInstr *MI,
572 const MachineInstr *Other,
573 const MachineRegisterInfo *MRI) const;
575 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
578 } // End llvm namespace