1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the target machine instruction set to the code generator.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
15 #define LLVM_TARGET_TARGETINSTRINFO_H
17 #include "llvm/Target/TargetInstrDesc.h"
18 #include "llvm/CodeGen/MachineFunction.h"
23 class TargetRegisterClass;
24 class TargetRegisterInfo;
26 class CalleeSavedInfo;
30 template<class T> class SmallVectorImpl;
33 //---------------------------------------------------------------------------
35 /// TargetInstrInfo - Interface to description of machine instruction set
37 class TargetInstrInfo {
38 const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
39 unsigned NumOpcodes; // Number of entries in the desc array
41 TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
42 void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
44 TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
45 virtual ~TargetInstrInfo();
47 // Invariant opcodes: All instruction sets have these as their low opcodes.
55 /// KILL - This instruction is a noop that is used only to adjust the liveness
56 /// of registers. This can be useful when dealing with sub-registers.
59 /// EXTRACT_SUBREG - This instruction takes two operands: a register
60 /// that has subregisters, and a subregister index. It returns the
61 /// extracted subregister value. This is commonly used to implement
62 /// truncation operations on target architectures which support it.
65 /// INSERT_SUBREG - This instruction takes three operands: a register
66 /// that has subregisters, a register providing an insert value, and a
67 /// subregister index. It returns the value of the first register with
68 /// the value of the second register inserted. The first register is
69 /// often defined by an IMPLICIT_DEF, as is commonly used to implement
70 /// anyext operations on target architectures which support it.
73 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
76 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except
77 /// that the first operand is an immediate integer constant. This constant
78 /// is often zero, as is commonly used to implement zext operations on
79 /// target architectures which support it, such as with x86-64 (with
80 /// zext from i32 to i64 via implicit zero-extension).
83 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
84 /// register-to-register copy into a specific register class. This is only
85 /// used between instruction selection and MachineInstr creation, before
86 /// virtual registers have been created for all the instructions, and it's
87 /// only needed in cases where the register classes implied by the
88 /// instructions are insufficient. The actual MachineInstrs to perform
89 /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
93 unsigned getNumOpcodes() const { return NumOpcodes; }
95 /// get - Return the machine instruction descriptor that corresponds to the
96 /// specified instruction opcode.
98 const TargetInstrDesc &get(unsigned Opcode) const {
99 assert(Opcode < NumOpcodes && "Invalid opcode!");
100 return Descriptors[Opcode];
103 /// isTriviallyReMaterializable - Return true if the instruction is trivially
104 /// rematerializable, meaning it has no side effects and requires no operands
105 /// that aren't always available.
106 bool isTriviallyReMaterializable(const MachineInstr *MI,
107 AliasAnalysis *AA = 0) const {
108 return MI->getOpcode() == IMPLICIT_DEF ||
109 (MI->getDesc().isRematerializable() &&
110 (isReallyTriviallyReMaterializable(MI, AA) ||
111 isReallyTriviallyReMaterializableGeneric(MI, AA)));
115 /// isReallyTriviallyReMaterializable - For instructions with opcodes for
116 /// which the M_REMATERIALIZABLE flag is set, this hook lets the target
117 /// specify whether the instruction is actually trivially rematerializable,
118 /// taking into consideration its operands. This predicate must return false
119 /// if the instruction has any side effects other than producing a value, or
120 /// if it requres any address registers that are not always available.
121 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
122 AliasAnalysis *AA) const {
127 /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes
128 /// for which the M_REMATERIALIZABLE flag is set and the target hook
129 /// isReallyTriviallyReMaterializable returns false, this function does
130 /// target-independent tests to determine if the instruction is really
131 /// trivially rematerializable.
132 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
133 AliasAnalysis *AA) const;
136 /// isMoveInstr - Return true if the instruction is a register to register
137 /// move and return the source and dest operands and their sub-register
138 /// indices by reference.
139 virtual bool isMoveInstr(const MachineInstr& MI,
140 unsigned& SrcReg, unsigned& DstReg,
141 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
145 /// isIdentityCopy - Return true if the instruction is a copy (or
146 /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
147 /// destination registers are the same.
148 bool isIdentityCopy(const MachineInstr &MI) const {
149 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
150 if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
154 if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
155 MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
158 if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
159 MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
160 MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
165 /// isLoadFromStackSlot - If the specified machine instruction is a direct
166 /// load from a stack slot, return the virtual or physical register number of
167 /// the destination along with the FrameIndex of the loaded stack slot. If
168 /// not, return 0. This predicate must return 0 if the instruction has
169 /// any side effects other than loading from the stack slot.
170 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
171 int &FrameIndex) const {
175 /// isStoreToStackSlot - If the specified machine instruction is a direct
176 /// store to a stack slot, return the virtual or physical register number of
177 /// the source reg along with the FrameIndex of the loaded stack slot. If
178 /// not, return 0. This predicate must return 0 if the instruction has
179 /// any side effects other than storing to the stack slot.
180 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
181 int &FrameIndex) const {
185 /// reMaterialize - Re-issue the specified 'original' instruction at the
186 /// specific location targeting a new destination register.
187 virtual void reMaterialize(MachineBasicBlock &MBB,
188 MachineBasicBlock::iterator MI,
189 unsigned DestReg, unsigned SubIdx,
190 const MachineInstr *Orig) const = 0;
192 /// convertToThreeAddress - This method must be implemented by targets that
193 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
194 /// may be able to convert a two-address instruction into one or more true
195 /// three-address instructions on demand. This allows the X86 target (for
196 /// example) to convert ADD and SHL instructions into LEA instructions if they
197 /// would require register copies due to two-addressness.
199 /// This method returns a null pointer if the transformation cannot be
200 /// performed, otherwise it returns the last new instruction.
202 virtual MachineInstr *
203 convertToThreeAddress(MachineFunction::iterator &MFI,
204 MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const {
208 /// commuteInstruction - If a target has any instructions that are commutable,
209 /// but require converting to a different instruction or making non-trivial
210 /// changes to commute them, this method can overloaded to do this. The
211 /// default implementation of this method simply swaps the first two operands
212 /// of MI and returns it.
214 /// If a target wants to make more aggressive changes, they can construct and
215 /// return a new machine instruction. If an instruction cannot commute, it
216 /// can also return null.
218 /// If NewMI is true, then a new machine instruction must be created.
220 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
221 bool NewMI = false) const = 0;
223 /// findCommutedOpIndices - If specified MI is commutable, return the two
224 /// operand indices that would swap value. Return true if the instruction
225 /// is not in a form which this routine understands.
226 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
227 unsigned &SrcOpIdx2) const = 0;
229 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
230 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
231 /// implemented for a target). Upon success, this returns false and returns
232 /// with the following information in various cases:
234 /// 1. If this block ends with no branches (it just falls through to its succ)
235 /// just return false, leaving TBB/FBB null.
236 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
237 /// the destination block.
238 /// 3. If this block ends with an conditional branch and it falls through to
239 /// a successor block, it sets TBB to be the branch destination block and
240 /// a list of operands that evaluate the condition. These
241 /// operands can be passed to other TargetInstrInfo methods to create new
243 /// 4. If this block ends with a conditional branch followed by an
244 /// unconditional branch, it returns the 'true' destination in TBB, the
245 /// 'false' destination in FBB, and a list of operands that evaluate the
246 /// condition. These operands can be passed to other TargetInstrInfo
247 /// methods to create new branches.
249 /// Note that RemoveBranch and InsertBranch must be implemented to support
250 /// cases where this method returns success.
252 /// If AllowModify is true, then this routine is allowed to modify the basic
253 /// block (e.g. delete instructions after the unconditional branch).
255 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
256 MachineBasicBlock *&FBB,
257 SmallVectorImpl<MachineOperand> &Cond,
258 bool AllowModify = false) const {
262 /// RemoveBranch - Remove the branching code at the end of the specific MBB.
263 /// This is only invoked in cases where AnalyzeBranch returns success. It
264 /// returns the number of instructions that were removed.
265 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
266 assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
270 /// InsertBranch - Insert branch code into the end of the specified
271 /// MachineBasicBlock. The operands to this method are the same as those
272 /// returned by AnalyzeBranch. This is only invoked in cases where
273 /// AnalyzeBranch returns success. It returns the number of instructions
276 /// It is also invoked by tail merging to add unconditional branches in
277 /// cases where AnalyzeBranch doesn't apply because there was no original
278 /// branch to analyze. At least this much must be implemented, else tail
279 /// merging needs to be disabled.
280 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
281 MachineBasicBlock *FBB,
282 const SmallVectorImpl<MachineOperand> &Cond) const {
283 assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
287 /// copyRegToReg - Emit instructions to copy between a pair of registers. It
288 /// returns false if the target does not how to copy between the specified
290 virtual bool copyRegToReg(MachineBasicBlock &MBB,
291 MachineBasicBlock::iterator MI,
292 unsigned DestReg, unsigned SrcReg,
293 const TargetRegisterClass *DestRC,
294 const TargetRegisterClass *SrcRC) const {
295 assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
299 /// storeRegToStackSlot - Store the specified register of the given register
300 /// class to the specified stack frame index. The store instruction is to be
301 /// added to the given machine basic block before the specified machine
302 /// instruction. If isKill is true, the register operand is the last use and
303 /// must be marked kill.
304 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
305 MachineBasicBlock::iterator MI,
306 unsigned SrcReg, bool isKill, int FrameIndex,
307 const TargetRegisterClass *RC) const {
308 assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
311 /// loadRegFromStackSlot - Load the specified register of the given register
312 /// class from the specified stack frame index. The load instruction is to be
313 /// added to the given machine basic block before the specified machine
315 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
316 MachineBasicBlock::iterator MI,
317 unsigned DestReg, int FrameIndex,
318 const TargetRegisterClass *RC) const {
319 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
322 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
323 /// saved registers and returns true if it isn't possible / profitable to do
324 /// so by issuing a series of store instructions via
325 /// storeRegToStackSlot(). Returns false otherwise.
326 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator MI,
328 const std::vector<CalleeSavedInfo> &CSI) const {
332 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
333 /// saved registers and returns true if it isn't possible / profitable to do
334 /// so by issuing a series of load instructions via loadRegToStackSlot().
335 /// Returns false otherwise.
336 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
337 MachineBasicBlock::iterator MI,
338 const std::vector<CalleeSavedInfo> &CSI) const {
342 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
343 /// slot into the specified machine instruction for the specified operand(s).
344 /// If this is possible, a new instruction is returned with the specified
345 /// operand folded, otherwise NULL is returned. The client is responsible for
346 /// removing the old instruction and adding the new one in the instruction
348 MachineInstr* foldMemoryOperand(MachineFunction &MF,
350 const SmallVectorImpl<unsigned> &Ops,
351 int FrameIndex) const;
353 /// foldMemoryOperand - Same as the previous version except it allows folding
354 /// of any load and store from / to any address, not just from a specific
356 MachineInstr* foldMemoryOperand(MachineFunction &MF,
358 const SmallVectorImpl<unsigned> &Ops,
359 MachineInstr* LoadMI) const;
362 /// foldMemoryOperandImpl - Target-dependent implementation for
363 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
364 /// take care of adding a MachineMemOperand to the newly created instruction.
365 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
367 const SmallVectorImpl<unsigned> &Ops,
368 int FrameIndex) const {
372 /// foldMemoryOperandImpl - Target-dependent implementation for
373 /// foldMemoryOperand. Target-independent code in foldMemoryOperand will
374 /// take care of adding a MachineMemOperand to the newly created instruction.
375 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
377 const SmallVectorImpl<unsigned> &Ops,
378 MachineInstr* LoadMI) const {
383 /// canFoldMemoryOperand - Returns true for the specified load / store if
384 /// folding is possible.
386 bool canFoldMemoryOperand(const MachineInstr *MI,
387 const SmallVectorImpl<unsigned> &Ops) const {
391 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
392 /// a store or a load and a store into two or more instruction. If this is
393 /// possible, returns true as well as the new instructions by reference.
394 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
395 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
396 SmallVectorImpl<MachineInstr*> &NewMIs) const{
400 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
401 SmallVectorImpl<SDNode*> &NewNodes) const {
405 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
406 /// instruction after load / store are unfolded from an instruction of the
407 /// specified opcode. It returns zero if the specified unfolding is not
408 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
409 /// index of the operand which will hold the register holding the loaded
411 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
412 bool UnfoldLoad, bool UnfoldStore,
413 unsigned *LoadRegIndex = 0) const {
417 /// BlockHasNoFallThrough - Return true if the specified block does not
418 /// fall-through into its successor block. This is primarily used when a
419 /// branch is unanalyzable. It is useful for things like unconditional
420 /// indirect branches (jump tables).
421 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
425 /// ReverseBranchCondition - Reverses the branch condition of the specified
426 /// condition list, returning false on success and true if it cannot be
429 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
433 /// insertNoop - Insert a noop into the instruction stream at the specified
435 virtual void insertNoop(MachineBasicBlock &MBB,
436 MachineBasicBlock::iterator MI) const;
438 /// isPredicated - Returns true if the instruction is already predicated.
440 virtual bool isPredicated(const MachineInstr *MI) const {
444 /// isUnpredicatedTerminator - Returns true if the instruction is a
445 /// terminator instruction that has not been predicated.
446 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
448 /// PredicateInstruction - Convert the instruction into a predicated
449 /// instruction. It returns true if the operation was successful.
451 bool PredicateInstruction(MachineInstr *MI,
452 const SmallVectorImpl<MachineOperand> &Pred) const = 0;
454 /// SubsumesPredicate - Returns true if the first specified predicate
455 /// subsumes the second, e.g. GE subsumes GT.
457 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
458 const SmallVectorImpl<MachineOperand> &Pred2) const {
462 /// DefinesPredicate - If the specified instruction defines any predicate
463 /// or condition code register(s) used for predication, returns true as well
464 /// as the definition predicate(s) by reference.
465 virtual bool DefinesPredicate(MachineInstr *MI,
466 std::vector<MachineOperand> &Pred) const {
470 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
471 /// instruction that defines the specified register class.
472 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
476 /// GetInstSize - Returns the size of the specified Instruction.
478 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const {
479 assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!");
483 /// GetFunctionSizeInBytes - Returns the size of the specified
486 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0;
488 /// Measure the specified inline asm to determine an approximation of its
490 virtual unsigned getInlineAsmLength(const char *Str,
491 const MCAsmInfo &MAI) const;
494 /// TargetInstrInfoImpl - This is the default implementation of
495 /// TargetInstrInfo, which just provides a couple of default implementations
496 /// for various methods. This separated out because it is implemented in
497 /// libcodegen, not in libtarget.
498 class TargetInstrInfoImpl : public TargetInstrInfo {
500 TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
501 : TargetInstrInfo(desc, NumOpcodes) {}
503 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
504 bool NewMI = false) const;
505 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
506 unsigned &SrcOpIdx2) const;
507 virtual bool PredicateInstruction(MachineInstr *MI,
508 const SmallVectorImpl<MachineOperand> &Pred) const;
509 virtual void reMaterialize(MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator MI,
511 unsigned DestReg, unsigned SubReg,
512 const MachineInstr *Orig) const;
513 virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
516 } // End llvm namespace