1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/IR/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
25 class SubRegIndex<list<SubRegIndex> comps = []> {
26 string Namespace = "";
28 // ComposedOf - A list of two SubRegIndex instances, [A, B].
29 // This indicates that this SubRegIndex is the result of composing A and B.
30 list<SubRegIndex> ComposedOf = comps;
32 // CoveringSubRegIndices - A list of two or more sub-register indexes that
33 // cover this sub-register.
35 // This field should normally be left blank as TableGen can infer it.
37 // TableGen automatically detects sub-registers that straddle the registers
38 // in the SubRegs field of a Register definition. For example:
40 // Q0 = dsub_0 -> D0, dsub_1 -> D1
41 // Q1 = dsub_0 -> D2, dsub_1 -> D3
42 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2
43 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
45 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given
46 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with
47 // CoveringSubRegIndices = [dsub_1, dsub_2].
48 list<SubRegIndex> CoveringSubRegIndices = [];
51 // RegAltNameIndex - The alternate name set to use for register operands of
52 // this register class when printing.
53 class RegAltNameIndex {
54 string Namespace = "";
56 def NoRegAltName : RegAltNameIndex;
58 // Register - You should define one instance of this class for each register
59 // in the target machine. String n will become the "name" of the register.
60 class Register<string n, list<string> altNames = []> {
61 string Namespace = "";
63 list<string> AltNames = altNames;
65 // Aliases - A list of registers that this register overlaps with. A read or
66 // modification of this register can potentially read or modify the aliased
68 list<Register> Aliases = [];
70 // SubRegs - A list of registers that are parts of this register. Note these
71 // are "immediate" sub-registers and the registers within the list do not
72 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
74 list<Register> SubRegs = [];
76 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
77 // to address it. Sub-sub-register indices are automatically inherited from
79 list<SubRegIndex> SubRegIndices = [];
81 // RegAltNameIndices - The alternate name indices which are valid for this
83 list<RegAltNameIndex> RegAltNameIndices = [];
85 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
86 // These values can be determined by locating the <target>.h file in the
87 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
88 // order of these names correspond to the enumeration used by gcc. A value of
89 // -1 indicates that the gcc number is undefined and -2 that register number
90 // is invalid for this mode/flavour.
91 list<int> DwarfNumbers = [];
93 // CostPerUse - Additional cost of instructions using this register compared
94 // to other registers in its class. The register allocator will try to
95 // minimize the number of instructions using a register with a CostPerUse.
96 // This is used by the x86-64 and ARM Thumb targets where some registers
97 // require larger instruction encodings.
100 // CoveredBySubRegs - When this bit is set, the value of this register is
101 // completely determined by the value of its sub-registers. For example, the
102 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
103 // covered by its sub-register AX.
104 bit CoveredBySubRegs = 0;
106 // HWEncoding - The target specific hardware encoding for this register.
107 bits<16> HWEncoding = 0;
110 // RegisterWithSubRegs - This can be used to define instances of Register which
111 // need to specify sub-registers.
112 // List "subregs" specifies which registers are sub-registers to this one. This
113 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
114 // This allows the code generator to be careful not to put two values with
115 // overlapping live ranges into registers which alias.
116 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
117 let SubRegs = subregs;
120 // DAGOperand - An empty base class that unifies RegisterClass's and other forms
121 // of Operand's that are legal as type qualifiers in DAG patterns. This should
122 // only ever be used for defining multiclasses that are polymorphic over both
123 // RegisterClass's and other Operand's.
126 // RegisterClass - Now that all of the registers are defined, and aliases
127 // between registers are defined, specify which registers belong to which
128 // register classes. This also defines the default allocation order of
129 // registers by register allocators.
131 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
132 dag regList, RegAltNameIndex idx = NoRegAltName>
134 string Namespace = namespace;
136 // RegType - Specify the list ValueType of the registers in this register
137 // class. Note that all registers in a register class must have the same
138 // ValueTypes. This is a list because some targets permit storing different
139 // types in same register, for example vector values with 128-bit total size,
140 // but different count/size of items, like SSE on x86.
142 list<ValueType> RegTypes = regTypes;
144 // Size - Specify the spill size in bits of the registers. A default value of
145 // zero lets tablgen pick an appropriate size.
148 // Alignment - Specify the alignment required of the registers when they are
149 // stored or loaded to memory.
151 int Alignment = alignment;
153 // CopyCost - This value is used to specify the cost of copying a value
154 // between two registers in this register class. The default value is one
155 // meaning it takes a single instruction to perform the copying. A negative
156 // value means copying is extremely expensive or impossible.
159 // MemberList - Specify which registers are in this class. If the
160 // allocation_order_* method are not specified, this also defines the order of
161 // allocation used by the register allocator.
163 dag MemberList = regList;
165 // AltNameIndex - The alternate register name to use when printing operands
166 // of this register class. Every register in the register class must have
167 // a valid alternate name for the given index.
168 RegAltNameIndex altNameIndex = idx;
170 // isAllocatable - Specify that the register class can be used for virtual
171 // registers and register allocation. Some register classes are only used to
172 // model instruction operand constraints, and should have isAllocatable = 0.
173 bit isAllocatable = 1;
175 // AltOrders - List of alternative allocation orders. The default order is
176 // MemberList itself, and that is good enough for most targets since the
177 // register allocators automatically remove reserved registers and move
178 // callee-saved registers to the end.
179 list<dag> AltOrders = [];
181 // AltOrderSelect - The body of a function that selects the allocation order
182 // to use in a given machine function. The code will be inserted in a
183 // function like this:
185 // static inline unsigned f(const MachineFunction &MF) { ... }
187 // The function should return 0 to select the default order defined by
188 // MemberList, 1 to select the first AltOrders entry and so on.
189 code AltOrderSelect = [{}];
192 // The memberList in a RegisterClass is a dag of set operations. TableGen
193 // evaluates these set operations and expand them into register lists. These
194 // are the most common operation, see test/TableGen/SetTheory.td for more
195 // examples of what is possible:
197 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
198 // register class, or a sub-expression. This is also the way to simply list
201 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
203 // (and GPR, CSR) - Set intersection. All registers from the first set that are
204 // also in the second set.
206 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
207 // numbered registers. Takes an optional 4th operand which is a stride to use
208 // when generating the sequence.
210 // (shl GPR, 4) - Remove the first N elements.
212 // (trunc GPR, 4) - Truncate after the first N elements.
214 // (rotl GPR, 1) - Rotate N places to the left.
216 // (rotr GPR, 1) - Rotate N places to the right.
218 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
220 // (interleave A, B, ...) - Interleave the elements from each argument list.
222 // All of these operators work on ordered sets, not lists. That means
223 // duplicates are removed from sub-expressions.
225 // Set operators. The rest is defined in TargetSelectionDAG.td.
230 // RegisterTuples - Automatically generate super-registers by forming tuples of
231 // sub-registers. This is useful for modeling register sequence constraints
232 // with pseudo-registers that are larger than the architectural registers.
234 // The sub-register lists are zipped together:
236 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
238 // Generates the same registers as:
240 // let SubRegIndices = [sube, subo] in {
241 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
242 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
245 // The generated pseudo-registers inherit super-classes and fields from their
246 // first sub-register. Most fields from the Register class are inferred, and
247 // the AsmName and Dwarf numbers are cleared.
249 // RegisterTuples instances can be used in other set operations to form
250 // register classes and so on. This is the only way of using the generated
252 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
253 // SubRegs - N lists of registers to be zipped up. Super-registers are
254 // synthesized from the first element of each SubRegs list, the second
255 // element and so on.
256 list<dag> SubRegs = Regs;
258 // SubRegIndices - N SubRegIndex instances. This provides the names of the
259 // sub-registers in the synthesized super-registers.
260 list<SubRegIndex> SubRegIndices = Indices;
264 //===----------------------------------------------------------------------===//
265 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
266 // to the register numbering used by gcc and gdb. These values are used by a
267 // debug information writer to describe where values may be located during
269 class DwarfRegNum<list<int> Numbers> {
270 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
271 // These values can be determined by locating the <target>.h file in the
272 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
273 // order of these names correspond to the enumeration used by gcc. A value of
274 // -1 indicates that the gcc number is undefined and -2 that register number
275 // is invalid for this mode/flavour.
276 list<int> DwarfNumbers = Numbers;
279 // DwarfRegAlias - This class declares that a given register uses the same dwarf
280 // numbers as another one. This is useful for making it clear that the two
281 // registers do have the same number. It also lets us build a mapping
282 // from dwarf register number to llvm register.
283 class DwarfRegAlias<Register reg> {
284 Register DwarfAlias = reg;
287 //===----------------------------------------------------------------------===//
288 // Pull in the common support for scheduling
290 include "llvm/Target/TargetSchedule.td"
292 class Predicate; // Forward def
294 //===----------------------------------------------------------------------===//
295 // Instruction set description - These classes correspond to the C++ classes in
296 // the Target/TargetInstrInfo.h file.
299 string Namespace = "";
301 dag OutOperandList; // An dag containing the MI def operand list.
302 dag InOperandList; // An dag containing the MI use operand list.
303 string AsmString = ""; // The .s format to print the instruction with.
305 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
306 // otherwise, uninitialized.
309 // The follow state will eventually be inferred automatically from the
310 // instruction pattern.
312 list<Register> Uses = []; // Default to using no non-operand registers
313 list<Register> Defs = []; // Default to modifying no non-operand registers
315 // Predicates - List of predicates which will be turned into isel matching
317 list<Predicate> Predicates = [];
319 // Size - Size of encoded instruction, or zero if the size cannot be determined
323 // DecoderNamespace - The "namespace" in which this instruction exists, on
324 // targets like ARM which multiple ISA namespaces exist.
325 string DecoderNamespace = "";
327 // Code size, for instruction selection.
328 // FIXME: What does this actually mean?
331 // Added complexity passed onto matching pattern.
332 int AddedComplexity = 0;
334 // These bits capture information about the high-level semantics of the
336 bit isReturn = 0; // Is this instruction a return instruction?
337 bit isBranch = 0; // Is this instruction a branch instruction?
338 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
339 bit isCompare = 0; // Is this instruction a comparison instruction?
340 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
341 bit isBitcast = 0; // Is this instruction a bitcast instruction?
342 bit isSelect = 0; // Is this instruction a select instruction?
343 bit isBarrier = 0; // Can control flow fall through this instruction?
344 bit isCall = 0; // Is this instruction a call instruction?
345 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
346 bit mayLoad = ?; // Is it possible for this inst to read memory?
347 bit mayStore = ?; // Is it possible for this inst to write memory?
348 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
349 bit isCommutable = 0; // Is this 3 operand instruction commutable?
350 bit isTerminator = 0; // Is this part of the terminator for a basic block?
351 bit isReMaterializable = 0; // Is this instruction re-materializable?
352 bit isPredicable = 0; // Is this instruction predicable?
353 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
354 bit usesCustomInserter = 0; // Pseudo instr needing special help.
355 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
356 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
357 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
358 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
359 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
360 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
361 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
362 // If so, won't have encoding information for
363 // the [MC]CodeEmitter stuff.
365 // Side effect flags - When set, the flags have these meanings:
367 // hasSideEffects - The instruction has side effects that are not
368 // captured by any operands of the instruction or other flags.
370 // neverHasSideEffects (deprecated) - Set on an instruction with no pattern
371 // if it has no side effects. This is now equivalent to setting
372 // "hasSideEffects = 0".
373 bit hasSideEffects = ?;
374 bit neverHasSideEffects = 0;
376 // Is this instruction a "real" instruction (with a distinct machine
377 // encoding), or is it a pseudo instruction used for codegen modeling
379 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
380 // instructions can (and often do) still have encoding information
381 // associated with them. Once we've migrated all of them over to true
382 // pseudo-instructions that are lowered to real instructions prior to
383 // the printer/emitter, we can remove this attribute and just use isPseudo.
385 // The intended use is:
386 // isPseudo: Does not have encoding information and should be expanded,
387 // at the latest, during lowering to MCInst.
389 // isCodeGenOnly: Does have encoding information and can go through to the
390 // CodeEmitter unchanged, but duplicates a canonical instruction
391 // definition's encoding and should be ignored when constructing the
392 // assembler match tables.
393 bit isCodeGenOnly = 0;
395 // Is this instruction a pseudo instruction for use by the assembler parser.
396 bit isAsmParserOnly = 0;
398 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
400 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
402 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
403 /// be encoded into the output machineinstr.
404 string DisableEncoding = "";
406 string PostEncoderMethod = "";
407 string DecoderMethod = "";
409 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
410 bits<64> TSFlags = 0;
412 ///@name Assembler Parser Support
415 string AsmMatchConverter = "";
417 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
418 /// two-operand matcher inst-alias for a three operand instruction.
419 /// For example, the arm instruction "add r3, r3, r5" can be written
420 /// as "add r3, r5". The constraint is of the same form as a tied-operand
421 /// constraint. For example, "$Rn = $Rd".
422 string TwoOperandAliasConstraint = "";
427 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
428 /// Which instruction it expands to and how the operands map from the
430 class PseudoInstExpansion<dag Result> {
431 dag ResultInst = Result; // The instruction to generate.
435 /// Predicates - These are extra conditionals which are turned into instruction
436 /// selector matching code. Currently each predicate is just a string.
437 class Predicate<string cond> {
438 string CondString = cond;
440 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
441 /// matcher, this is true. Targets should set this by inheriting their
442 /// feature from the AssemblerPredicate class in addition to Predicate.
443 bit AssemblerMatcherPredicate = 0;
445 /// AssemblerCondString - Name of the subtarget feature being tested used
446 /// as alternative condition string used for assembler matcher.
447 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
448 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
449 /// It can also list multiple features separated by ",".
450 /// e.g. "ModeThumb,FeatureThumb2" is translated to
451 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
452 string AssemblerCondString = "";
454 /// PredicateName - User-level name to use for the predicate. Mainly for use
455 /// in diagnostics such as missing feature errors in the asm matcher.
456 string PredicateName = "";
459 /// NoHonorSignDependentRounding - This predicate is true if support for
460 /// sign-dependent-rounding is not enabled.
461 def NoHonorSignDependentRounding
462 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">;
464 class Requires<list<Predicate> preds> {
465 list<Predicate> Predicates = preds;
468 /// ops definition - This is just a simple marker used to identify the operand
469 /// list for an instruction. outs and ins are identical both syntactically and
470 /// semanticallyr; they are used to define def operands and use operands to
471 /// improve readibility. This should be used like this:
472 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
477 /// variable_ops definition - Mark this instruction as taking a variable number
482 /// PointerLikeRegClass - Values that are designed to have pointer width are
483 /// derived from this. TableGen treats the register class as having a symbolic
484 /// type that it doesn't know, and resolves the actual regclass to use by using
485 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
486 class PointerLikeRegClass<int Kind> {
487 int RegClassKind = Kind;
491 /// ptr_rc definition - Mark this operand as being a pointer value whose
492 /// register class is resolved dynamically via a callback to TargetInstrInfo.
493 /// FIXME: We should probably change this to a class which contain a list of
494 /// flags. But currently we have but one flag.
495 def ptr_rc : PointerLikeRegClass<0>;
497 /// unknown definition - Mark this operand as being of unknown type, causing
498 /// it to be resolved by inference in the context it is used.
500 def unknown : unknown_class;
502 /// AsmOperandClass - Representation for the kinds of operands which the target
503 /// specific parser can create and the assembly matcher may need to distinguish.
505 /// Operand classes are used to define the order in which instructions are
506 /// matched, to ensure that the instruction which gets matched for any
507 /// particular list of operands is deterministic.
509 /// The target specific parser must be able to classify a parsed operand into a
510 /// unique class which does not partially overlap with any other classes. It can
511 /// match a subset of some other class, in which case the super class field
512 /// should be defined.
513 class AsmOperandClass {
514 /// The name to use for this class, which should be usable as an enum value.
517 /// The super classes of this operand.
518 list<AsmOperandClass> SuperClasses = [];
520 /// The name of the method on the target specific operand to call to test
521 /// whether the operand is an instance of this class. If not set, this will
522 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
523 /// signature should be:
524 /// bool isFoo() const;
525 string PredicateMethod = ?;
527 /// The name of the method on the target specific operand to call to add the
528 /// target specific operand to an MCInst. If not set, this will default to
529 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
530 /// signature should be:
531 /// void addFooOperands(MCInst &Inst, unsigned N) const;
532 string RenderMethod = ?;
534 /// The name of the method on the target specific operand to call to custom
535 /// handle the operand parsing. This is useful when the operands do not relate
536 /// to immediates or registers and are very instruction specific (as flags to
537 /// set in a processor register, coprocessor number, ...).
538 string ParserMethod = ?;
540 // The diagnostic type to present when referencing this operand in a
541 // match failure error message. By default, use a generic "invalid operand"
542 // diagnostic. The target AsmParser maps these codes to text.
543 string DiagnosticType = "";
546 def ImmAsmOperand : AsmOperandClass {
550 /// Operand Types - These provide the built-in operand types that may be used
551 /// by a target. Targets can optionally provide their own operand types as
552 /// needed, though this should not be needed for RISC targets.
553 class Operand<ValueType ty> : DAGOperand {
555 string PrintMethod = "printOperand";
556 string EncoderMethod = "";
557 string DecoderMethod = "";
558 string AsmOperandLowerMethod = ?;
559 string OperandType = "OPERAND_UNKNOWN";
560 dag MIOperandInfo = (ops);
562 // ParserMatchClass - The "match class" that operands of this type fit
563 // in. Match classes are used to define the order in which instructions are
564 // match, to ensure that which instructions gets matched is deterministic.
566 // The target specific parser must be able to classify an parsed operand into
567 // a unique class, which does not partially overlap with any other classes. It
568 // can match a subset of some other class, in which case the AsmOperandClass
569 // should declare the other operand as one of its super classes.
570 AsmOperandClass ParserMatchClass = ImmAsmOperand;
573 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
575 // RegClass - The register class of the operand.
576 RegisterClass RegClass = regclass;
577 // PrintMethod - The target method to call to print register operands of
578 // this type. The method normally will just use an alt-name index to look
579 // up the name to print. Default to the generic printOperand().
580 string PrintMethod = pm;
581 // ParserMatchClass - The "match class" that operands of this type fit
582 // in. Match classes are used to define the order in which instructions are
583 // match, to ensure that which instructions gets matched is deterministic.
585 // The target specific parser must be able to classify an parsed operand into
586 // a unique class, which does not partially overlap with any other classes. It
587 // can match a subset of some other class, in which case the AsmOperandClass
588 // should declare the other operand as one of its super classes.
589 AsmOperandClass ParserMatchClass;
592 let OperandType = "OPERAND_IMMEDIATE" in {
593 def i1imm : Operand<i1>;
594 def i8imm : Operand<i8>;
595 def i16imm : Operand<i16>;
596 def i32imm : Operand<i32>;
597 def i64imm : Operand<i64>;
599 def f32imm : Operand<f32>;
600 def f64imm : Operand<f64>;
603 /// zero_reg definition - Special node to stand for the zero register.
607 /// OperandWithDefaultOps - This Operand class can be used as the parent class
608 /// for an Operand that needs to be initialized with a default value if
609 /// no value is supplied in a pattern. This class can be used to simplify the
610 /// pattern definitions for instructions that have target specific flags
611 /// encoded as immediate operands.
612 class OperandWithDefaultOps<ValueType ty, dag defaultops>
614 dag DefaultOps = defaultops;
617 /// PredicateOperand - This can be used to define a predicate operand for an
618 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
619 /// AlwaysVal specifies the value of this predicate when set to "always
621 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
622 : OperandWithDefaultOps<ty, AlwaysVal> {
623 let MIOperandInfo = OpTypes;
626 /// OptionalDefOperand - This is used to define a optional definition operand
627 /// for an instruction. DefaultOps is the register the operand represents if
628 /// none is supplied, e.g. zero_reg.
629 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
630 : OperandWithDefaultOps<ty, defaultops> {
631 let MIOperandInfo = OpTypes;
635 // InstrInfo - This class should only be instantiated once to provide parameters
636 // which are global to the target machine.
639 // Target can specify its instructions in either big or little-endian formats.
640 // For instance, while both Sparc and PowerPC are big-endian platforms, the
641 // Sparc manual specifies its instructions in the format [31..0] (big), while
642 // PowerPC specifies them using the format [0..31] (little).
643 bit isLittleEndianEncoding = 0;
645 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
646 // by default, and TableGen will infer their value from the instruction
647 // pattern when possible.
649 // Normally, TableGen will issue an error it it can't infer the value of a
650 // property that hasn't been set explicitly. When guessInstructionProperties
651 // is set, it will guess a safe value instead.
653 // This option is a temporary migration help. It will go away.
654 bit guessInstructionProperties = 1;
657 // Standard Pseudo Instructions.
658 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
659 // Only these instructions are allowed in the TargetOpcode namespace.
660 let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
661 def PHI : Instruction {
662 let OutOperandList = (outs);
663 let InOperandList = (ins variable_ops);
664 let AsmString = "PHINODE";
666 def INLINEASM : Instruction {
667 let OutOperandList = (outs);
668 let InOperandList = (ins variable_ops);
670 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
672 def PROLOG_LABEL : Instruction {
673 let OutOperandList = (outs);
674 let InOperandList = (ins i32imm:$id);
677 let isNotDuplicable = 1;
679 def EH_LABEL : Instruction {
680 let OutOperandList = (outs);
681 let InOperandList = (ins i32imm:$id);
684 let isNotDuplicable = 1;
686 def GC_LABEL : Instruction {
687 let OutOperandList = (outs);
688 let InOperandList = (ins i32imm:$id);
691 let isNotDuplicable = 1;
693 def KILL : Instruction {
694 let OutOperandList = (outs);
695 let InOperandList = (ins variable_ops);
697 let neverHasSideEffects = 1;
699 def EXTRACT_SUBREG : Instruction {
700 let OutOperandList = (outs unknown:$dst);
701 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
703 let neverHasSideEffects = 1;
705 def INSERT_SUBREG : Instruction {
706 let OutOperandList = (outs unknown:$dst);
707 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
709 let neverHasSideEffects = 1;
710 let Constraints = "$supersrc = $dst";
712 def IMPLICIT_DEF : Instruction {
713 let OutOperandList = (outs unknown:$dst);
714 let InOperandList = (ins);
716 let neverHasSideEffects = 1;
717 let isReMaterializable = 1;
718 let isAsCheapAsAMove = 1;
720 def SUBREG_TO_REG : Instruction {
721 let OutOperandList = (outs unknown:$dst);
722 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
724 let neverHasSideEffects = 1;
726 def COPY_TO_REGCLASS : Instruction {
727 let OutOperandList = (outs unknown:$dst);
728 let InOperandList = (ins unknown:$src, i32imm:$regclass);
730 let neverHasSideEffects = 1;
731 let isAsCheapAsAMove = 1;
733 def DBG_VALUE : Instruction {
734 let OutOperandList = (outs);
735 let InOperandList = (ins variable_ops);
736 let AsmString = "DBG_VALUE";
737 let neverHasSideEffects = 1;
739 def REG_SEQUENCE : Instruction {
740 let OutOperandList = (outs unknown:$dst);
741 let InOperandList = (ins variable_ops);
743 let neverHasSideEffects = 1;
744 let isAsCheapAsAMove = 1;
746 def COPY : Instruction {
747 let OutOperandList = (outs unknown:$dst);
748 let InOperandList = (ins unknown:$src);
750 let neverHasSideEffects = 1;
751 let isAsCheapAsAMove = 1;
753 def BUNDLE : Instruction {
754 let OutOperandList = (outs);
755 let InOperandList = (ins variable_ops);
756 let AsmString = "BUNDLE";
758 def LIFETIME_START : Instruction {
759 let OutOperandList = (outs);
760 let InOperandList = (ins i32imm:$id);
761 let AsmString = "LIFETIME_START";
762 let neverHasSideEffects = 1;
764 def LIFETIME_END : Instruction {
765 let OutOperandList = (outs);
766 let InOperandList = (ins i32imm:$id);
767 let AsmString = "LIFETIME_END";
768 let neverHasSideEffects = 1;
772 //===----------------------------------------------------------------------===//
773 // AsmParser - This class can be implemented by targets that wish to implement
776 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
777 // syntax on X86 for example).
780 // AsmParserClassName - This specifies the suffix to use for the asmparser
781 // class. Generated AsmParser classes are always prefixed with the target
783 string AsmParserClassName = "AsmParser";
785 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
786 // function of the AsmParser class to call on every matched instruction.
787 // This can be used to perform target specific instruction post-processing.
788 string AsmParserInstCleanup = "";
790 //ShouldEmitMatchRegisterName - Set to false if the target needs a hand
791 //written register name matcher
792 bit ShouldEmitMatchRegisterName = 1;
794 def DefaultAsmParser : AsmParser;
796 //===----------------------------------------------------------------------===//
797 // AsmParserVariant - Subtargets can have multiple different assembly parsers
798 // (e.g. AT&T vs Intel syntax on X86 for example). This class can be
799 // implemented by targets to describe such variants.
801 class AsmParserVariant {
802 // Variant - AsmParsers can be of multiple different variants. Variants are
803 // used to support targets that need to parser multiple formats for the
804 // assembly language.
807 // CommentDelimiter - If given, the delimiter string used to recognize
808 // comments which are hard coded in the .td assembler strings for individual
810 string CommentDelimiter = "";
812 // RegisterPrefix - If given, the token prefix which indicates a register
813 // token. This is used by the matcher to automatically recognize hard coded
814 // register tokens as constrained registers, instead of tokens, for the
815 // purposes of matching.
816 string RegisterPrefix = "";
818 def DefaultAsmParserVariant : AsmParserVariant;
820 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
821 /// matches instructions and aliases.
822 class AssemblerPredicate<string cond, string name = ""> {
823 bit AssemblerMatcherPredicate = 1;
824 string AssemblerCondString = cond;
825 string PredicateName = name;
828 /// TokenAlias - This class allows targets to define assembler token
829 /// operand aliases. That is, a token literal operand which is equivalent
830 /// to another, canonical, token literal. For example, ARM allows:
831 /// vmov.u32 s4, #0 -> vmov.i32, #0
832 /// 'u32' is a more specific designator for the 32-bit integer type specifier
833 /// and is legal for any instruction which accepts 'i32' as a datatype suffix.
834 /// def : TokenAlias<".u32", ".i32">;
836 /// This works by marking the match class of 'From' as a subclass of the
837 /// match class of 'To'.
838 class TokenAlias<string From, string To> {
839 string FromToken = From;
843 /// MnemonicAlias - This class allows targets to define assembler mnemonic
844 /// aliases. This should be used when all forms of one mnemonic are accepted
845 /// with a different mnemonic. For example, X86 allows:
846 /// sal %al, 1 -> shl %al, 1
847 /// sal %ax, %cl -> shl %ax, %cl
848 /// sal %eax, %cl -> shl %eax, %cl
849 /// etc. Though "sal" is accepted with many forms, all of them are directly
850 /// translated to a shl, so it can be handled with (in the case of X86, it
851 /// actually has one for each suffix as well):
852 /// def : MnemonicAlias<"sal", "shl">;
854 /// Mnemonic aliases are mapped before any other translation in the match phase,
855 /// and do allow Requires predicates, e.g.:
857 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
858 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
860 class MnemonicAlias<string From, string To> {
861 string FromMnemonic = From;
862 string ToMnemonic = To;
864 // Predicates - Predicates that must be true for this remapping to happen.
865 list<Predicate> Predicates = [];
868 /// InstAlias - This defines an alternate assembly syntax that is allowed to
869 /// match an instruction that has a different (more canonical) assembly
871 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
872 string AsmString = Asm; // The .s format to match the instruction with.
873 dag ResultInst = Result; // The MCInst to generate.
874 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
876 // Predicates - Predicates that must be true for this to match.
877 list<Predicate> Predicates = [];
880 //===----------------------------------------------------------------------===//
881 // AsmWriter - This class can be implemented by targets that need to customize
882 // the format of the .s file writer.
884 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
885 // on X86 for example).
888 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
889 // class. Generated AsmWriter classes are always prefixed with the target
891 string AsmWriterClassName = "AsmPrinter";
893 // Variant - AsmWriters can be of multiple different variants. Variants are
894 // used to support targets that need to emit assembly code in ways that are
895 // mostly the same for different targets, but have minor differences in
896 // syntax. If the asmstring contains {|} characters in them, this integer
897 // will specify which alternative to use. For example "{x|y|z}" with Variant
898 // == 1, will expand to "y".
902 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
903 // layout, the asmwriter can actually generate output in this columns (in
904 // verbose-asm mode). These two values indicate the width of the first column
905 // (the "opcode" area) and the width to reserve for subsequent operands. When
906 // verbose asm mode is enabled, operands will be indented to respect this.
907 int FirstOperandColumn = -1;
909 // OperandSpacing - Space between operand columns.
910 int OperandSpacing = -1;
912 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
913 // generation of the printInstruction() method. For MC printers, it takes
914 // an MCInstr* operand, otherwise it takes a MachineInstr*.
915 bit isMCAsmWriter = 0;
917 def DefaultAsmWriter : AsmWriter;
920 //===----------------------------------------------------------------------===//
921 // Target - This class contains the "global" target information
924 // InstructionSet - Instruction set description for this target.
925 InstrInfo InstructionSet;
927 // AssemblyParsers - The AsmParser instances available for this target.
928 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
930 /// AssemblyParserVariants - The AsmParserVariant instances available for
932 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant];
934 // AssemblyWriters - The AsmWriter instances available for this target.
935 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
938 //===----------------------------------------------------------------------===//
939 // SubtargetFeature - A characteristic of the chip set.
941 class SubtargetFeature<string n, string a, string v, string d,
942 list<SubtargetFeature> i = []> {
943 // Name - Feature name. Used by command line (-mattr=) to determine the
944 // appropriate target chip.
948 // Attribute - Attribute to be set by feature.
950 string Attribute = a;
952 // Value - Value the attribute to be set to by feature.
956 // Desc - Feature description. Used by command line (-mattr=) to display help
961 // Implies - Features that this feature implies are present. If one of those
962 // features isn't set, then this one shouldn't be set either.
964 list<SubtargetFeature> Implies = i;
967 //===----------------------------------------------------------------------===//
968 // Processor chip sets - These values represent each of the chip sets supported
969 // by the scheduler. Each Processor definition requires corresponding
970 // instruction itineraries.
972 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
973 // Name - Chip set name. Used by command line (-mcpu=) to determine the
974 // appropriate target chip.
978 // SchedModel - The machine model for scheduling and instruction cost.
980 SchedMachineModel SchedModel = NoSchedModel;
982 // ProcItin - The scheduling information for the target processor.
984 ProcessorItineraries ProcItin = pi;
986 // Features - list of
987 list<SubtargetFeature> Features = f;
990 // ProcessorModel allows subtargets to specify the more general
991 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
992 // gradually move to this newer form.
994 // Although this class always passes NoItineraries to the Processor
995 // class, the SchedMachineModel may still define valid Itineraries.
996 class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
997 : Processor<n, NoItineraries, f> {
1001 //===----------------------------------------------------------------------===//
1002 // InstrMapping - This class is used to create mapping tables to relate
1003 // instructions with each other based on the values specified in RowFields,
1004 // ColFields, KeyCol and ValueCols.
1006 class InstrMapping {
1007 // FilterClass - Used to limit search space only to the instructions that
1008 // define the relationship modeled by this InstrMapping record.
1011 // RowFields - List of fields/attributes that should be same for all the
1012 // instructions in a row of the relation table. Think of this as a set of
1013 // properties shared by all the instructions related by this relationship
1014 // model and is used to categorize instructions into subgroups. For instance,
1015 // if we want to define a relation that maps 'Add' instruction to its
1016 // predicated forms, we can define RowFields like this:
1018 // let RowFields = BaseOp
1019 // All add instruction predicated/non-predicated will have to set their BaseOp
1020 // to the same value.
1022 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' }
1023 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' }
1024 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' }
1025 list<string> RowFields = [];
1027 // List of fields/attributes that are same for all the instructions
1028 // in a column of the relation table.
1029 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged
1030 // based on the 'predSense' values. All the instruction in a specific
1031 // column have the same value and it is fixed for the column according
1032 // to the values set in 'ValueCols'.
1033 list<string> ColFields = [];
1035 // Values for the fields/attributes listed in 'ColFields'.
1036 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction
1037 // that models this relation) should be non-predicated.
1038 // In the example above, 'Add' is the key instruction.
1039 list<string> KeyCol = [];
1041 // List of values for the fields/attributes listed in 'ColFields', one for
1042 // each column in the relation table.
1044 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the
1045 // table. First column requires all the instructions to have predSense
1046 // set to 'true' and second column requires it to be 'false'.
1047 list<list<string> > ValueCols = [];
1050 //===----------------------------------------------------------------------===//
1051 // Pull in the common support for calling conventions.
1053 include "llvm/Target/TargetCallingConv.td"
1055 //===----------------------------------------------------------------------===//
1056 // Pull in the common support for DAG isel generation.
1058 include "llvm/Target/TargetSelectionDAG.td"