1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // Aliases - A list of registers that this register overlaps with. A read or
36 // modification of this register can potentially read or modify the aliased
38 list<Register> Aliases = [];
40 // SubRegs - A list of registers that are parts of this register. Note these
41 // are "immediate" sub-registers and the registers within the list do not
42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
44 list<Register> SubRegs = [];
46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
47 // to address it. Sub-sub-register indices are automatically inherited from
49 list<SubRegIndex> SubRegIndices = [];
51 // CompositeIndices - Specify subreg indices that don't correspond directly to
52 // a register in SubRegs and are not inherited. The following formats are
55 // (a) Identity - Reg:a == Reg
56 // (a b) Alias - Reg:a == Reg:b
57 // (a b,c) Composite - Reg:a == (Reg:b):c
59 // This can be used to disambiguate a sub-sub-register that exists in more
60 // than one subregister and other weird stuff.
61 list<dag> CompositeIndices = [];
63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
64 // These values can be determined by locating the <target>.h file in the
65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
66 // order of these names correspond to the enumeration used by gcc. A value of
67 // -1 indicates that the gcc number is undefined and -2 that register number
68 // is invalid for this mode/flavour.
69 list<int> DwarfNumbers = [];
71 // CostPerUse - Additional cost of instructions using this register compared
72 // to other registers in its class. The register allocator will try to
73 // minimize the number of instructions using a register with a CostPerUse.
74 // This is used by the x86-64 and ARM Thumb targets where some registers
75 // require larger instruction encodings.
79 // RegisterWithSubRegs - This can be used to define instances of Register which
80 // need to specify sub-registers.
81 // List "subregs" specifies which registers are sub-registers to this one. This
82 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
83 // This allows the code generator to be careful not to put two values with
84 // overlapping live ranges into registers which alias.
85 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
86 let SubRegs = subregs;
89 // RegisterClass - Now that all of the registers are defined, and aliases
90 // between registers are defined, specify which registers belong to which
91 // register classes. This also defines the default allocation order of
92 // registers by register allocators.
94 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
96 string Namespace = namespace;
98 // RegType - Specify the list ValueType of the registers in this register
99 // class. Note that all registers in a register class must have the same
100 // ValueTypes. This is a list because some targets permit storing different
101 // types in same register, for example vector values with 128-bit total size,
102 // but different count/size of items, like SSE on x86.
104 list<ValueType> RegTypes = regTypes;
106 // Size - Specify the spill size in bits of the registers. A default value of
107 // zero lets tablgen pick an appropriate size.
110 // Alignment - Specify the alignment required of the registers when they are
111 // stored or loaded to memory.
113 int Alignment = alignment;
115 // CopyCost - This value is used to specify the cost of copying a value
116 // between two registers in this register class. The default value is one
117 // meaning it takes a single instruction to perform the copying. A negative
118 // value means copying is extremely expensive or impossible.
121 // MemberList - Specify which registers are in this class. If the
122 // allocation_order_* method are not specified, this also defines the order of
123 // allocation used by the register allocator.
125 dag MemberList = regList;
127 // SubRegClasses - Specify the register class of subregisters as a list of
128 // dags: (RegClass SubRegIndex, SubRegindex, ...)
129 list<dag> SubRegClasses = [];
131 // isAllocatable - Specify that the register class can be used for virtual
132 // registers and register allocation. Some register classes are only used to
133 // model instruction operand constraints, and should have isAllocatable = 0.
134 bit isAllocatable = 1;
136 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
137 // code into a generated register class. The normal usage of this is to
138 // overload virtual methods.
139 code MethodProtos = [{}];
140 code MethodBodies = [{}];
143 // The memberList in a RegisterClass is a dag of set operations. TableGen
144 // evaluates these set operations and expand them into register lists. These
145 // are the most common operation, see test/TableGen/SetTheory.td for more
146 // examples of what is possible:
148 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
149 // register class, or a sub-expression. This is also the way to simply list
152 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
154 // (and GPR, CSR) - Set intersection. All registers from the first set that are
155 // also in the second set.
157 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
158 // numbered registers.
160 // (shl GPR, 4) - Remove the first N elements.
162 // (trunc GPR, 4) - Truncate after the first N elements.
164 // (rotl GPR, 1) - Rotate N places to the left.
166 // (rotr GPR, 1) - Rotate N places to the right.
168 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
170 // All of these operators work on ordered sets, not lists. That means
171 // duplicates are removed from sub-expressions.
173 // Set operators. The rest is defined in TargetSelectionDAG.td.
177 //===----------------------------------------------------------------------===//
178 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
179 // to the register numbering used by gcc and gdb. These values are used by a
180 // debug information writer to describe where values may be located during
182 class DwarfRegNum<list<int> Numbers> {
183 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
184 // These values can be determined by locating the <target>.h file in the
185 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
186 // order of these names correspond to the enumeration used by gcc. A value of
187 // -1 indicates that the gcc number is undefined and -2 that register number
188 // is invalid for this mode/flavour.
189 list<int> DwarfNumbers = Numbers;
192 // DwarfRegAlias - This class declares that a given register uses the same dwarf
193 // numbers as another one. This is useful for making it clear that the two
194 // registers do have the same number. It also lets us build a mapping
195 // from dwarf register number to llvm register.
196 class DwarfRegAlias<Register reg> {
197 Register DwarfAlias = reg;
200 //===----------------------------------------------------------------------===//
201 // Pull in the common support for scheduling
203 include "llvm/Target/TargetSchedule.td"
205 class Predicate; // Forward def
207 //===----------------------------------------------------------------------===//
208 // Instruction set description - These classes correspond to the C++ classes in
209 // the Target/TargetInstrInfo.h file.
212 string Namespace = "";
214 dag OutOperandList; // An dag containing the MI def operand list.
215 dag InOperandList; // An dag containing the MI use operand list.
216 string AsmString = ""; // The .s format to print the instruction with.
218 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
219 // otherwise, uninitialized.
222 // The follow state will eventually be inferred automatically from the
223 // instruction pattern.
225 list<Register> Uses = []; // Default to using no non-operand registers
226 list<Register> Defs = []; // Default to modifying no non-operand registers
228 // Predicates - List of predicates which will be turned into isel matching
230 list<Predicate> Predicates = [];
235 // Added complexity passed onto matching pattern.
236 int AddedComplexity = 0;
238 // These bits capture information about the high-level semantics of the
240 bit isReturn = 0; // Is this instruction a return instruction?
241 bit isBranch = 0; // Is this instruction a branch instruction?
242 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
243 bit isCompare = 0; // Is this instruction a comparison instruction?
244 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
245 bit isBitcast = 0; // Is this instruction a bitcast instruction?
246 bit isBarrier = 0; // Can control flow fall through this instruction?
247 bit isCall = 0; // Is this instruction a call instruction?
248 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
249 bit mayLoad = 0; // Is it possible for this inst to read memory?
250 bit mayStore = 0; // Is it possible for this inst to write memory?
251 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
252 bit isCommutable = 0; // Is this 3 operand instruction commutable?
253 bit isTerminator = 0; // Is this part of the terminator for a basic block?
254 bit isReMaterializable = 0; // Is this instruction re-materializable?
255 bit isPredicable = 0; // Is this instruction predicable?
256 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
257 bit usesCustomInserter = 0; // Pseudo instr needing special help.
258 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
259 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
260 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
261 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
262 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
264 // Side effect flags - When set, the flags have these meanings:
266 // hasSideEffects - The instruction has side effects that are not
267 // captured by any operands of the instruction or other flags.
269 // neverHasSideEffects - Set on an instruction with no pattern if it has no
271 bit hasSideEffects = 0;
272 bit neverHasSideEffects = 0;
274 // Is this instruction a "real" instruction (with a distinct machine
275 // encoding), or is it a pseudo instruction used for codegen modeling
277 bit isCodeGenOnly = 0;
279 // Is this instruction a pseudo instruction for use by the assembler parser.
280 bit isAsmParserOnly = 0;
282 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
284 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
286 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
287 /// be encoded into the output machineinstr.
288 string DisableEncoding = "";
290 string PostEncoderMethod = "";
291 string DecoderMethod = "";
293 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
294 bits<64> TSFlags = 0;
296 ///@name Assembler Parser Support
299 string AsmMatchConverter = "";
304 /// Predicates - These are extra conditionals which are turned into instruction
305 /// selector matching code. Currently each predicate is just a string.
306 class Predicate<string cond> {
307 string CondString = cond;
309 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
310 /// matcher, this is true. Targets should set this by inheriting their
311 /// feature from the AssemblerPredicate class in addition to Predicate.
312 bit AssemblerMatcherPredicate = 0;
315 /// NoHonorSignDependentRounding - This predicate is true if support for
316 /// sign-dependent-rounding is not enabled.
317 def NoHonorSignDependentRounding
318 : Predicate<"!HonorSignDependentRoundingFPMath()">;
320 class Requires<list<Predicate> preds> {
321 list<Predicate> Predicates = preds;
324 /// ops definition - This is just a simple marker used to identify the operand
325 /// list for an instruction. outs and ins are identical both syntactically and
326 /// semanticallyr; they are used to define def operands and use operands to
327 /// improve readibility. This should be used like this:
328 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
333 /// variable_ops definition - Mark this instruction as taking a variable number
338 /// PointerLikeRegClass - Values that are designed to have pointer width are
339 /// derived from this. TableGen treats the register class as having a symbolic
340 /// type that it doesn't know, and resolves the actual regclass to use by using
341 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
342 class PointerLikeRegClass<int Kind> {
343 int RegClassKind = Kind;
347 /// ptr_rc definition - Mark this operand as being a pointer value whose
348 /// register class is resolved dynamically via a callback to TargetInstrInfo.
349 /// FIXME: We should probably change this to a class which contain a list of
350 /// flags. But currently we have but one flag.
351 def ptr_rc : PointerLikeRegClass<0>;
353 /// unknown definition - Mark this operand as being of unknown type, causing
354 /// it to be resolved by inference in the context it is used.
357 /// AsmOperandClass - Representation for the kinds of operands which the target
358 /// specific parser can create and the assembly matcher may need to distinguish.
360 /// Operand classes are used to define the order in which instructions are
361 /// matched, to ensure that the instruction which gets matched for any
362 /// particular list of operands is deterministic.
364 /// The target specific parser must be able to classify a parsed operand into a
365 /// unique class which does not partially overlap with any other classes. It can
366 /// match a subset of some other class, in which case the super class field
367 /// should be defined.
368 class AsmOperandClass {
369 /// The name to use for this class, which should be usable as an enum value.
372 /// The super classes of this operand.
373 list<AsmOperandClass> SuperClasses = [];
375 /// The name of the method on the target specific operand to call to test
376 /// whether the operand is an instance of this class. If not set, this will
377 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
378 /// signature should be:
379 /// bool isFoo() const;
380 string PredicateMethod = ?;
382 /// The name of the method on the target specific operand to call to add the
383 /// target specific operand to an MCInst. If not set, this will default to
384 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
385 /// signature should be:
386 /// void addFooOperands(MCInst &Inst, unsigned N) const;
387 string RenderMethod = ?;
389 /// The name of the method on the target specific operand to call to custom
390 /// handle the operand parsing. This is useful when the operands do not relate
391 /// to immediates or registers and are very instruction specific (as flags to
392 /// set in a processor register, coprocessor number, ...).
393 string ParserMethod = ?;
396 def ImmAsmOperand : AsmOperandClass {
400 /// Operand Types - These provide the built-in operand types that may be used
401 /// by a target. Targets can optionally provide their own operand types as
402 /// needed, though this should not be needed for RISC targets.
403 class Operand<ValueType ty> {
405 string PrintMethod = "printOperand";
406 string EncoderMethod = "";
407 string DecoderMethod = "";
408 string AsmOperandLowerMethod = ?;
409 dag MIOperandInfo = (ops);
411 // ParserMatchClass - The "match class" that operands of this type fit
412 // in. Match classes are used to define the order in which instructions are
413 // match, to ensure that which instructions gets matched is deterministic.
415 // The target specific parser must be able to classify an parsed operand into
416 // a unique class, which does not partially overlap with any other classes. It
417 // can match a subset of some other class, in which case the AsmOperandClass
418 // should declare the other operand as one of its super classes.
419 AsmOperandClass ParserMatchClass = ImmAsmOperand;
422 def i1imm : Operand<i1>;
423 def i8imm : Operand<i8>;
424 def i16imm : Operand<i16>;
425 def i32imm : Operand<i32>;
426 def i64imm : Operand<i64>;
428 def f32imm : Operand<f32>;
429 def f64imm : Operand<f64>;
431 /// zero_reg definition - Special node to stand for the zero register.
435 /// PredicateOperand - This can be used to define a predicate operand for an
436 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
437 /// AlwaysVal specifies the value of this predicate when set to "always
439 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
441 let MIOperandInfo = OpTypes;
442 dag DefaultOps = AlwaysVal;
445 /// OptionalDefOperand - This is used to define a optional definition operand
446 /// for an instruction. DefaultOps is the register the operand represents if
447 /// none is supplied, e.g. zero_reg.
448 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
450 let MIOperandInfo = OpTypes;
451 dag DefaultOps = defaultops;
455 // InstrInfo - This class should only be instantiated once to provide parameters
456 // which are global to the target machine.
459 // Target can specify its instructions in either big or little-endian formats.
460 // For instance, while both Sparc and PowerPC are big-endian platforms, the
461 // Sparc manual specifies its instructions in the format [31..0] (big), while
462 // PowerPC specifies them using the format [0..31] (little).
463 bit isLittleEndianEncoding = 0;
466 // Standard Pseudo Instructions.
467 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
468 // Only these instructions are allowed in the TargetOpcode namespace.
469 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
470 def PHI : Instruction {
471 let OutOperandList = (outs);
472 let InOperandList = (ins variable_ops);
473 let AsmString = "PHINODE";
475 def INLINEASM : Instruction {
476 let OutOperandList = (outs);
477 let InOperandList = (ins variable_ops);
479 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
481 def PROLOG_LABEL : Instruction {
482 let OutOperandList = (outs);
483 let InOperandList = (ins i32imm:$id);
486 let isNotDuplicable = 1;
488 def EH_LABEL : Instruction {
489 let OutOperandList = (outs);
490 let InOperandList = (ins i32imm:$id);
493 let isNotDuplicable = 1;
495 def GC_LABEL : Instruction {
496 let OutOperandList = (outs);
497 let InOperandList = (ins i32imm:$id);
500 let isNotDuplicable = 1;
502 def KILL : Instruction {
503 let OutOperandList = (outs);
504 let InOperandList = (ins variable_ops);
506 let neverHasSideEffects = 1;
508 def EXTRACT_SUBREG : Instruction {
509 let OutOperandList = (outs unknown:$dst);
510 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
512 let neverHasSideEffects = 1;
514 def INSERT_SUBREG : Instruction {
515 let OutOperandList = (outs unknown:$dst);
516 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
518 let neverHasSideEffects = 1;
519 let Constraints = "$supersrc = $dst";
521 def IMPLICIT_DEF : Instruction {
522 let OutOperandList = (outs unknown:$dst);
523 let InOperandList = (ins);
525 let neverHasSideEffects = 1;
526 let isReMaterializable = 1;
527 let isAsCheapAsAMove = 1;
529 def SUBREG_TO_REG : Instruction {
530 let OutOperandList = (outs unknown:$dst);
531 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
533 let neverHasSideEffects = 1;
535 def COPY_TO_REGCLASS : Instruction {
536 let OutOperandList = (outs unknown:$dst);
537 let InOperandList = (ins unknown:$src, i32imm:$regclass);
539 let neverHasSideEffects = 1;
540 let isAsCheapAsAMove = 1;
542 def DBG_VALUE : Instruction {
543 let OutOperandList = (outs);
544 let InOperandList = (ins variable_ops);
545 let AsmString = "DBG_VALUE";
546 let neverHasSideEffects = 1;
548 def REG_SEQUENCE : Instruction {
549 let OutOperandList = (outs unknown:$dst);
550 let InOperandList = (ins variable_ops);
552 let neverHasSideEffects = 1;
553 let isAsCheapAsAMove = 1;
555 def COPY : Instruction {
556 let OutOperandList = (outs unknown:$dst);
557 let InOperandList = (ins unknown:$src);
559 let neverHasSideEffects = 1;
560 let isAsCheapAsAMove = 1;
564 //===----------------------------------------------------------------------===//
565 // AsmParser - This class can be implemented by targets that wish to implement
568 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
569 // syntax on X86 for example).
572 // AsmParserClassName - This specifies the suffix to use for the asmparser
573 // class. Generated AsmParser classes are always prefixed with the target
575 string AsmParserClassName = "AsmParser";
577 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
578 // function of the AsmParser class to call on every matched instruction.
579 // This can be used to perform target specific instruction post-processing.
580 string AsmParserInstCleanup = "";
582 // Variant - AsmParsers can be of multiple different variants. Variants are
583 // used to support targets that need to parser multiple formats for the
584 // assembly language.
587 // CommentDelimiter - If given, the delimiter string used to recognize
588 // comments which are hard coded in the .td assembler strings for individual
590 string CommentDelimiter = "";
592 // RegisterPrefix - If given, the token prefix which indicates a register
593 // token. This is used by the matcher to automatically recognize hard coded
594 // register tokens as constrained registers, instead of tokens, for the
595 // purposes of matching.
596 string RegisterPrefix = "";
598 def DefaultAsmParser : AsmParser;
600 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
601 /// matches instructions and aliases.
602 class AssemblerPredicate {
603 bit AssemblerMatcherPredicate = 1;
608 /// MnemonicAlias - This class allows targets to define assembler mnemonic
609 /// aliases. This should be used when all forms of one mnemonic are accepted
610 /// with a different mnemonic. For example, X86 allows:
611 /// sal %al, 1 -> shl %al, 1
612 /// sal %ax, %cl -> shl %ax, %cl
613 /// sal %eax, %cl -> shl %eax, %cl
614 /// etc. Though "sal" is accepted with many forms, all of them are directly
615 /// translated to a shl, so it can be handled with (in the case of X86, it
616 /// actually has one for each suffix as well):
617 /// def : MnemonicAlias<"sal", "shl">;
619 /// Mnemonic aliases are mapped before any other translation in the match phase,
620 /// and do allow Requires predicates, e.g.:
622 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
623 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
625 class MnemonicAlias<string From, string To> {
626 string FromMnemonic = From;
627 string ToMnemonic = To;
629 // Predicates - Predicates that must be true for this remapping to happen.
630 list<Predicate> Predicates = [];
633 /// InstAlias - This defines an alternate assembly syntax that is allowed to
634 /// match an instruction that has a different (more canonical) assembly
636 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
637 string AsmString = Asm; // The .s format to match the instruction with.
638 dag ResultInst = Result; // The MCInst to generate.
639 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
641 // Predicates - Predicates that must be true for this to match.
642 list<Predicate> Predicates = [];
645 //===----------------------------------------------------------------------===//
646 // AsmWriter - This class can be implemented by targets that need to customize
647 // the format of the .s file writer.
649 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
650 // on X86 for example).
653 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
654 // class. Generated AsmWriter classes are always prefixed with the target
656 string AsmWriterClassName = "AsmPrinter";
658 // Variant - AsmWriters can be of multiple different variants. Variants are
659 // used to support targets that need to emit assembly code in ways that are
660 // mostly the same for different targets, but have minor differences in
661 // syntax. If the asmstring contains {|} characters in them, this integer
662 // will specify which alternative to use. For example "{x|y|z}" with Variant
663 // == 1, will expand to "y".
667 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
668 // layout, the asmwriter can actually generate output in this columns (in
669 // verbose-asm mode). These two values indicate the width of the first column
670 // (the "opcode" area) and the width to reserve for subsequent operands. When
671 // verbose asm mode is enabled, operands will be indented to respect this.
672 int FirstOperandColumn = -1;
674 // OperandSpacing - Space between operand columns.
675 int OperandSpacing = -1;
677 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
678 // generation of the printInstruction() method. For MC printers, it takes
679 // an MCInstr* operand, otherwise it takes a MachineInstr*.
680 bit isMCAsmWriter = 0;
682 def DefaultAsmWriter : AsmWriter;
685 //===----------------------------------------------------------------------===//
686 // Target - This class contains the "global" target information
689 // InstructionSet - Instruction set description for this target.
690 InstrInfo InstructionSet;
692 // AssemblyParsers - The AsmParser instances available for this target.
693 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
695 // AssemblyWriters - The AsmWriter instances available for this target.
696 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
699 //===----------------------------------------------------------------------===//
700 // SubtargetFeature - A characteristic of the chip set.
702 class SubtargetFeature<string n, string a, string v, string d,
703 list<SubtargetFeature> i = []> {
704 // Name - Feature name. Used by command line (-mattr=) to determine the
705 // appropriate target chip.
709 // Attribute - Attribute to be set by feature.
711 string Attribute = a;
713 // Value - Value the attribute to be set to by feature.
717 // Desc - Feature description. Used by command line (-mattr=) to display help
722 // Implies - Features that this feature implies are present. If one of those
723 // features isn't set, then this one shouldn't be set either.
725 list<SubtargetFeature> Implies = i;
728 //===----------------------------------------------------------------------===//
729 // Processor chip sets - These values represent each of the chip sets supported
730 // by the scheduler. Each Processor definition requires corresponding
731 // instruction itineraries.
733 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
734 // Name - Chip set name. Used by command line (-mcpu=) to determine the
735 // appropriate target chip.
739 // ProcItin - The scheduling information for the target processor.
741 ProcessorItineraries ProcItin = pi;
743 // Features - list of
744 list<SubtargetFeature> Features = f;
747 //===----------------------------------------------------------------------===//
748 // Pull in the common support for calling conventions.
750 include "llvm/Target/TargetCallingConv.td"
752 //===----------------------------------------------------------------------===//
753 // Pull in the common support for DAG isel generation.
755 include "llvm/Target/TargetSelectionDAG.td"