1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // RegAltNameIndex - The alternate name set to use for register operands of
30 // this register class when printing.
31 class RegAltNameIndex {
32 string Namespace = "";
34 def NoRegAltName : RegAltNameIndex;
36 // Register - You should define one instance of this class for each register
37 // in the target machine. String n will become the "name" of the register.
38 class Register<string n, list<string> altNames = []> {
39 string Namespace = "";
41 list<string> AltNames = altNames;
43 // Aliases - A list of registers that this register overlaps with. A read or
44 // modification of this register can potentially read or modify the aliased
46 list<Register> Aliases = [];
48 // SubRegs - A list of registers that are parts of this register. Note these
49 // are "immediate" sub-registers and the registers within the list do not
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
55 // to address it. Sub-sub-register indices are automatically inherited from
57 list<SubRegIndex> SubRegIndices = [];
59 // RegAltNameIndices - The alternate name indices which are valid for this
61 list<RegAltNameIndex> RegAltNameIndices = [];
63 // CompositeIndices - Specify subreg indices that don't correspond directly to
64 // a register in SubRegs and are not inherited. The following formats are
67 // (a) Identity - Reg:a == Reg
68 // (a b) Alias - Reg:a == Reg:b
69 // (a b,c) Composite - Reg:a == (Reg:b):c
71 // This can be used to disambiguate a sub-sub-register that exists in more
72 // than one subregister and other weird stuff.
73 list<dag> CompositeIndices = [];
75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
76 // These values can be determined by locating the <target>.h file in the
77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
78 // order of these names correspond to the enumeration used by gcc. A value of
79 // -1 indicates that the gcc number is undefined and -2 that register number
80 // is invalid for this mode/flavour.
81 list<int> DwarfNumbers = [];
83 // CostPerUse - Additional cost of instructions using this register compared
84 // to other registers in its class. The register allocator will try to
85 // minimize the number of instructions using a register with a CostPerUse.
86 // This is used by the x86-64 and ARM Thumb targets where some registers
87 // require larger instruction encodings.
91 // RegisterWithSubRegs - This can be used to define instances of Register which
92 // need to specify sub-registers.
93 // List "subregs" specifies which registers are sub-registers to this one. This
94 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
95 // This allows the code generator to be careful not to put two values with
96 // overlapping live ranges into registers which alias.
97 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
98 let SubRegs = subregs;
101 // RegisterClass - Now that all of the registers are defined, and aliases
102 // between registers are defined, specify which registers belong to which
103 // register classes. This also defines the default allocation order of
104 // registers by register allocators.
106 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
107 dag regList, RegAltNameIndex idx = NoRegAltName> {
108 string Namespace = namespace;
110 // RegType - Specify the list ValueType of the registers in this register
111 // class. Note that all registers in a register class must have the same
112 // ValueTypes. This is a list because some targets permit storing different
113 // types in same register, for example vector values with 128-bit total size,
114 // but different count/size of items, like SSE on x86.
116 list<ValueType> RegTypes = regTypes;
118 // Size - Specify the spill size in bits of the registers. A default value of
119 // zero lets tablgen pick an appropriate size.
122 // Alignment - Specify the alignment required of the registers when they are
123 // stored or loaded to memory.
125 int Alignment = alignment;
127 // CopyCost - This value is used to specify the cost of copying a value
128 // between two registers in this register class. The default value is one
129 // meaning it takes a single instruction to perform the copying. A negative
130 // value means copying is extremely expensive or impossible.
133 // MemberList - Specify which registers are in this class. If the
134 // allocation_order_* method are not specified, this also defines the order of
135 // allocation used by the register allocator.
137 dag MemberList = regList;
139 // AltNameIndex - The alternate register name to use when printing operands
140 // of this register class. Every register in the register class must have
141 // a valid alternate name for the given index.
142 RegAltNameIndex altNameIndex = idx;
144 // SubRegClasses - Specify the register class of subregisters as a list of
145 // dags: (RegClass SubRegIndex, SubRegindex, ...)
146 list<dag> SubRegClasses = [];
148 // isAllocatable - Specify that the register class can be used for virtual
149 // registers and register allocation. Some register classes are only used to
150 // model instruction operand constraints, and should have isAllocatable = 0.
151 bit isAllocatable = 1;
153 // AltOrders - List of alternative allocation orders. The default order is
154 // MemberList itself, and that is good enough for most targets since the
155 // register allocators automatically remove reserved registers and move
156 // callee-saved registers to the end.
157 list<dag> AltOrders = [];
159 // AltOrderSelect - The body of a function that selects the allocation order
160 // to use in a given machine function. The code will be inserted in a
161 // function like this:
163 // static inline unsigned f(const MachineFunction &MF) { ... }
165 // The function should return 0 to select the default order defined by
166 // MemberList, 1 to select the first AltOrders entry and so on.
167 code AltOrderSelect = [{}];
170 // The memberList in a RegisterClass is a dag of set operations. TableGen
171 // evaluates these set operations and expand them into register lists. These
172 // are the most common operation, see test/TableGen/SetTheory.td for more
173 // examples of what is possible:
175 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
176 // register class, or a sub-expression. This is also the way to simply list
179 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
181 // (and GPR, CSR) - Set intersection. All registers from the first set that are
182 // also in the second set.
184 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
185 // numbered registers.
187 // (shl GPR, 4) - Remove the first N elements.
189 // (trunc GPR, 4) - Truncate after the first N elements.
191 // (rotl GPR, 1) - Rotate N places to the left.
193 // (rotr GPR, 1) - Rotate N places to the right.
195 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
197 // All of these operators work on ordered sets, not lists. That means
198 // duplicates are removed from sub-expressions.
200 // Set operators. The rest is defined in TargetSelectionDAG.td.
204 // RegisterTuples - Automatically generate super-registers by forming tuples of
205 // sub-registers. This is useful for modeling register sequence constraints
206 // with pseudo-registers that are larger than the architectural registers.
208 // The sub-register lists are zipped together:
210 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
212 // Generates the same registers as:
214 // let SubRegIndices = [sube, subo] in {
215 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
216 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
219 // The generated pseudo-registers inherit super-classes and fields from their
220 // first sub-register. Most fields from the Register class are inferred, and
221 // the AsmName and Dwarf numbers are cleared.
223 // RegisterTuples instances can be used in other set operations to form
224 // register classes and so on. This is the only way of using the generated
226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
227 // SubRegs - N lists of registers to be zipped up. Super-registers are
228 // synthesized from the first element of each SubRegs list, the second
229 // element and so on.
230 list<dag> SubRegs = Regs;
232 // SubRegIndices - N SubRegIndex instances. This provides the names of the
233 // sub-registers in the synthesized super-registers.
234 list<SubRegIndex> SubRegIndices = Indices;
236 // Compose sub-register indices like in a normal Register.
237 list<dag> CompositeIndices = [];
241 //===----------------------------------------------------------------------===//
242 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
243 // to the register numbering used by gcc and gdb. These values are used by a
244 // debug information writer to describe where values may be located during
246 class DwarfRegNum<list<int> Numbers> {
247 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
248 // These values can be determined by locating the <target>.h file in the
249 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
250 // order of these names correspond to the enumeration used by gcc. A value of
251 // -1 indicates that the gcc number is undefined and -2 that register number
252 // is invalid for this mode/flavour.
253 list<int> DwarfNumbers = Numbers;
256 // DwarfRegAlias - This class declares that a given register uses the same dwarf
257 // numbers as another one. This is useful for making it clear that the two
258 // registers do have the same number. It also lets us build a mapping
259 // from dwarf register number to llvm register.
260 class DwarfRegAlias<Register reg> {
261 Register DwarfAlias = reg;
264 //===----------------------------------------------------------------------===//
265 // Pull in the common support for scheduling
267 include "llvm/Target/TargetSchedule.td"
269 class Predicate; // Forward def
271 //===----------------------------------------------------------------------===//
272 // Instruction set description - These classes correspond to the C++ classes in
273 // the Target/TargetInstrInfo.h file.
276 string Namespace = "";
278 dag OutOperandList; // An dag containing the MI def operand list.
279 dag InOperandList; // An dag containing the MI use operand list.
280 string AsmString = ""; // The .s format to print the instruction with.
282 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
283 // otherwise, uninitialized.
286 // The follow state will eventually be inferred automatically from the
287 // instruction pattern.
289 list<Register> Uses = []; // Default to using no non-operand registers
290 list<Register> Defs = []; // Default to modifying no non-operand registers
292 // Predicates - List of predicates which will be turned into isel matching
294 list<Predicate> Predicates = [];
299 // Added complexity passed onto matching pattern.
300 int AddedComplexity = 0;
302 // These bits capture information about the high-level semantics of the
304 bit isReturn = 0; // Is this instruction a return instruction?
305 bit isBranch = 0; // Is this instruction a branch instruction?
306 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
307 bit isCompare = 0; // Is this instruction a comparison instruction?
308 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
309 bit isBitcast = 0; // Is this instruction a bitcast instruction?
310 bit isBarrier = 0; // Can control flow fall through this instruction?
311 bit isCall = 0; // Is this instruction a call instruction?
312 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
313 bit mayLoad = 0; // Is it possible for this inst to read memory?
314 bit mayStore = 0; // Is it possible for this inst to write memory?
315 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
316 bit isCommutable = 0; // Is this 3 operand instruction commutable?
317 bit isTerminator = 0; // Is this part of the terminator for a basic block?
318 bit isReMaterializable = 0; // Is this instruction re-materializable?
319 bit isPredicable = 0; // Is this instruction predicable?
320 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
321 bit usesCustomInserter = 0; // Pseudo instr needing special help.
322 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
323 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
324 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
325 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
326 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
328 // Side effect flags - When set, the flags have these meanings:
330 // hasSideEffects - The instruction has side effects that are not
331 // captured by any operands of the instruction or other flags.
333 // neverHasSideEffects - Set on an instruction with no pattern if it has no
335 bit hasSideEffects = 0;
336 bit neverHasSideEffects = 0;
338 // Is this instruction a "real" instruction (with a distinct machine
339 // encoding), or is it a pseudo instruction used for codegen modeling
341 bit isCodeGenOnly = 0;
343 // Is this instruction a pseudo instruction for use by the assembler parser.
344 bit isAsmParserOnly = 0;
346 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
348 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
350 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
351 /// be encoded into the output machineinstr.
352 string DisableEncoding = "";
354 string PostEncoderMethod = "";
355 string DecoderMethod = "";
357 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
358 bits<64> TSFlags = 0;
360 ///@name Assembler Parser Support
363 string AsmMatchConverter = "";
368 /// Predicates - These are extra conditionals which are turned into instruction
369 /// selector matching code. Currently each predicate is just a string.
370 class Predicate<string cond> {
371 string CondString = cond;
373 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
374 /// matcher, this is true. Targets should set this by inheriting their
375 /// feature from the AssemblerPredicate class in addition to Predicate.
376 bit AssemblerMatcherPredicate = 0;
379 /// NoHonorSignDependentRounding - This predicate is true if support for
380 /// sign-dependent-rounding is not enabled.
381 def NoHonorSignDependentRounding
382 : Predicate<"!HonorSignDependentRoundingFPMath()">;
384 class Requires<list<Predicate> preds> {
385 list<Predicate> Predicates = preds;
388 /// ops definition - This is just a simple marker used to identify the operand
389 /// list for an instruction. outs and ins are identical both syntactically and
390 /// semanticallyr; they are used to define def operands and use operands to
391 /// improve readibility. This should be used like this:
392 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
397 /// variable_ops definition - Mark this instruction as taking a variable number
402 /// PointerLikeRegClass - Values that are designed to have pointer width are
403 /// derived from this. TableGen treats the register class as having a symbolic
404 /// type that it doesn't know, and resolves the actual regclass to use by using
405 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
406 class PointerLikeRegClass<int Kind> {
407 int RegClassKind = Kind;
411 /// ptr_rc definition - Mark this operand as being a pointer value whose
412 /// register class is resolved dynamically via a callback to TargetInstrInfo.
413 /// FIXME: We should probably change this to a class which contain a list of
414 /// flags. But currently we have but one flag.
415 def ptr_rc : PointerLikeRegClass<0>;
417 /// unknown definition - Mark this operand as being of unknown type, causing
418 /// it to be resolved by inference in the context it is used.
421 /// AsmOperandClass - Representation for the kinds of operands which the target
422 /// specific parser can create and the assembly matcher may need to distinguish.
424 /// Operand classes are used to define the order in which instructions are
425 /// matched, to ensure that the instruction which gets matched for any
426 /// particular list of operands is deterministic.
428 /// The target specific parser must be able to classify a parsed operand into a
429 /// unique class which does not partially overlap with any other classes. It can
430 /// match a subset of some other class, in which case the super class field
431 /// should be defined.
432 class AsmOperandClass {
433 /// The name to use for this class, which should be usable as an enum value.
436 /// The super classes of this operand.
437 list<AsmOperandClass> SuperClasses = [];
439 /// The name of the method on the target specific operand to call to test
440 /// whether the operand is an instance of this class. If not set, this will
441 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
442 /// signature should be:
443 /// bool isFoo() const;
444 string PredicateMethod = ?;
446 /// The name of the method on the target specific operand to call to add the
447 /// target specific operand to an MCInst. If not set, this will default to
448 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
449 /// signature should be:
450 /// void addFooOperands(MCInst &Inst, unsigned N) const;
451 string RenderMethod = ?;
453 /// The name of the method on the target specific operand to call to custom
454 /// handle the operand parsing. This is useful when the operands do not relate
455 /// to immediates or registers and are very instruction specific (as flags to
456 /// set in a processor register, coprocessor number, ...).
457 string ParserMethod = ?;
460 def ImmAsmOperand : AsmOperandClass {
464 /// Operand Types - These provide the built-in operand types that may be used
465 /// by a target. Targets can optionally provide their own operand types as
466 /// needed, though this should not be needed for RISC targets.
467 class Operand<ValueType ty> {
469 string PrintMethod = "printOperand";
470 string EncoderMethod = "";
471 string DecoderMethod = "";
472 string AsmOperandLowerMethod = ?;
473 dag MIOperandInfo = (ops);
475 // ParserMatchClass - The "match class" that operands of this type fit
476 // in. Match classes are used to define the order in which instructions are
477 // match, to ensure that which instructions gets matched is deterministic.
479 // The target specific parser must be able to classify an parsed operand into
480 // a unique class, which does not partially overlap with any other classes. It
481 // can match a subset of some other class, in which case the AsmOperandClass
482 // should declare the other operand as one of its super classes.
483 AsmOperandClass ParserMatchClass = ImmAsmOperand;
486 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
487 // RegClass - The register class of the operand.
488 RegisterClass RegClass = regclass;
489 // PrintMethod - The target method to call to print register operands of
490 // this type. The method normally will just use an alt-name index to look
491 // up the name to print. Default to the generic printOperand().
492 string PrintMethod = pm;
493 // ParserMatchClass - The "match class" that operands of this type fit
494 // in. Match classes are used to define the order in which instructions are
495 // match, to ensure that which instructions gets matched is deterministic.
497 // The target specific parser must be able to classify an parsed operand into
498 // a unique class, which does not partially overlap with any other classes. It
499 // can match a subset of some other class, in which case the AsmOperandClass
500 // should declare the other operand as one of its super classes.
501 AsmOperandClass ParserMatchClass;
504 def i1imm : Operand<i1>;
505 def i8imm : Operand<i8>;
506 def i16imm : Operand<i16>;
507 def i32imm : Operand<i32>;
508 def i64imm : Operand<i64>;
510 def f32imm : Operand<f32>;
511 def f64imm : Operand<f64>;
513 /// zero_reg definition - Special node to stand for the zero register.
517 /// PredicateOperand - This can be used to define a predicate operand for an
518 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
519 /// AlwaysVal specifies the value of this predicate when set to "always
521 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
523 let MIOperandInfo = OpTypes;
524 dag DefaultOps = AlwaysVal;
527 /// OptionalDefOperand - This is used to define a optional definition operand
528 /// for an instruction. DefaultOps is the register the operand represents if
529 /// none is supplied, e.g. zero_reg.
530 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
532 let MIOperandInfo = OpTypes;
533 dag DefaultOps = defaultops;
537 // InstrInfo - This class should only be instantiated once to provide parameters
538 // which are global to the target machine.
541 // Target can specify its instructions in either big or little-endian formats.
542 // For instance, while both Sparc and PowerPC are big-endian platforms, the
543 // Sparc manual specifies its instructions in the format [31..0] (big), while
544 // PowerPC specifies them using the format [0..31] (little).
545 bit isLittleEndianEncoding = 0;
548 // Standard Pseudo Instructions.
549 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
550 // Only these instructions are allowed in the TargetOpcode namespace.
551 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
552 def PHI : Instruction {
553 let OutOperandList = (outs);
554 let InOperandList = (ins variable_ops);
555 let AsmString = "PHINODE";
557 def INLINEASM : Instruction {
558 let OutOperandList = (outs);
559 let InOperandList = (ins variable_ops);
561 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
563 def PROLOG_LABEL : Instruction {
564 let OutOperandList = (outs);
565 let InOperandList = (ins i32imm:$id);
568 let isNotDuplicable = 1;
570 def EH_LABEL : Instruction {
571 let OutOperandList = (outs);
572 let InOperandList = (ins i32imm:$id);
575 let isNotDuplicable = 1;
577 def GC_LABEL : Instruction {
578 let OutOperandList = (outs);
579 let InOperandList = (ins i32imm:$id);
582 let isNotDuplicable = 1;
584 def KILL : Instruction {
585 let OutOperandList = (outs);
586 let InOperandList = (ins variable_ops);
588 let neverHasSideEffects = 1;
590 def EXTRACT_SUBREG : Instruction {
591 let OutOperandList = (outs unknown:$dst);
592 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
594 let neverHasSideEffects = 1;
596 def INSERT_SUBREG : Instruction {
597 let OutOperandList = (outs unknown:$dst);
598 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
600 let neverHasSideEffects = 1;
601 let Constraints = "$supersrc = $dst";
603 def IMPLICIT_DEF : Instruction {
604 let OutOperandList = (outs unknown:$dst);
605 let InOperandList = (ins);
607 let neverHasSideEffects = 1;
608 let isReMaterializable = 1;
609 let isAsCheapAsAMove = 1;
611 def SUBREG_TO_REG : Instruction {
612 let OutOperandList = (outs unknown:$dst);
613 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
615 let neverHasSideEffects = 1;
617 def COPY_TO_REGCLASS : Instruction {
618 let OutOperandList = (outs unknown:$dst);
619 let InOperandList = (ins unknown:$src, i32imm:$regclass);
621 let neverHasSideEffects = 1;
622 let isAsCheapAsAMove = 1;
624 def DBG_VALUE : Instruction {
625 let OutOperandList = (outs);
626 let InOperandList = (ins variable_ops);
627 let AsmString = "DBG_VALUE";
628 let neverHasSideEffects = 1;
630 def REG_SEQUENCE : Instruction {
631 let OutOperandList = (outs unknown:$dst);
632 let InOperandList = (ins variable_ops);
634 let neverHasSideEffects = 1;
635 let isAsCheapAsAMove = 1;
637 def COPY : Instruction {
638 let OutOperandList = (outs unknown:$dst);
639 let InOperandList = (ins unknown:$src);
641 let neverHasSideEffects = 1;
642 let isAsCheapAsAMove = 1;
646 //===----------------------------------------------------------------------===//
647 // AsmParser - This class can be implemented by targets that wish to implement
650 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
651 // syntax on X86 for example).
654 // AsmParserClassName - This specifies the suffix to use for the asmparser
655 // class. Generated AsmParser classes are always prefixed with the target
657 string AsmParserClassName = "AsmParser";
659 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
660 // function of the AsmParser class to call on every matched instruction.
661 // This can be used to perform target specific instruction post-processing.
662 string AsmParserInstCleanup = "";
664 // Variant - AsmParsers can be of multiple different variants. Variants are
665 // used to support targets that need to parser multiple formats for the
666 // assembly language.
669 // CommentDelimiter - If given, the delimiter string used to recognize
670 // comments which are hard coded in the .td assembler strings for individual
672 string CommentDelimiter = "";
674 // RegisterPrefix - If given, the token prefix which indicates a register
675 // token. This is used by the matcher to automatically recognize hard coded
676 // register tokens as constrained registers, instead of tokens, for the
677 // purposes of matching.
678 string RegisterPrefix = "";
680 def DefaultAsmParser : AsmParser;
682 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
683 /// matches instructions and aliases.
684 class AssemblerPredicate {
685 bit AssemblerMatcherPredicate = 1;
690 /// MnemonicAlias - This class allows targets to define assembler mnemonic
691 /// aliases. This should be used when all forms of one mnemonic are accepted
692 /// with a different mnemonic. For example, X86 allows:
693 /// sal %al, 1 -> shl %al, 1
694 /// sal %ax, %cl -> shl %ax, %cl
695 /// sal %eax, %cl -> shl %eax, %cl
696 /// etc. Though "sal" is accepted with many forms, all of them are directly
697 /// translated to a shl, so it can be handled with (in the case of X86, it
698 /// actually has one for each suffix as well):
699 /// def : MnemonicAlias<"sal", "shl">;
701 /// Mnemonic aliases are mapped before any other translation in the match phase,
702 /// and do allow Requires predicates, e.g.:
704 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
705 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
707 class MnemonicAlias<string From, string To> {
708 string FromMnemonic = From;
709 string ToMnemonic = To;
711 // Predicates - Predicates that must be true for this remapping to happen.
712 list<Predicate> Predicates = [];
715 /// InstAlias - This defines an alternate assembly syntax that is allowed to
716 /// match an instruction that has a different (more canonical) assembly
718 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
719 string AsmString = Asm; // The .s format to match the instruction with.
720 dag ResultInst = Result; // The MCInst to generate.
721 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
723 // Predicates - Predicates that must be true for this to match.
724 list<Predicate> Predicates = [];
727 //===----------------------------------------------------------------------===//
728 // AsmWriter - This class can be implemented by targets that need to customize
729 // the format of the .s file writer.
731 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
732 // on X86 for example).
735 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
736 // class. Generated AsmWriter classes are always prefixed with the target
738 string AsmWriterClassName = "AsmPrinter";
740 // Variant - AsmWriters can be of multiple different variants. Variants are
741 // used to support targets that need to emit assembly code in ways that are
742 // mostly the same for different targets, but have minor differences in
743 // syntax. If the asmstring contains {|} characters in them, this integer
744 // will specify which alternative to use. For example "{x|y|z}" with Variant
745 // == 1, will expand to "y".
749 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
750 // layout, the asmwriter can actually generate output in this columns (in
751 // verbose-asm mode). These two values indicate the width of the first column
752 // (the "opcode" area) and the width to reserve for subsequent operands. When
753 // verbose asm mode is enabled, operands will be indented to respect this.
754 int FirstOperandColumn = -1;
756 // OperandSpacing - Space between operand columns.
757 int OperandSpacing = -1;
759 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
760 // generation of the printInstruction() method. For MC printers, it takes
761 // an MCInstr* operand, otherwise it takes a MachineInstr*.
762 bit isMCAsmWriter = 0;
764 def DefaultAsmWriter : AsmWriter;
767 //===----------------------------------------------------------------------===//
768 // Target - This class contains the "global" target information
771 // InstructionSet - Instruction set description for this target.
772 InstrInfo InstructionSet;
774 // AssemblyParsers - The AsmParser instances available for this target.
775 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
777 // AssemblyWriters - The AsmWriter instances available for this target.
778 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
781 //===----------------------------------------------------------------------===//
782 // SubtargetFeature - A characteristic of the chip set.
784 class SubtargetFeature<string n, string a, string v, string d,
785 list<SubtargetFeature> i = []> {
786 // Name - Feature name. Used by command line (-mattr=) to determine the
787 // appropriate target chip.
791 // Attribute - Attribute to be set by feature.
793 string Attribute = a;
795 // Value - Value the attribute to be set to by feature.
799 // Desc - Feature description. Used by command line (-mattr=) to display help
804 // Implies - Features that this feature implies are present. If one of those
805 // features isn't set, then this one shouldn't be set either.
807 list<SubtargetFeature> Implies = i;
810 //===----------------------------------------------------------------------===//
811 // Processor chip sets - These values represent each of the chip sets supported
812 // by the scheduler. Each Processor definition requires corresponding
813 // instruction itineraries.
815 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
816 // Name - Chip set name. Used by command line (-mcpu=) to determine the
817 // appropriate target chip.
821 // ProcItin - The scheduling information for the target processor.
823 ProcessorItineraries ProcItin = pi;
825 // Features - list of
826 list<SubtargetFeature> Features = f;
829 //===----------------------------------------------------------------------===//
830 // Pull in the common support for calling conventions.
832 include "llvm/Target/TargetCallingConv.td"
834 //===----------------------------------------------------------------------===//
835 // Pull in the common support for DAG isel generation.
837 include "llvm/Target/TargetSelectionDAG.td"