1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // Register - You should define one instance of this class for each register
30 // in the target machine. String n will become the "name" of the register.
31 class Register<string n> {
32 string Namespace = "";
35 // Aliases - A list of registers that this register overlaps with. A read or
36 // modification of this register can potentially read or modify the aliased
38 list<Register> Aliases = [];
40 // SubRegs - A list of registers that are parts of this register. Note these
41 // are "immediate" sub-registers and the registers within the list do not
42 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
44 list<Register> SubRegs = [];
46 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
47 // to address it. Sub-sub-register indices are automatically inherited from
49 list<SubRegIndex> SubRegIndices = [];
51 // CompositeIndices - Specify subreg indices that don't correspond directly to
52 // a register in SubRegs and are not inherited. The following formats are
55 // (a) Identity - Reg:a == Reg
56 // (a b) Alias - Reg:a == Reg:b
57 // (a b,c) Composite - Reg:a == (Reg:b):c
59 // This can be used to disambiguate a sub-sub-register that exists in more
60 // than one subregister and other weird stuff.
61 list<dag> CompositeIndices = [];
63 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
64 // These values can be determined by locating the <target>.h file in the
65 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
66 // order of these names correspond to the enumeration used by gcc. A value of
67 // -1 indicates that the gcc number is undefined and -2 that register number
68 // is invalid for this mode/flavour.
69 list<int> DwarfNumbers = [];
71 // CostPerUse - Additional cost of instructions using this register compared
72 // to other registers in its class. The register allocator will try to
73 // minimize the number of instructions using a register with a CostPerUse.
74 // This is used by the x86-64 and ARM Thumb targets where some registers
75 // require larger instruction encodings.
79 // RegisterWithSubRegs - This can be used to define instances of Register which
80 // need to specify sub-registers.
81 // List "subregs" specifies which registers are sub-registers to this one. This
82 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
83 // This allows the code generator to be careful not to put two values with
84 // overlapping live ranges into registers which alias.
85 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
86 let SubRegs = subregs;
89 // RegisterClass - Now that all of the registers are defined, and aliases
90 // between registers are defined, specify which registers belong to which
91 // register classes. This also defines the default allocation order of
92 // registers by register allocators.
94 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
96 string Namespace = namespace;
98 // RegType - Specify the list ValueType of the registers in this register
99 // class. Note that all registers in a register class must have the same
100 // ValueTypes. This is a list because some targets permit storing different
101 // types in same register, for example vector values with 128-bit total size,
102 // but different count/size of items, like SSE on x86.
104 list<ValueType> RegTypes = regTypes;
106 // Size - Specify the spill size in bits of the registers. A default value of
107 // zero lets tablgen pick an appropriate size.
110 // Alignment - Specify the alignment required of the registers when they are
111 // stored or loaded to memory.
113 int Alignment = alignment;
115 // CopyCost - This value is used to specify the cost of copying a value
116 // between two registers in this register class. The default value is one
117 // meaning it takes a single instruction to perform the copying. A negative
118 // value means copying is extremely expensive or impossible.
121 // MemberList - Specify which registers are in this class. If the
122 // allocation_order_* method are not specified, this also defines the order of
123 // allocation used by the register allocator.
125 dag MemberList = regList;
127 // SubRegClasses - Specify the register class of subregisters as a list of
128 // dags: (RegClass SubRegIndex, SubRegindex, ...)
129 list<dag> SubRegClasses = [];
131 // isAllocatable - Specify that the register class can be used for virtual
132 // registers and register allocation. Some register classes are only used to
133 // model instruction operand constraints, and should have isAllocatable = 0.
134 bit isAllocatable = 1;
136 // AltOrders - List of alternative allocation orders. The default order is
137 // MemberList itself, and that is good enough for most targets since the
138 // register allocators automatically remove reserved registers and move
139 // callee-saved registers to the end.
140 list<dag> AltOrders = [];
142 // AltOrderSelect - The body of a function that selects the allocation order
143 // to use in a given machine function. The code will be inserted in a
144 // function like this:
146 // static inline unsigned f(const MachineFunction &MF) { ... }
148 // The function should return 0 to select the default order defined by
149 // MemberList, 1 to select the first AltOrders entry and so on.
150 code AltOrderSelect = [{}];
153 // The memberList in a RegisterClass is a dag of set operations. TableGen
154 // evaluates these set operations and expand them into register lists. These
155 // are the most common operation, see test/TableGen/SetTheory.td for more
156 // examples of what is possible:
158 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
159 // register class, or a sub-expression. This is also the way to simply list
162 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
164 // (and GPR, CSR) - Set intersection. All registers from the first set that are
165 // also in the second set.
167 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
168 // numbered registers.
170 // (shl GPR, 4) - Remove the first N elements.
172 // (trunc GPR, 4) - Truncate after the first N elements.
174 // (rotl GPR, 1) - Rotate N places to the left.
176 // (rotr GPR, 1) - Rotate N places to the right.
178 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
180 // All of these operators work on ordered sets, not lists. That means
181 // duplicates are removed from sub-expressions.
183 // Set operators. The rest is defined in TargetSelectionDAG.td.
187 // RegisterTuples - Automatically generate super-registers by forming tuples of
188 // sub-registers. This is useful for modeling register sequence constraints
189 // with pseudo-registers that are larger than the architectural registers.
191 // The sub-register lists are zipped together:
193 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
195 // Generates the same registers as:
197 // let SubRegIndices = [sube, subo] in {
198 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
199 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
202 // The generated pseudo-registers inherit super-classes and fields from their
203 // first sub-register. Most fields from the Register class are inferred, and
204 // the AsmName and Dwarf numbers are cleared.
206 // RegisterTuples instances can be used in other set operations to form
207 // register classes and so on. This is the only way of using the generated
209 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
210 // SubRegs - N lists of registers to be zipped up. Super-registers are
211 // synthesized from the first element of each SubRegs list, the second
212 // element and so on.
213 list<dag> SubRegs = Regs;
215 // SubRegIndices - N SubRegIndex instances. This provides the names of the
216 // sub-registers in the synthesized super-registers.
217 list<SubRegIndex> SubRegIndices = Indices;
219 // Compose sub-register indices like in a normal Register.
220 list<dag> CompositeIndices = [];
224 //===----------------------------------------------------------------------===//
225 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
226 // to the register numbering used by gcc and gdb. These values are used by a
227 // debug information writer to describe where values may be located during
229 class DwarfRegNum<list<int> Numbers> {
230 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
231 // These values can be determined by locating the <target>.h file in the
232 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
233 // order of these names correspond to the enumeration used by gcc. A value of
234 // -1 indicates that the gcc number is undefined and -2 that register number
235 // is invalid for this mode/flavour.
236 list<int> DwarfNumbers = Numbers;
239 // DwarfRegAlias - This class declares that a given register uses the same dwarf
240 // numbers as another one. This is useful for making it clear that the two
241 // registers do have the same number. It also lets us build a mapping
242 // from dwarf register number to llvm register.
243 class DwarfRegAlias<Register reg> {
244 Register DwarfAlias = reg;
247 //===----------------------------------------------------------------------===//
248 // Pull in the common support for scheduling
250 include "llvm/Target/TargetSchedule.td"
252 class Predicate; // Forward def
254 //===----------------------------------------------------------------------===//
255 // Instruction set description - These classes correspond to the C++ classes in
256 // the Target/TargetInstrInfo.h file.
259 string Namespace = "";
261 dag OutOperandList; // An dag containing the MI def operand list.
262 dag InOperandList; // An dag containing the MI use operand list.
263 string AsmString = ""; // The .s format to print the instruction with.
265 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
266 // otherwise, uninitialized.
269 // The follow state will eventually be inferred automatically from the
270 // instruction pattern.
272 list<Register> Uses = []; // Default to using no non-operand registers
273 list<Register> Defs = []; // Default to modifying no non-operand registers
275 // Predicates - List of predicates which will be turned into isel matching
277 list<Predicate> Predicates = [];
282 // Added complexity passed onto matching pattern.
283 int AddedComplexity = 0;
285 // These bits capture information about the high-level semantics of the
287 bit isReturn = 0; // Is this instruction a return instruction?
288 bit isBranch = 0; // Is this instruction a branch instruction?
289 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
290 bit isCompare = 0; // Is this instruction a comparison instruction?
291 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
292 bit isBitcast = 0; // Is this instruction a bitcast instruction?
293 bit isBarrier = 0; // Can control flow fall through this instruction?
294 bit isCall = 0; // Is this instruction a call instruction?
295 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
296 bit mayLoad = 0; // Is it possible for this inst to read memory?
297 bit mayStore = 0; // Is it possible for this inst to write memory?
298 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
299 bit isCommutable = 0; // Is this 3 operand instruction commutable?
300 bit isTerminator = 0; // Is this part of the terminator for a basic block?
301 bit isReMaterializable = 0; // Is this instruction re-materializable?
302 bit isPredicable = 0; // Is this instruction predicable?
303 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
304 bit usesCustomInserter = 0; // Pseudo instr needing special help.
305 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
306 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
307 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
308 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
309 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
311 // Side effect flags - When set, the flags have these meanings:
313 // hasSideEffects - The instruction has side effects that are not
314 // captured by any operands of the instruction or other flags.
316 // neverHasSideEffects - Set on an instruction with no pattern if it has no
318 bit hasSideEffects = 0;
319 bit neverHasSideEffects = 0;
321 // Is this instruction a "real" instruction (with a distinct machine
322 // encoding), or is it a pseudo instruction used for codegen modeling
324 bit isCodeGenOnly = 0;
326 // Is this instruction a pseudo instruction for use by the assembler parser.
327 bit isAsmParserOnly = 0;
329 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
331 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
333 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
334 /// be encoded into the output machineinstr.
335 string DisableEncoding = "";
337 string PostEncoderMethod = "";
338 string DecoderMethod = "";
340 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
341 bits<64> TSFlags = 0;
343 ///@name Assembler Parser Support
346 string AsmMatchConverter = "";
351 /// Predicates - These are extra conditionals which are turned into instruction
352 /// selector matching code. Currently each predicate is just a string.
353 class Predicate<string cond> {
354 string CondString = cond;
356 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
357 /// matcher, this is true. Targets should set this by inheriting their
358 /// feature from the AssemblerPredicate class in addition to Predicate.
359 bit AssemblerMatcherPredicate = 0;
362 /// NoHonorSignDependentRounding - This predicate is true if support for
363 /// sign-dependent-rounding is not enabled.
364 def NoHonorSignDependentRounding
365 : Predicate<"!HonorSignDependentRoundingFPMath()">;
367 class Requires<list<Predicate> preds> {
368 list<Predicate> Predicates = preds;
371 /// ops definition - This is just a simple marker used to identify the operand
372 /// list for an instruction. outs and ins are identical both syntactically and
373 /// semanticallyr; they are used to define def operands and use operands to
374 /// improve readibility. This should be used like this:
375 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
380 /// variable_ops definition - Mark this instruction as taking a variable number
385 /// PointerLikeRegClass - Values that are designed to have pointer width are
386 /// derived from this. TableGen treats the register class as having a symbolic
387 /// type that it doesn't know, and resolves the actual regclass to use by using
388 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
389 class PointerLikeRegClass<int Kind> {
390 int RegClassKind = Kind;
394 /// ptr_rc definition - Mark this operand as being a pointer value whose
395 /// register class is resolved dynamically via a callback to TargetInstrInfo.
396 /// FIXME: We should probably change this to a class which contain a list of
397 /// flags. But currently we have but one flag.
398 def ptr_rc : PointerLikeRegClass<0>;
400 /// unknown definition - Mark this operand as being of unknown type, causing
401 /// it to be resolved by inference in the context it is used.
404 /// AsmOperandClass - Representation for the kinds of operands which the target
405 /// specific parser can create and the assembly matcher may need to distinguish.
407 /// Operand classes are used to define the order in which instructions are
408 /// matched, to ensure that the instruction which gets matched for any
409 /// particular list of operands is deterministic.
411 /// The target specific parser must be able to classify a parsed operand into a
412 /// unique class which does not partially overlap with any other classes. It can
413 /// match a subset of some other class, in which case the super class field
414 /// should be defined.
415 class AsmOperandClass {
416 /// The name to use for this class, which should be usable as an enum value.
419 /// The super classes of this operand.
420 list<AsmOperandClass> SuperClasses = [];
422 /// The name of the method on the target specific operand to call to test
423 /// whether the operand is an instance of this class. If not set, this will
424 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
425 /// signature should be:
426 /// bool isFoo() const;
427 string PredicateMethod = ?;
429 /// The name of the method on the target specific operand to call to add the
430 /// target specific operand to an MCInst. If not set, this will default to
431 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
432 /// signature should be:
433 /// void addFooOperands(MCInst &Inst, unsigned N) const;
434 string RenderMethod = ?;
436 /// The name of the method on the target specific operand to call to custom
437 /// handle the operand parsing. This is useful when the operands do not relate
438 /// to immediates or registers and are very instruction specific (as flags to
439 /// set in a processor register, coprocessor number, ...).
440 string ParserMethod = ?;
443 def ImmAsmOperand : AsmOperandClass {
447 /// Operand Types - These provide the built-in operand types that may be used
448 /// by a target. Targets can optionally provide their own operand types as
449 /// needed, though this should not be needed for RISC targets.
450 class Operand<ValueType ty> {
452 string PrintMethod = "printOperand";
453 string EncoderMethod = "";
454 string DecoderMethod = "";
455 string AsmOperandLowerMethod = ?;
456 dag MIOperandInfo = (ops);
458 // ParserMatchClass - The "match class" that operands of this type fit
459 // in. Match classes are used to define the order in which instructions are
460 // match, to ensure that which instructions gets matched is deterministic.
462 // The target specific parser must be able to classify an parsed operand into
463 // a unique class, which does not partially overlap with any other classes. It
464 // can match a subset of some other class, in which case the AsmOperandClass
465 // should declare the other operand as one of its super classes.
466 AsmOperandClass ParserMatchClass = ImmAsmOperand;
469 def i1imm : Operand<i1>;
470 def i8imm : Operand<i8>;
471 def i16imm : Operand<i16>;
472 def i32imm : Operand<i32>;
473 def i64imm : Operand<i64>;
475 def f32imm : Operand<f32>;
476 def f64imm : Operand<f64>;
478 /// zero_reg definition - Special node to stand for the zero register.
482 /// PredicateOperand - This can be used to define a predicate operand for an
483 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
484 /// AlwaysVal specifies the value of this predicate when set to "always
486 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
488 let MIOperandInfo = OpTypes;
489 dag DefaultOps = AlwaysVal;
492 /// OptionalDefOperand - This is used to define a optional definition operand
493 /// for an instruction. DefaultOps is the register the operand represents if
494 /// none is supplied, e.g. zero_reg.
495 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
497 let MIOperandInfo = OpTypes;
498 dag DefaultOps = defaultops;
502 // InstrInfo - This class should only be instantiated once to provide parameters
503 // which are global to the target machine.
506 // Target can specify its instructions in either big or little-endian formats.
507 // For instance, while both Sparc and PowerPC are big-endian platforms, the
508 // Sparc manual specifies its instructions in the format [31..0] (big), while
509 // PowerPC specifies them using the format [0..31] (little).
510 bit isLittleEndianEncoding = 0;
513 // Standard Pseudo Instructions.
514 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
515 // Only these instructions are allowed in the TargetOpcode namespace.
516 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
517 def PHI : Instruction {
518 let OutOperandList = (outs);
519 let InOperandList = (ins variable_ops);
520 let AsmString = "PHINODE";
522 def INLINEASM : Instruction {
523 let OutOperandList = (outs);
524 let InOperandList = (ins variable_ops);
526 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
528 def PROLOG_LABEL : Instruction {
529 let OutOperandList = (outs);
530 let InOperandList = (ins i32imm:$id);
533 let isNotDuplicable = 1;
535 def EH_LABEL : Instruction {
536 let OutOperandList = (outs);
537 let InOperandList = (ins i32imm:$id);
540 let isNotDuplicable = 1;
542 def GC_LABEL : Instruction {
543 let OutOperandList = (outs);
544 let InOperandList = (ins i32imm:$id);
547 let isNotDuplicable = 1;
549 def KILL : Instruction {
550 let OutOperandList = (outs);
551 let InOperandList = (ins variable_ops);
553 let neverHasSideEffects = 1;
555 def EXTRACT_SUBREG : Instruction {
556 let OutOperandList = (outs unknown:$dst);
557 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
559 let neverHasSideEffects = 1;
561 def INSERT_SUBREG : Instruction {
562 let OutOperandList = (outs unknown:$dst);
563 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
565 let neverHasSideEffects = 1;
566 let Constraints = "$supersrc = $dst";
568 def IMPLICIT_DEF : Instruction {
569 let OutOperandList = (outs unknown:$dst);
570 let InOperandList = (ins);
572 let neverHasSideEffects = 1;
573 let isReMaterializable = 1;
574 let isAsCheapAsAMove = 1;
576 def SUBREG_TO_REG : Instruction {
577 let OutOperandList = (outs unknown:$dst);
578 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
580 let neverHasSideEffects = 1;
582 def COPY_TO_REGCLASS : Instruction {
583 let OutOperandList = (outs unknown:$dst);
584 let InOperandList = (ins unknown:$src, i32imm:$regclass);
586 let neverHasSideEffects = 1;
587 let isAsCheapAsAMove = 1;
589 def DBG_VALUE : Instruction {
590 let OutOperandList = (outs);
591 let InOperandList = (ins variable_ops);
592 let AsmString = "DBG_VALUE";
593 let neverHasSideEffects = 1;
595 def REG_SEQUENCE : Instruction {
596 let OutOperandList = (outs unknown:$dst);
597 let InOperandList = (ins variable_ops);
599 let neverHasSideEffects = 1;
600 let isAsCheapAsAMove = 1;
602 def COPY : Instruction {
603 let OutOperandList = (outs unknown:$dst);
604 let InOperandList = (ins unknown:$src);
606 let neverHasSideEffects = 1;
607 let isAsCheapAsAMove = 1;
611 //===----------------------------------------------------------------------===//
612 // AsmParser - This class can be implemented by targets that wish to implement
615 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
616 // syntax on X86 for example).
619 // AsmParserClassName - This specifies the suffix to use for the asmparser
620 // class. Generated AsmParser classes are always prefixed with the target
622 string AsmParserClassName = "AsmParser";
624 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
625 // function of the AsmParser class to call on every matched instruction.
626 // This can be used to perform target specific instruction post-processing.
627 string AsmParserInstCleanup = "";
629 // Variant - AsmParsers can be of multiple different variants. Variants are
630 // used to support targets that need to parser multiple formats for the
631 // assembly language.
634 // CommentDelimiter - If given, the delimiter string used to recognize
635 // comments which are hard coded in the .td assembler strings for individual
637 string CommentDelimiter = "";
639 // RegisterPrefix - If given, the token prefix which indicates a register
640 // token. This is used by the matcher to automatically recognize hard coded
641 // register tokens as constrained registers, instead of tokens, for the
642 // purposes of matching.
643 string RegisterPrefix = "";
645 def DefaultAsmParser : AsmParser;
647 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
648 /// matches instructions and aliases.
649 class AssemblerPredicate {
650 bit AssemblerMatcherPredicate = 1;
655 /// MnemonicAlias - This class allows targets to define assembler mnemonic
656 /// aliases. This should be used when all forms of one mnemonic are accepted
657 /// with a different mnemonic. For example, X86 allows:
658 /// sal %al, 1 -> shl %al, 1
659 /// sal %ax, %cl -> shl %ax, %cl
660 /// sal %eax, %cl -> shl %eax, %cl
661 /// etc. Though "sal" is accepted with many forms, all of them are directly
662 /// translated to a shl, so it can be handled with (in the case of X86, it
663 /// actually has one for each suffix as well):
664 /// def : MnemonicAlias<"sal", "shl">;
666 /// Mnemonic aliases are mapped before any other translation in the match phase,
667 /// and do allow Requires predicates, e.g.:
669 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
670 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
672 class MnemonicAlias<string From, string To> {
673 string FromMnemonic = From;
674 string ToMnemonic = To;
676 // Predicates - Predicates that must be true for this remapping to happen.
677 list<Predicate> Predicates = [];
680 /// InstAlias - This defines an alternate assembly syntax that is allowed to
681 /// match an instruction that has a different (more canonical) assembly
683 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
684 string AsmString = Asm; // The .s format to match the instruction with.
685 dag ResultInst = Result; // The MCInst to generate.
686 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
688 // Predicates - Predicates that must be true for this to match.
689 list<Predicate> Predicates = [];
692 //===----------------------------------------------------------------------===//
693 // AsmWriter - This class can be implemented by targets that need to customize
694 // the format of the .s file writer.
696 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
697 // on X86 for example).
700 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
701 // class. Generated AsmWriter classes are always prefixed with the target
703 string AsmWriterClassName = "AsmPrinter";
705 // Variant - AsmWriters can be of multiple different variants. Variants are
706 // used to support targets that need to emit assembly code in ways that are
707 // mostly the same for different targets, but have minor differences in
708 // syntax. If the asmstring contains {|} characters in them, this integer
709 // will specify which alternative to use. For example "{x|y|z}" with Variant
710 // == 1, will expand to "y".
714 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
715 // layout, the asmwriter can actually generate output in this columns (in
716 // verbose-asm mode). These two values indicate the width of the first column
717 // (the "opcode" area) and the width to reserve for subsequent operands. When
718 // verbose asm mode is enabled, operands will be indented to respect this.
719 int FirstOperandColumn = -1;
721 // OperandSpacing - Space between operand columns.
722 int OperandSpacing = -1;
724 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
725 // generation of the printInstruction() method. For MC printers, it takes
726 // an MCInstr* operand, otherwise it takes a MachineInstr*.
727 bit isMCAsmWriter = 0;
729 def DefaultAsmWriter : AsmWriter;
732 //===----------------------------------------------------------------------===//
733 // Target - This class contains the "global" target information
736 // InstructionSet - Instruction set description for this target.
737 InstrInfo InstructionSet;
739 // AssemblyParsers - The AsmParser instances available for this target.
740 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
742 // AssemblyWriters - The AsmWriter instances available for this target.
743 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
746 //===----------------------------------------------------------------------===//
747 // SubtargetFeature - A characteristic of the chip set.
749 class SubtargetFeature<string n, string a, string v, string d,
750 list<SubtargetFeature> i = []> {
751 // Name - Feature name. Used by command line (-mattr=) to determine the
752 // appropriate target chip.
756 // Attribute - Attribute to be set by feature.
758 string Attribute = a;
760 // Value - Value the attribute to be set to by feature.
764 // Desc - Feature description. Used by command line (-mattr=) to display help
769 // Implies - Features that this feature implies are present. If one of those
770 // features isn't set, then this one shouldn't be set either.
772 list<SubtargetFeature> Implies = i;
775 //===----------------------------------------------------------------------===//
776 // Processor chip sets - These values represent each of the chip sets supported
777 // by the scheduler. Each Processor definition requires corresponding
778 // instruction itineraries.
780 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
781 // Name - Chip set name. Used by command line (-mcpu=) to determine the
782 // appropriate target chip.
786 // ProcItin - The scheduling information for the target processor.
788 ProcessorItineraries ProcItin = pi;
790 // Features - list of
791 list<SubtargetFeature> Features = f;
794 //===----------------------------------------------------------------------===//
795 // Pull in the common support for calling conventions.
797 include "llvm/Target/TargetCallingConv.td"
799 //===----------------------------------------------------------------------===//
800 // Pull in the common support for DAG isel generation.
802 include "llvm/Target/TargetSelectionDAG.td"