1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
26 string Namespace = "";
29 // RegAltNameIndex - The alternate name set to use for register operands of
30 // this register class when printing.
31 class RegAltNameIndex {
32 string Namespace = "";
34 def NoRegAltName : RegAltNameIndex;
36 // Register - You should define one instance of this class for each register
37 // in the target machine. String n will become the "name" of the register.
38 class Register<string n, list<string> altNames = []> {
39 string Namespace = "";
41 list<string> AltNames = altNames;
43 // Aliases - A list of registers that this register overlaps with. A read or
44 // modification of this register can potentially read or modify the aliased
46 list<Register> Aliases = [];
48 // SubRegs - A list of registers that are parts of this register. Note these
49 // are "immediate" sub-registers and the registers within the list do not
50 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
52 list<Register> SubRegs = [];
54 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
55 // to address it. Sub-sub-register indices are automatically inherited from
57 list<SubRegIndex> SubRegIndices = [];
59 // RegAltNameIndices - The alternate name indices which are valid for this
61 list<RegAltNameIndex> RegAltNameIndices = [];
63 // CompositeIndices - Specify subreg indices that don't correspond directly to
64 // a register in SubRegs and are not inherited. The following formats are
67 // (a) Identity - Reg:a == Reg
68 // (a b) Alias - Reg:a == Reg:b
69 // (a b,c) Composite - Reg:a == (Reg:b):c
71 // This can be used to disambiguate a sub-sub-register that exists in more
72 // than one subregister and other weird stuff.
73 list<dag> CompositeIndices = [];
75 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
76 // These values can be determined by locating the <target>.h file in the
77 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
78 // order of these names correspond to the enumeration used by gcc. A value of
79 // -1 indicates that the gcc number is undefined and -2 that register number
80 // is invalid for this mode/flavour.
81 list<int> DwarfNumbers = [];
83 // CostPerUse - Additional cost of instructions using this register compared
84 // to other registers in its class. The register allocator will try to
85 // minimize the number of instructions using a register with a CostPerUse.
86 // This is used by the x86-64 and ARM Thumb targets where some registers
87 // require larger instruction encodings.
91 // RegisterWithSubRegs - This can be used to define instances of Register which
92 // need to specify sub-registers.
93 // List "subregs" specifies which registers are sub-registers to this one. This
94 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
95 // This allows the code generator to be careful not to put two values with
96 // overlapping live ranges into registers which alias.
97 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
98 let SubRegs = subregs;
101 // RegisterClass - Now that all of the registers are defined, and aliases
102 // between registers are defined, specify which registers belong to which
103 // register classes. This also defines the default allocation order of
104 // registers by register allocators.
106 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
107 dag regList, RegAltNameIndex idx = NoRegAltName> {
108 string Namespace = namespace;
110 // RegType - Specify the list ValueType of the registers in this register
111 // class. Note that all registers in a register class must have the same
112 // ValueTypes. This is a list because some targets permit storing different
113 // types in same register, for example vector values with 128-bit total size,
114 // but different count/size of items, like SSE on x86.
116 list<ValueType> RegTypes = regTypes;
118 // Size - Specify the spill size in bits of the registers. A default value of
119 // zero lets tablgen pick an appropriate size.
122 // Alignment - Specify the alignment required of the registers when they are
123 // stored or loaded to memory.
125 int Alignment = alignment;
127 // CopyCost - This value is used to specify the cost of copying a value
128 // between two registers in this register class. The default value is one
129 // meaning it takes a single instruction to perform the copying. A negative
130 // value means copying is extremely expensive or impossible.
133 // MemberList - Specify which registers are in this class. If the
134 // allocation_order_* method are not specified, this also defines the order of
135 // allocation used by the register allocator.
137 dag MemberList = regList;
139 // AltNameIndex - The alternate register name to use when printing operands
140 // of this register class. Every register in the register class must have
141 // a valid alternate name for the given index.
142 RegAltNameIndex altNameIndex = idx;
144 // SubRegClasses - Specify the register class of subregisters as a list of
145 // dags: (RegClass SubRegIndex, SubRegindex, ...)
146 list<dag> SubRegClasses = [];
148 // isAllocatable - Specify that the register class can be used for virtual
149 // registers and register allocation. Some register classes are only used to
150 // model instruction operand constraints, and should have isAllocatable = 0.
151 bit isAllocatable = 1;
153 // AltOrders - List of alternative allocation orders. The default order is
154 // MemberList itself, and that is good enough for most targets since the
155 // register allocators automatically remove reserved registers and move
156 // callee-saved registers to the end.
157 list<dag> AltOrders = [];
159 // AltOrderSelect - The body of a function that selects the allocation order
160 // to use in a given machine function. The code will be inserted in a
161 // function like this:
163 // static inline unsigned f(const MachineFunction &MF) { ... }
165 // The function should return 0 to select the default order defined by
166 // MemberList, 1 to select the first AltOrders entry and so on.
167 code AltOrderSelect = [{}];
170 // The memberList in a RegisterClass is a dag of set operations. TableGen
171 // evaluates these set operations and expand them into register lists. These
172 // are the most common operation, see test/TableGen/SetTheory.td for more
173 // examples of what is possible:
175 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
176 // register class, or a sub-expression. This is also the way to simply list
179 // (sub GPR, SP) - Set difference. Subtract the last arguments from the first.
181 // (and GPR, CSR) - Set intersection. All registers from the first set that are
182 // also in the second set.
184 // (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of
185 // numbered registers.
187 // (shl GPR, 4) - Remove the first N elements.
189 // (trunc GPR, 4) - Truncate after the first N elements.
191 // (rotl GPR, 1) - Rotate N places to the left.
193 // (rotr GPR, 1) - Rotate N places to the right.
195 // (decimate GPR, 2) - Pick every N'th element, starting with the first.
197 // All of these operators work on ordered sets, not lists. That means
198 // duplicates are removed from sub-expressions.
200 // Set operators. The rest is defined in TargetSelectionDAG.td.
204 // RegisterTuples - Automatically generate super-registers by forming tuples of
205 // sub-registers. This is useful for modeling register sequence constraints
206 // with pseudo-registers that are larger than the architectural registers.
208 // The sub-register lists are zipped together:
210 // def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>;
212 // Generates the same registers as:
214 // let SubRegIndices = [sube, subo] in {
215 // def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>;
216 // def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>;
219 // The generated pseudo-registers inherit super-classes and fields from their
220 // first sub-register. Most fields from the Register class are inferred, and
221 // the AsmName and Dwarf numbers are cleared.
223 // RegisterTuples instances can be used in other set operations to form
224 // register classes and so on. This is the only way of using the generated
226 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
227 // SubRegs - N lists of registers to be zipped up. Super-registers are
228 // synthesized from the first element of each SubRegs list, the second
229 // element and so on.
230 list<dag> SubRegs = Regs;
232 // SubRegIndices - N SubRegIndex instances. This provides the names of the
233 // sub-registers in the synthesized super-registers.
234 list<SubRegIndex> SubRegIndices = Indices;
236 // Compose sub-register indices like in a normal Register.
237 list<dag> CompositeIndices = [];
241 //===----------------------------------------------------------------------===//
242 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
243 // to the register numbering used by gcc and gdb. These values are used by a
244 // debug information writer to describe where values may be located during
246 class DwarfRegNum<list<int> Numbers> {
247 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
248 // These values can be determined by locating the <target>.h file in the
249 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
250 // order of these names correspond to the enumeration used by gcc. A value of
251 // -1 indicates that the gcc number is undefined and -2 that register number
252 // is invalid for this mode/flavour.
253 list<int> DwarfNumbers = Numbers;
256 // DwarfRegAlias - This class declares that a given register uses the same dwarf
257 // numbers as another one. This is useful for making it clear that the two
258 // registers do have the same number. It also lets us build a mapping
259 // from dwarf register number to llvm register.
260 class DwarfRegAlias<Register reg> {
261 Register DwarfAlias = reg;
264 //===----------------------------------------------------------------------===//
265 // Pull in the common support for scheduling
267 include "llvm/Target/TargetSchedule.td"
269 class Predicate; // Forward def
271 //===----------------------------------------------------------------------===//
272 // Instruction set description - These classes correspond to the C++ classes in
273 // the Target/TargetInstrInfo.h file.
276 string Namespace = "";
278 dag OutOperandList; // An dag containing the MI def operand list.
279 dag InOperandList; // An dag containing the MI use operand list.
280 string AsmString = ""; // The .s format to print the instruction with.
282 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
283 // otherwise, uninitialized.
286 // The follow state will eventually be inferred automatically from the
287 // instruction pattern.
289 list<Register> Uses = []; // Default to using no non-operand registers
290 list<Register> Defs = []; // Default to modifying no non-operand registers
292 // Predicates - List of predicates which will be turned into isel matching
294 list<Predicate> Predicates = [];
296 // Size - Size of encoded instruction, or zero if the size cannot be determined
300 // Code size, for instruction selection.
301 // FIXME: What does this actually mean?
304 // Added complexity passed onto matching pattern.
305 int AddedComplexity = 0;
307 // These bits capture information about the high-level semantics of the
309 bit isReturn = 0; // Is this instruction a return instruction?
310 bit isBranch = 0; // Is this instruction a branch instruction?
311 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
312 bit isCompare = 0; // Is this instruction a comparison instruction?
313 bit isMoveImm = 0; // Is this instruction a move immediate instruction?
314 bit isBitcast = 0; // Is this instruction a bitcast instruction?
315 bit isBarrier = 0; // Can control flow fall through this instruction?
316 bit isCall = 0; // Is this instruction a call instruction?
317 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
318 bit mayLoad = 0; // Is it possible for this inst to read memory?
319 bit mayStore = 0; // Is it possible for this inst to write memory?
320 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
321 bit isCommutable = 0; // Is this 3 operand instruction commutable?
322 bit isTerminator = 0; // Is this part of the terminator for a basic block?
323 bit isReMaterializable = 0; // Is this instruction re-materializable?
324 bit isPredicable = 0; // Is this instruction predicable?
325 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
326 bit usesCustomInserter = 0; // Pseudo instr needing special help.
327 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
328 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
329 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
330 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
331 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
332 bit isPseudo = 0; // Is this instruction a pseudo-instruction?
333 // If so, won't have encoding information for
334 // the [MC]CodeEmitter stuff.
336 // Side effect flags - When set, the flags have these meanings:
338 // hasSideEffects - The instruction has side effects that are not
339 // captured by any operands of the instruction or other flags.
341 // neverHasSideEffects - Set on an instruction with no pattern if it has no
343 bit hasSideEffects = 0;
344 bit neverHasSideEffects = 0;
346 // Is this instruction a "real" instruction (with a distinct machine
347 // encoding), or is it a pseudo instruction used for codegen modeling
349 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only
350 // instructions can (and often do) still have encoding information
351 // associated with them. Once we've migrated all of them over to true
352 // pseudo-instructions that are lowered to real instructions prior to
353 // the printer/emitter, we can remove this attribute and just use isPseudo.
354 bit isCodeGenOnly = 0;
356 // Is this instruction a pseudo instruction for use by the assembler parser.
357 bit isAsmParserOnly = 0;
359 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
361 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
363 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
364 /// be encoded into the output machineinstr.
365 string DisableEncoding = "";
367 string PostEncoderMethod = "";
368 string DecoderMethod = "";
370 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
371 bits<64> TSFlags = 0;
373 ///@name Assembler Parser Support
376 string AsmMatchConverter = "";
381 /// PseudoInstExpansion - Expansion information for a pseudo-instruction.
382 /// Which instruction it expands to and how the operands map from the
384 class PseudoInstExpansion<dag Result> {
385 dag ResultInst = Result; // The instruction to generate.
389 /// Predicates - These are extra conditionals which are turned into instruction
390 /// selector matching code. Currently each predicate is just a string.
391 class Predicate<string cond> {
392 string CondString = cond;
394 /// AssemblerMatcherPredicate - If this feature can be used by the assembler
395 /// matcher, this is true. Targets should set this by inheriting their
396 /// feature from the AssemblerPredicate class in addition to Predicate.
397 bit AssemblerMatcherPredicate = 0;
399 /// AssemblerCondString - Name of the subtarget feature being tested used
400 /// as alternative condition string used for assembler matcher.
401 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0".
402 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0".
403 /// It can also list multiple features separated by ",".
404 /// e.g. "ModeThumb,FeatureThumb2" is translated to
405 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
406 string AssemblerCondString = "";
409 /// NoHonorSignDependentRounding - This predicate is true if support for
410 /// sign-dependent-rounding is not enabled.
411 def NoHonorSignDependentRounding
412 : Predicate<"!HonorSignDependentRoundingFPMath()">;
414 class Requires<list<Predicate> preds> {
415 list<Predicate> Predicates = preds;
418 /// ops definition - This is just a simple marker used to identify the operand
419 /// list for an instruction. outs and ins are identical both syntactically and
420 /// semanticallyr; they are used to define def operands and use operands to
421 /// improve readibility. This should be used like this:
422 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
427 /// variable_ops definition - Mark this instruction as taking a variable number
432 /// PointerLikeRegClass - Values that are designed to have pointer width are
433 /// derived from this. TableGen treats the register class as having a symbolic
434 /// type that it doesn't know, and resolves the actual regclass to use by using
435 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
436 class PointerLikeRegClass<int Kind> {
437 int RegClassKind = Kind;
441 /// ptr_rc definition - Mark this operand as being a pointer value whose
442 /// register class is resolved dynamically via a callback to TargetInstrInfo.
443 /// FIXME: We should probably change this to a class which contain a list of
444 /// flags. But currently we have but one flag.
445 def ptr_rc : PointerLikeRegClass<0>;
447 /// unknown definition - Mark this operand as being of unknown type, causing
448 /// it to be resolved by inference in the context it is used.
451 /// AsmOperandClass - Representation for the kinds of operands which the target
452 /// specific parser can create and the assembly matcher may need to distinguish.
454 /// Operand classes are used to define the order in which instructions are
455 /// matched, to ensure that the instruction which gets matched for any
456 /// particular list of operands is deterministic.
458 /// The target specific parser must be able to classify a parsed operand into a
459 /// unique class which does not partially overlap with any other classes. It can
460 /// match a subset of some other class, in which case the super class field
461 /// should be defined.
462 class AsmOperandClass {
463 /// The name to use for this class, which should be usable as an enum value.
466 /// The super classes of this operand.
467 list<AsmOperandClass> SuperClasses = [];
469 /// The name of the method on the target specific operand to call to test
470 /// whether the operand is an instance of this class. If not set, this will
471 /// default to "isFoo", where Foo is the AsmOperandClass name. The method
472 /// signature should be:
473 /// bool isFoo() const;
474 string PredicateMethod = ?;
476 /// The name of the method on the target specific operand to call to add the
477 /// target specific operand to an MCInst. If not set, this will default to
478 /// "addFooOperands", where Foo is the AsmOperandClass name. The method
479 /// signature should be:
480 /// void addFooOperands(MCInst &Inst, unsigned N) const;
481 string RenderMethod = ?;
483 /// The name of the method on the target specific operand to call to custom
484 /// handle the operand parsing. This is useful when the operands do not relate
485 /// to immediates or registers and are very instruction specific (as flags to
486 /// set in a processor register, coprocessor number, ...).
487 string ParserMethod = ?;
490 def ImmAsmOperand : AsmOperandClass {
494 /// Operand Types - These provide the built-in operand types that may be used
495 /// by a target. Targets can optionally provide their own operand types as
496 /// needed, though this should not be needed for RISC targets.
497 class Operand<ValueType ty> {
499 string PrintMethod = "printOperand";
500 string EncoderMethod = "";
501 string DecoderMethod = "";
502 string AsmOperandLowerMethod = ?;
503 dag MIOperandInfo = (ops);
505 // ParserMatchClass - The "match class" that operands of this type fit
506 // in. Match classes are used to define the order in which instructions are
507 // match, to ensure that which instructions gets matched is deterministic.
509 // The target specific parser must be able to classify an parsed operand into
510 // a unique class, which does not partially overlap with any other classes. It
511 // can match a subset of some other class, in which case the AsmOperandClass
512 // should declare the other operand as one of its super classes.
513 AsmOperandClass ParserMatchClass = ImmAsmOperand;
516 class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> {
517 // RegClass - The register class of the operand.
518 RegisterClass RegClass = regclass;
519 // PrintMethod - The target method to call to print register operands of
520 // this type. The method normally will just use an alt-name index to look
521 // up the name to print. Default to the generic printOperand().
522 string PrintMethod = pm;
523 // ParserMatchClass - The "match class" that operands of this type fit
524 // in. Match classes are used to define the order in which instructions are
525 // match, to ensure that which instructions gets matched is deterministic.
527 // The target specific parser must be able to classify an parsed operand into
528 // a unique class, which does not partially overlap with any other classes. It
529 // can match a subset of some other class, in which case the AsmOperandClass
530 // should declare the other operand as one of its super classes.
531 AsmOperandClass ParserMatchClass;
534 def i1imm : Operand<i1>;
535 def i8imm : Operand<i8>;
536 def i16imm : Operand<i16>;
537 def i32imm : Operand<i32>;
538 def i64imm : Operand<i64>;
540 def f32imm : Operand<f32>;
541 def f64imm : Operand<f64>;
543 /// zero_reg definition - Special node to stand for the zero register.
547 /// PredicateOperand - This can be used to define a predicate operand for an
548 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
549 /// AlwaysVal specifies the value of this predicate when set to "always
551 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
553 let MIOperandInfo = OpTypes;
554 dag DefaultOps = AlwaysVal;
557 /// OptionalDefOperand - This is used to define a optional definition operand
558 /// for an instruction. DefaultOps is the register the operand represents if
559 /// none is supplied, e.g. zero_reg.
560 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
562 let MIOperandInfo = OpTypes;
563 dag DefaultOps = defaultops;
567 // InstrInfo - This class should only be instantiated once to provide parameters
568 // which are global to the target machine.
571 // Target can specify its instructions in either big or little-endian formats.
572 // For instance, while both Sparc and PowerPC are big-endian platforms, the
573 // Sparc manual specifies its instructions in the format [31..0] (big), while
574 // PowerPC specifies them using the format [0..31] (little).
575 bit isLittleEndianEncoding = 0;
578 // Standard Pseudo Instructions.
579 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
580 // Only these instructions are allowed in the TargetOpcode namespace.
581 let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
582 def PHI : Instruction {
583 let OutOperandList = (outs);
584 let InOperandList = (ins variable_ops);
585 let AsmString = "PHINODE";
587 def INLINEASM : Instruction {
588 let OutOperandList = (outs);
589 let InOperandList = (ins variable_ops);
591 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
593 def PROLOG_LABEL : Instruction {
594 let OutOperandList = (outs);
595 let InOperandList = (ins i32imm:$id);
598 let isNotDuplicable = 1;
600 def EH_LABEL : Instruction {
601 let OutOperandList = (outs);
602 let InOperandList = (ins i32imm:$id);
605 let isNotDuplicable = 1;
607 def GC_LABEL : Instruction {
608 let OutOperandList = (outs);
609 let InOperandList = (ins i32imm:$id);
612 let isNotDuplicable = 1;
614 def KILL : Instruction {
615 let OutOperandList = (outs);
616 let InOperandList = (ins variable_ops);
618 let neverHasSideEffects = 1;
620 def EXTRACT_SUBREG : Instruction {
621 let OutOperandList = (outs unknown:$dst);
622 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
624 let neverHasSideEffects = 1;
626 def INSERT_SUBREG : Instruction {
627 let OutOperandList = (outs unknown:$dst);
628 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
630 let neverHasSideEffects = 1;
631 let Constraints = "$supersrc = $dst";
633 def IMPLICIT_DEF : Instruction {
634 let OutOperandList = (outs unknown:$dst);
635 let InOperandList = (ins);
637 let neverHasSideEffects = 1;
638 let isReMaterializable = 1;
639 let isAsCheapAsAMove = 1;
641 def SUBREG_TO_REG : Instruction {
642 let OutOperandList = (outs unknown:$dst);
643 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
645 let neverHasSideEffects = 1;
647 def COPY_TO_REGCLASS : Instruction {
648 let OutOperandList = (outs unknown:$dst);
649 let InOperandList = (ins unknown:$src, i32imm:$regclass);
651 let neverHasSideEffects = 1;
652 let isAsCheapAsAMove = 1;
654 def DBG_VALUE : Instruction {
655 let OutOperandList = (outs);
656 let InOperandList = (ins variable_ops);
657 let AsmString = "DBG_VALUE";
658 let neverHasSideEffects = 1;
660 def REG_SEQUENCE : Instruction {
661 let OutOperandList = (outs unknown:$dst);
662 let InOperandList = (ins variable_ops);
664 let neverHasSideEffects = 1;
665 let isAsCheapAsAMove = 1;
667 def COPY : Instruction {
668 let OutOperandList = (outs unknown:$dst);
669 let InOperandList = (ins unknown:$src);
671 let neverHasSideEffects = 1;
672 let isAsCheapAsAMove = 1;
676 //===----------------------------------------------------------------------===//
677 // AsmParser - This class can be implemented by targets that wish to implement
680 // Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel
681 // syntax on X86 for example).
684 // AsmParserClassName - This specifies the suffix to use for the asmparser
685 // class. Generated AsmParser classes are always prefixed with the target
687 string AsmParserClassName = "AsmParser";
689 // AsmParserInstCleanup - If non-empty, this is the name of a custom member
690 // function of the AsmParser class to call on every matched instruction.
691 // This can be used to perform target specific instruction post-processing.
692 string AsmParserInstCleanup = "";
694 // Variant - AsmParsers can be of multiple different variants. Variants are
695 // used to support targets that need to parser multiple formats for the
696 // assembly language.
699 // CommentDelimiter - If given, the delimiter string used to recognize
700 // comments which are hard coded in the .td assembler strings for individual
702 string CommentDelimiter = "";
704 // RegisterPrefix - If given, the token prefix which indicates a register
705 // token. This is used by the matcher to automatically recognize hard coded
706 // register tokens as constrained registers, instead of tokens, for the
707 // purposes of matching.
708 string RegisterPrefix = "";
710 def DefaultAsmParser : AsmParser;
712 /// AssemblerPredicate - This is a Predicate that can be used when the assembler
713 /// matches instructions and aliases.
714 class AssemblerPredicate<string cond> {
715 bit AssemblerMatcherPredicate = 1;
716 string AssemblerCondString = cond;
721 /// MnemonicAlias - This class allows targets to define assembler mnemonic
722 /// aliases. This should be used when all forms of one mnemonic are accepted
723 /// with a different mnemonic. For example, X86 allows:
724 /// sal %al, 1 -> shl %al, 1
725 /// sal %ax, %cl -> shl %ax, %cl
726 /// sal %eax, %cl -> shl %eax, %cl
727 /// etc. Though "sal" is accepted with many forms, all of them are directly
728 /// translated to a shl, so it can be handled with (in the case of X86, it
729 /// actually has one for each suffix as well):
730 /// def : MnemonicAlias<"sal", "shl">;
732 /// Mnemonic aliases are mapped before any other translation in the match phase,
733 /// and do allow Requires predicates, e.g.:
735 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
736 /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>;
738 class MnemonicAlias<string From, string To> {
739 string FromMnemonic = From;
740 string ToMnemonic = To;
742 // Predicates - Predicates that must be true for this remapping to happen.
743 list<Predicate> Predicates = [];
746 /// InstAlias - This defines an alternate assembly syntax that is allowed to
747 /// match an instruction that has a different (more canonical) assembly
749 class InstAlias<string Asm, dag Result, bit Emit = 0b1> {
750 string AsmString = Asm; // The .s format to match the instruction with.
751 dag ResultInst = Result; // The MCInst to generate.
752 bit EmitAlias = Emit; // Emit the alias instead of what's aliased.
754 // Predicates - Predicates that must be true for this to match.
755 list<Predicate> Predicates = [];
758 //===----------------------------------------------------------------------===//
759 // AsmWriter - This class can be implemented by targets that need to customize
760 // the format of the .s file writer.
762 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
763 // on X86 for example).
766 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
767 // class. Generated AsmWriter classes are always prefixed with the target
769 string AsmWriterClassName = "AsmPrinter";
771 // Variant - AsmWriters can be of multiple different variants. Variants are
772 // used to support targets that need to emit assembly code in ways that are
773 // mostly the same for different targets, but have minor differences in
774 // syntax. If the asmstring contains {|} characters in them, this integer
775 // will specify which alternative to use. For example "{x|y|z}" with Variant
776 // == 1, will expand to "y".
780 // FirstOperandColumn/OperandSpacing - If the assembler syntax uses a columnar
781 // layout, the asmwriter can actually generate output in this columns (in
782 // verbose-asm mode). These two values indicate the width of the first column
783 // (the "opcode" area) and the width to reserve for subsequent operands. When
784 // verbose asm mode is enabled, operands will be indented to respect this.
785 int FirstOperandColumn = -1;
787 // OperandSpacing - Space between operand columns.
788 int OperandSpacing = -1;
790 // isMCAsmWriter - Is this assembly writer for an MC emitter? This controls
791 // generation of the printInstruction() method. For MC printers, it takes
792 // an MCInstr* operand, otherwise it takes a MachineInstr*.
793 bit isMCAsmWriter = 0;
795 def DefaultAsmWriter : AsmWriter;
798 //===----------------------------------------------------------------------===//
799 // Target - This class contains the "global" target information
802 // InstructionSet - Instruction set description for this target.
803 InstrInfo InstructionSet;
805 // AssemblyParsers - The AsmParser instances available for this target.
806 list<AsmParser> AssemblyParsers = [DefaultAsmParser];
808 // AssemblyWriters - The AsmWriter instances available for this target.
809 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
812 //===----------------------------------------------------------------------===//
813 // SubtargetFeature - A characteristic of the chip set.
815 class SubtargetFeature<string n, string a, string v, string d,
816 list<SubtargetFeature> i = []> {
817 // Name - Feature name. Used by command line (-mattr=) to determine the
818 // appropriate target chip.
822 // Attribute - Attribute to be set by feature.
824 string Attribute = a;
826 // Value - Value the attribute to be set to by feature.
830 // Desc - Feature description. Used by command line (-mattr=) to display help
835 // Implies - Features that this feature implies are present. If one of those
836 // features isn't set, then this one shouldn't be set either.
838 list<SubtargetFeature> Implies = i;
841 //===----------------------------------------------------------------------===//
842 // Processor chip sets - These values represent each of the chip sets supported
843 // by the scheduler. Each Processor definition requires corresponding
844 // instruction itineraries.
846 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
847 // Name - Chip set name. Used by command line (-mcpu=) to determine the
848 // appropriate target chip.
852 // ProcItin - The scheduling information for the target processor.
854 ProcessorItineraries ProcItin = pi;
856 // Features - list of
857 list<SubtargetFeature> Features = f;
860 //===----------------------------------------------------------------------===//
861 // Pull in the common support for calling conventions.
863 include "llvm/Target/TargetCallingConv.td"
865 //===----------------------------------------------------------------------===//
866 // Pull in the common support for DAG isel generation.
868 include "llvm/Target/TargetSelectionDAG.td"