1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
43 /// The SuperRegs field is a zero terminated array of registers that are
44 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
47 struct TargetRegisterDesc {
48 const char *Name; // Assembly language name for the register
49 const unsigned *AliasSet; // Register Alias Set, described above
50 const unsigned *SubRegs; // Sub-register set, described above
51 const unsigned *SuperRegs; // Super-register set, described above
54 class TargetRegisterClass {
56 typedef const unsigned* iterator;
57 typedef const unsigned* const_iterator;
59 typedef const MVT::ValueType* vt_iterator;
60 typedef const TargetRegisterClass* const * sc_iterator;
64 const vt_iterator VTs;
65 const sc_iterator SubClasses;
66 const sc_iterator SuperClasses;
67 const sc_iterator SubRegClasses;
68 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
69 const iterator RegsBegin, RegsEnd;
71 TargetRegisterClass(unsigned id,
72 const MVT::ValueType *vts,
73 const TargetRegisterClass * const *subcs,
74 const TargetRegisterClass * const *supcs,
75 const TargetRegisterClass * const *subregcs,
76 unsigned RS, unsigned Al, iterator RB, iterator RE)
77 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
78 SubRegClasses(subregcs),
79 RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
80 virtual ~TargetRegisterClass() {} // Allow subclasses
82 /// getID() - Return the register class ID number.
84 unsigned getID() const { return ID; }
86 /// begin/end - Return all of the registers in this class.
88 iterator begin() const { return RegsBegin; }
89 iterator end() const { return RegsEnd; }
91 /// getNumRegs - Return the number of registers in this class.
93 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
95 /// getRegister - Return the specified register in the class.
97 unsigned getRegister(unsigned i) const {
98 assert(i < getNumRegs() && "Register number out of range!");
102 /// contains - Return true if the specified register is included in this
104 bool contains(unsigned Reg) const {
105 for (iterator I = begin(), E = end(); I != E; ++I)
106 if (*I == Reg) return true;
110 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
112 bool hasType(MVT::ValueType vt) const {
113 for(int i = 0; VTs[i] != MVT::Other; ++i)
119 /// vt_begin / vt_end - Loop over all of the value types that can be
120 /// represented by values in this register class.
121 vt_iterator vt_begin() const {
125 vt_iterator vt_end() const {
127 while (*I != MVT::Other) ++I;
131 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
132 /// sub-register class of this TargetRegisterClass.
133 bool hasSubRegClass(const TargetRegisterClass *cs) const {
134 for (int i = 0; SubClasses[i] != NULL; ++i)
135 if (SubClasses[i] == cs)
140 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
141 /// this register class.
142 sc_iterator subclasses_begin() const {
146 sc_iterator subclasses_end() const {
147 sc_iterator I = SubClasses;
148 while (*I != NULL) ++I;
152 /// hasSuperRegClass - return true if the specified TargetRegisterClass is a
153 /// super-register class of this TargetRegisterClass.
154 bool hasSuperRegClass(const TargetRegisterClass *cs) const {
155 for (int i = 0; SuperClasses[i] != NULL; ++i)
156 if (SuperClasses[i] == cs)
161 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
162 /// of this register class.
163 sc_iterator superclasses_begin() const {
167 sc_iterator superclasses_end() const {
168 sc_iterator I = SuperClasses;
169 while (*I != NULL) ++I;
173 /// hasSubRegForClass - return true if the specified TargetRegisterClass is a
174 /// class of a sub-register class for this TargetRegisterClass.
175 bool hasSubRegForClass(const TargetRegisterClass *cs) const {
176 for (int i = 0; SubRegClasses[i] != NULL; ++i)
177 if (SubRegClasses[i] == cs)
182 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
183 /// class of a sub-register class for this TargetRegisterClass.
184 bool hasClassForSubReg(unsigned SubReg) const {
186 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
192 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
193 /// at idx for this TargetRegisterClass.
194 sc_iterator getClassForSubReg(unsigned SubReg) const {
196 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
198 return &SubRegClasses[i];
202 /// subregclasses_begin / subregclasses_end - Loop over all of
203 /// the subregister classes of this register class.
204 sc_iterator subregclasses_begin() const {
205 return SubRegClasses;
208 sc_iterator subregclasses_end() const {
209 sc_iterator I = SubRegClasses;
210 while (*I != NULL) ++I;
214 /// allocation_order_begin/end - These methods define a range of registers
215 /// which specify the registers in this class that are valid to register
216 /// allocate, and the preferred order to allocate them in. For example,
217 /// callee saved registers should be at the end of the list, because it is
218 /// cheaper to allocate caller saved registers.
220 /// These methods take a MachineFunction argument, which can be used to tune
221 /// the allocatable registers based on the characteristics of the function.
222 /// One simple example is that the frame pointer register can be used if
223 /// frame-pointer-elimination is performed.
225 /// By default, these methods return all registers in the class.
227 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
230 virtual iterator allocation_order_end(const MachineFunction &MF) const {
236 /// getSize - Return the size of the register in bytes, which is also the size
237 /// of a stack slot allocated to hold a spilled copy of this register.
238 unsigned getSize() const { return RegSize; }
240 /// getAlignment - Return the minimum required alignment for a register of
242 unsigned getAlignment() const { return Alignment; }
246 /// MRegisterInfo base class - We assume that the target defines a static array
247 /// of TargetRegisterDesc objects that represent all of the machine registers
248 /// that the target has. As such, we simply have to track a pointer to this
249 /// array so that we can turn register number into a register descriptor.
251 class MRegisterInfo {
253 typedef const TargetRegisterClass * const * regclass_iterator;
255 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
256 unsigned NumRegs; // Number of entries in the array
258 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
260 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
262 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
263 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
264 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
265 virtual ~MRegisterInfo();
268 enum { // Define some target independent constants
269 /// NoRegister - This physical register is not a real target register. It
270 /// is useful as a sentinal.
273 /// FirstVirtualRegister - This is the first register number that is
274 /// considered to be a 'virtual' register, which is part of the SSA
275 /// namespace. This must be the same for all targets, which means that each
276 /// target is limited to 1024 registers.
277 FirstVirtualRegister = 1024
280 /// isPhysicalRegister - Return true if the specified register number is in
281 /// the physical register namespace.
282 static bool isPhysicalRegister(unsigned Reg) {
283 assert(Reg && "this is not a register!");
284 return Reg < FirstVirtualRegister;
287 /// isVirtualRegister - Return true if the specified register number is in
288 /// the virtual register namespace.
289 static bool isVirtualRegister(unsigned Reg) {
290 assert(Reg && "this is not a register!");
291 return Reg >= FirstVirtualRegister;
294 /// getAllocatableSet - Returns a bitset indexed by register number
295 /// indicating if a register is allocatable or not. If a register class is
296 /// specified, returns the subset for the class.
297 BitVector getAllocatableSet(MachineFunction &MF,
298 const TargetRegisterClass *RC = NULL) const;
300 const TargetRegisterDesc &operator[](unsigned RegNo) const {
301 assert(RegNo < NumRegs &&
302 "Attempting to access record for invalid register number!");
306 /// Provide a get method, equivalent to [], but more useful if we have a
307 /// pointer to this object.
309 const TargetRegisterDesc &get(unsigned RegNo) const {
310 return operator[](RegNo);
313 /// getAliasSet - Return the set of registers aliased by the specified
314 /// register, or a null list of there are none. The list returned is zero
317 const unsigned *getAliasSet(unsigned RegNo) const {
318 return get(RegNo).AliasSet;
321 /// getSubRegisters - Return the set of registers that are sub-registers of
322 /// the specified register, or a null list of there are none. The list
323 /// returned is zero terminated.
325 const unsigned *getSubRegisters(unsigned RegNo) const {
326 return get(RegNo).SubRegs;
329 /// getSuperRegisters - Return the set of registers that are super-registers
330 /// of the specified register, or a null list of there are none. The list
331 /// returned is zero terminated.
333 const unsigned *getSuperRegisters(unsigned RegNo) const {
334 return get(RegNo).SuperRegs;
337 /// getName - Return the symbolic target specific name for the specified
338 /// physical register.
339 const char *getName(unsigned RegNo) const {
340 return get(RegNo).Name;
343 /// getNumRegs - Return the number of registers this target has
344 /// (useful for sizing arrays holding per register information)
345 unsigned getNumRegs() const {
349 /// areAliases - Returns true if the two registers alias each other,
351 bool areAliases(unsigned regA, unsigned regB) const {
352 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
353 if (*Alias == regB) return true;
357 /// regsOverlap - Returns true if the two registers are equal or alias
358 /// each other. The registers may be virtual register.
359 bool regsOverlap(unsigned regA, unsigned regB) const {
363 if (isVirtualRegister(regA) || isVirtualRegister(regB))
365 return areAliases(regA, regB);
368 /// isSubRegister - Returns true if regB is a sub-register of regA.
370 bool isSubRegister(unsigned regA, unsigned regB) const {
371 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
372 if (*SR == regB) return true;
376 /// isSuperRegister - Returns true if regB is a super-register of regA.
378 bool isSuperRegister(unsigned regA, unsigned regB) const {
379 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
380 if (*SR == regB) return true;
384 /// getCalleeSavedRegs - Return a null-terminated list of all of the
385 /// callee saved registers on this target. The register should be in the
386 /// order of desired callee-save stack frame offset. The first register is
387 /// closed to the incoming stack pointer if stack grows down, and vice versa.
388 virtual const unsigned* getCalleeSavedRegs() const = 0;
390 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
391 /// register classes to spill each callee saved register with. The order and
392 /// length of this list match the getCalleeSaveRegs() list.
393 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses() const =0;
395 /// getReservedRegs - Returns a bitset indexed by physical register number
396 /// indicating if a register is a special register that has particular uses and
397 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
398 /// register scavenger to determine what registers are free.
399 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
401 /// getSubReg - Returns the physical register number of sub-register "Index"
402 /// for physical register RegNo.
403 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
405 //===--------------------------------------------------------------------===//
406 // Register Class Information
409 /// Register class iterators
411 regclass_iterator regclass_begin() const { return RegClassBegin; }
412 regclass_iterator regclass_end() const { return RegClassEnd; }
414 unsigned getNumRegClasses() const {
415 return regclass_end()-regclass_begin();
418 /// getRegClass - Returns the register class associated with the enumeration
419 /// value. See class TargetOperandInfo.
420 const TargetRegisterClass *getRegClass(unsigned i) const {
421 assert(i <= getNumRegClasses() && "Register Class ID out of range");
422 return i ? RegClassBegin[i - 1] : NULL;
425 //===--------------------------------------------------------------------===//
426 // Interfaces used by the register allocator and stack frame
427 // manipulation passes to move data around between registers,
428 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
431 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
432 /// registers and returns true if it isn't possible / profitable to do so by
433 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
435 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
436 MachineBasicBlock::iterator MI,
437 const std::vector<CalleeSavedInfo> &CSI) const {
441 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
442 /// saved registers and returns true if it isn't possible / profitable to do
443 /// so by issuing a series of load instructions via loadRegToStackSlot().
444 /// Returns false otherwise.
445 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator MI,
447 const std::vector<CalleeSavedInfo> &CSI) const {
451 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
452 MachineBasicBlock::iterator MI,
453 unsigned SrcReg, int FrameIndex,
454 const TargetRegisterClass *RC) const = 0;
456 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator MI,
458 unsigned DestReg, int FrameIndex,
459 const TargetRegisterClass *RC) const = 0;
461 virtual void copyRegToReg(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator MI,
463 unsigned DestReg, unsigned SrcReg,
464 const TargetRegisterClass *RC) const = 0;
466 /// reMaterialize - Re-issue the specified 'original' instruction at the
467 /// specific location targeting a new destination register.
468 virtual void reMaterialize(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator MI,
471 const MachineInstr *Orig) const = 0;
473 /// foldMemoryOperand - Attempt to fold a load or store of the
474 /// specified stack slot into the specified machine instruction for
475 /// the specified operand. If this is possible, a new instruction
476 /// is returned with the specified operand folded, otherwise NULL is
477 /// returned. The client is responsible for removing the old
478 /// instruction and adding the new one in the instruction stream
479 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
481 int FrameIndex) const {
485 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
486 /// for rounding up the stack frame (probably at emitPrologue time).
487 virtual bool targetHandlesStackFrameRounding() const {
491 /// requiresRegisterScavenging - returns true if the target requires (and
492 /// can make use of) the register scavenger.
493 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
497 /// hasFP - Return true if the specified function should have a dedicated frame
498 /// pointer register. For most targets this is true only if the function has
499 /// variable sized allocas or if frame pointer elimination is disabled.
500 virtual bool hasFP(const MachineFunction &MF) const = 0;
502 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
503 // not required, we reserve argument space for call sites in the function
504 // immediately on entry to the current function. This eliminates the need for
505 // add/sub sp brackets around call sites. Returns true if the call frame is
506 // included as part of the stack frame.
507 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
511 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
512 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
513 /// targets use pseudo instructions in order to abstract away the difference
514 /// between operating with a frame pointer and operating without, through the
515 /// use of these two instructions.
517 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
518 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
521 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
522 /// code insertion to eliminate call frame setup and destroy pseudo
523 /// instructions (but only if the Target is using them). It is responsible
524 /// for eliminating these instructions, replacing them with concrete
525 /// instructions. This method need only be implemented if using call frame
526 /// setup/destroy pseudo instructions.
529 eliminateCallFramePseudoInstr(MachineFunction &MF,
530 MachineBasicBlock &MBB,
531 MachineBasicBlock::iterator MI) const {
532 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
533 "eliminateCallFramePseudoInstr must be implemented if using"
534 " call frame setup/destroy pseudo instructions!");
535 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
538 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
539 /// before PrologEpilogInserter scans the physical registers used to determine
540 /// what callee saved registers should be spilled. This method is optional.
541 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
542 RegScavenger *RS = NULL) const {
546 /// processFunctionBeforeFrameFinalized - This method is called immediately
547 /// before the specified functions frame layout (MF.getFrameInfo()) is
548 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
549 /// replaced with direct constants. This method is optional.
551 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
554 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
555 /// frame indices from instructions which may use them. The instruction
556 /// referenced by the iterator contains an MO_FrameIndex operand which must be
557 /// eliminated by this method. This method may modify or replace the
558 /// specified instruction, as long as it keeps the iterator pointing the the
559 /// finished product. SPAdj is the SP adjustment due to call frame setup
560 /// instruction. The return value is the number of instructions added to
561 /// (negative if removed from) the basic block.
563 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
564 int SPAdj, RegScavenger *RS=NULL) const = 0;
566 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
567 /// the function. The return value is the number of instructions
568 /// added to (negative if removed from) the basic block (entry for prologue).
570 virtual void emitPrologue(MachineFunction &MF) const = 0;
571 virtual void emitEpilogue(MachineFunction &MF,
572 MachineBasicBlock &MBB) const = 0;
574 //===--------------------------------------------------------------------===//
575 /// Debug information queries.
577 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
578 /// number. Returns -1 if there is no equivalent value.
579 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
581 /// getFrameRegister - This method should return the register used as a base
582 /// for values allocated in the current stack frame.
583 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
585 /// getRARegister - This method should return the register where the return
586 /// address can be found.
587 virtual unsigned getRARegister() const = 0;
589 /// getLocation - This method should return the actual location of a frame
590 /// variable given the frame index. The location is returned in ML.
591 /// Subclasses should override this method for special handling of frame
592 /// variables and call MRegisterInfo::getLocation for the default action.
593 virtual void getLocation(MachineFunction &MF, unsigned Index,
594 MachineLocation &ML) const;
596 /// getInitialFrameState - Returns a list of machine moves that are assumed
597 /// on entry to all functions. Note that LabelID is ignored (assumed to be
598 /// the beginning of the function.)
599 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
602 // This is useful when building IndexedMaps keyed on virtual registers
603 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
604 unsigned operator()(unsigned Reg) const {
605 return Reg - MRegisterInfo::FirstVirtualRegister;
609 } // End llvm namespace