1 //===- Target/MRegisterInfo.h - Target Register Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_MREGISTERINFO_H
17 #define LLVM_TARGET_MREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class CalleeSavedInfo;
28 class MachineFunction;
30 class MachineLocation;
33 class TargetRegisterClass;
36 /// TargetRegisterDesc - This record contains all of the information known about
37 /// a particular register. The AliasSet field (if not null) contains a pointer
38 /// to a Zero terminated array of registers that this register aliases. This is
39 /// needed for architectures like X86 which have AL alias AX alias EAX.
40 /// Registers that this does not apply to simply should set this to null.
41 /// The SubRegs field is a zero terminated array of registers that are
42 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
43 /// The ImmsubRegs field is a subset of SubRegs. It includes only the immediate
44 /// sub-registers. e.g. EAX has only one immediate sub-register of AX, not AH,
45 /// AL which are immediate sub-registers of AX. The SuperRegs field is a zero
46 /// terminated array of registers that are super-registers of the specific
47 /// register, e.g. RAX, EAX, are super-registers of AX.
49 struct TargetRegisterDesc {
50 const char *Name; // Assembly language name for the register
51 const unsigned *AliasSet; // Register Alias Set, described above
52 const unsigned *SubRegs; // Sub-register set, described above
53 const unsigned *ImmSubRegs; // Immediate sub-register set, described above
54 const unsigned *SuperRegs; // Super-register set, described above
57 class TargetRegisterClass {
59 typedef const unsigned* iterator;
60 typedef const unsigned* const_iterator;
62 typedef const MVT::ValueType* vt_iterator;
63 typedef const TargetRegisterClass* const * sc_iterator;
67 const vt_iterator VTs;
68 const sc_iterator SubClasses;
69 const sc_iterator SuperClasses;
70 const sc_iterator SubRegClasses;
71 const sc_iterator SuperRegClasses;
72 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
74 const iterator RegsBegin, RegsEnd;
76 TargetRegisterClass(unsigned id,
77 const MVT::ValueType *vts,
78 const TargetRegisterClass * const *subcs,
79 const TargetRegisterClass * const *supcs,
80 const TargetRegisterClass * const *subregcs,
81 const TargetRegisterClass * const *superregcs,
82 unsigned RS, unsigned Al, int CC,
83 iterator RB, iterator RE)
84 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
85 SubRegClasses(subregcs), SuperRegClasses(superregcs),
86 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
87 virtual ~TargetRegisterClass() {} // Allow subclasses
89 /// getID() - Return the register class ID number.
91 unsigned getID() const { return ID; }
93 /// begin/end - Return all of the registers in this class.
95 iterator begin() const { return RegsBegin; }
96 iterator end() const { return RegsEnd; }
98 /// getNumRegs - Return the number of registers in this class.
100 unsigned getNumRegs() const { return RegsEnd-RegsBegin; }
102 /// getRegister - Return the specified register in the class.
104 unsigned getRegister(unsigned i) const {
105 assert(i < getNumRegs() && "Register number out of range!");
109 /// contains - Return true if the specified register is included in this
111 bool contains(unsigned Reg) const {
112 for (iterator I = begin(), E = end(); I != E; ++I)
113 if (*I == Reg) return true;
117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
119 bool hasType(MVT::ValueType vt) const {
120 for(int i = 0; VTs[i] != MVT::Other; ++i)
126 /// vt_begin / vt_end - Loop over all of the value types that can be
127 /// represented by values in this register class.
128 vt_iterator vt_begin() const {
132 vt_iterator vt_end() const {
134 while (*I != MVT::Other) ++I;
138 /// hasSubClass - return true if the specified TargetRegisterClass is a
139 /// sub-register class of this TargetRegisterClass.
140 bool hasSubClass(const TargetRegisterClass *cs) const {
141 for (int i = 0; SubClasses[i] != NULL; ++i)
142 if (SubClasses[i] == cs)
147 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
148 /// this register class.
149 sc_iterator subclasses_begin() const {
153 sc_iterator subclasses_end() const {
154 sc_iterator I = SubClasses;
155 while (*I != NULL) ++I;
159 /// hasSuperClass - return true if the specified TargetRegisterClass is a
160 /// super-register class of this TargetRegisterClass.
161 bool hasSuperClass(const TargetRegisterClass *cs) const {
162 for (int i = 0; SuperClasses[i] != NULL; ++i)
163 if (SuperClasses[i] == cs)
168 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
169 /// of this register class.
170 sc_iterator superclasses_begin() const {
174 sc_iterator superclasses_end() const {
175 sc_iterator I = SuperClasses;
176 while (*I != NULL) ++I;
180 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
181 /// class of a sub-register class for this TargetRegisterClass.
182 bool hasSubRegClass(const TargetRegisterClass *cs) const {
183 for (int i = 0; SubRegClasses[i] != NULL; ++i)
184 if (SubRegClasses[i] == cs)
189 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
190 /// class of a sub-register class for this TargetRegisterClass.
191 bool hasClassForSubReg(unsigned SubReg) const {
193 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
199 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
200 /// at idx for this TargetRegisterClass.
201 sc_iterator getClassForSubReg(unsigned SubReg) const {
203 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
205 return &SubRegClasses[i];
206 assert(0 && "Invalid subregister index for register class");
210 /// subregclasses_begin / subregclasses_end - Loop over all of
211 /// the subregister classes of this register class.
212 sc_iterator subregclasses_begin() const {
213 return SubRegClasses;
216 sc_iterator subregclasses_end() const {
217 sc_iterator I = SubRegClasses;
218 while (*I != NULL) ++I;
222 /// superregclasses_begin / superregclasses_end - Loop over all of
223 /// the superregister classes of this register class.
224 sc_iterator superregclasses_begin() const {
225 return SuperRegClasses;
228 sc_iterator superregclasses_end() const {
229 sc_iterator I = SuperRegClasses;
230 while (*I != NULL) ++I;
234 /// allocation_order_begin/end - These methods define a range of registers
235 /// which specify the registers in this class that are valid to register
236 /// allocate, and the preferred order to allocate them in. For example,
237 /// callee saved registers should be at the end of the list, because it is
238 /// cheaper to allocate caller saved registers.
240 /// These methods take a MachineFunction argument, which can be used to tune
241 /// the allocatable registers based on the characteristics of the function.
242 /// One simple example is that the frame pointer register can be used if
243 /// frame-pointer-elimination is performed.
245 /// By default, these methods return all registers in the class.
247 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
250 virtual iterator allocation_order_end(const MachineFunction &MF) const {
256 /// getSize - Return the size of the register in bytes, which is also the size
257 /// of a stack slot allocated to hold a spilled copy of this register.
258 unsigned getSize() const { return RegSize; }
260 /// getAlignment - Return the minimum required alignment for a register of
262 unsigned getAlignment() const { return Alignment; }
264 /// getCopyCost - Return the cost of copying a value between two registers in
266 int getCopyCost() const { return CopyCost; }
270 /// MRegisterInfo base class - We assume that the target defines a static array
271 /// of TargetRegisterDesc objects that represent all of the machine registers
272 /// that the target has. As such, we simply have to track a pointer to this
273 /// array so that we can turn register number into a register descriptor.
275 class MRegisterInfo {
277 typedef const TargetRegisterClass * const * regclass_iterator;
279 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
280 unsigned NumRegs; // Number of entries in the array
282 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
284 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
286 MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
287 regclass_iterator RegClassBegin, regclass_iterator RegClassEnd,
288 int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);
289 virtual ~MRegisterInfo();
292 enum { // Define some target independent constants
293 /// NoRegister - This physical register is not a real target register. It
294 /// is useful as a sentinal.
297 /// FirstVirtualRegister - This is the first register number that is
298 /// considered to be a 'virtual' register, which is part of the SSA
299 /// namespace. This must be the same for all targets, which means that each
300 /// target is limited to 1024 registers.
301 FirstVirtualRegister = 1024
304 /// isPhysicalRegister - Return true if the specified register number is in
305 /// the physical register namespace.
306 static bool isPhysicalRegister(unsigned Reg) {
307 assert(Reg && "this is not a register!");
308 return Reg < FirstVirtualRegister;
311 /// isVirtualRegister - Return true if the specified register number is in
312 /// the virtual register namespace.
313 static bool isVirtualRegister(unsigned Reg) {
314 assert(Reg && "this is not a register!");
315 return Reg >= FirstVirtualRegister;
318 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
319 /// register of the given type.
320 const TargetRegisterClass *getPhysicalRegisterRegClass(MVT::ValueType VT,
323 /// getAllocatableSet - Returns a bitset indexed by register number
324 /// indicating if a register is allocatable or not. If a register class is
325 /// specified, returns the subset for the class.
326 BitVector getAllocatableSet(MachineFunction &MF,
327 const TargetRegisterClass *RC = NULL) const;
329 const TargetRegisterDesc &operator[](unsigned RegNo) const {
330 assert(RegNo < NumRegs &&
331 "Attempting to access record for invalid register number!");
335 /// Provide a get method, equivalent to [], but more useful if we have a
336 /// pointer to this object.
338 const TargetRegisterDesc &get(unsigned RegNo) const {
339 return operator[](RegNo);
342 /// getAliasSet - Return the set of registers aliased by the specified
343 /// register, or a null list of there are none. The list returned is zero
346 const unsigned *getAliasSet(unsigned RegNo) const {
347 return get(RegNo).AliasSet;
350 /// getSubRegisters - Return the set of registers that are sub-registers of
351 /// the specified register, or a null list of there are none. The list
352 /// returned is zero terminated.
354 const unsigned *getSubRegisters(unsigned RegNo) const {
355 return get(RegNo).SubRegs;
358 /// getImmediateSubRegisters - Return the set of registers that are immediate
359 /// sub-registers of the specified register, or a null list of there are none.
360 /// The list returned is zero terminated.
362 const unsigned *getImmediateSubRegisters(unsigned RegNo) const {
363 return get(RegNo).ImmSubRegs;
366 /// getSuperRegisters - Return the set of registers that are super-registers
367 /// of the specified register, or a null list of there are none. The list
368 /// returned is zero terminated.
370 const unsigned *getSuperRegisters(unsigned RegNo) const {
371 return get(RegNo).SuperRegs;
374 /// isSubRegOf - Predicate which returns true if RegA is a sub-register of
375 /// RegB. Returns false otherwise.
377 bool isSubRegOf(unsigned RegA, unsigned RegB) const {
378 const TargetRegisterDesc &RD = (*this)[RegA];
379 for (const unsigned *reg = RD.SuperRegs; *reg != 0; ++reg)
385 /// getName - Return the symbolic target specific name for the specified
386 /// physical register.
387 const char *getName(unsigned RegNo) const {
388 return get(RegNo).Name;
391 /// getNumRegs - Return the number of registers this target has
392 /// (useful for sizing arrays holding per register information)
393 unsigned getNumRegs() const {
397 /// areAliases - Returns true if the two registers alias each other,
399 bool areAliases(unsigned regA, unsigned regB) const {
400 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
401 if (*Alias == regB) return true;
405 /// regsOverlap - Returns true if the two registers are equal or alias
406 /// each other. The registers may be virtual register.
407 bool regsOverlap(unsigned regA, unsigned regB) const {
411 if (isVirtualRegister(regA) || isVirtualRegister(regB))
413 return areAliases(regA, regB);
416 /// isSubRegister - Returns true if regB is a sub-register of regA.
418 bool isSubRegister(unsigned regA, unsigned regB) const {
419 for (const unsigned *SR = getSubRegisters(regA); *SR; ++SR)
420 if (*SR == regB) return true;
424 /// isSuperRegister - Returns true if regB is a super-register of regA.
426 bool isSuperRegister(unsigned regA, unsigned regB) const {
427 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
428 if (*SR == regB) return true;
432 /// getCalleeSavedRegs - Return a null-terminated list of all of the
433 /// callee saved registers on this target. The register should be in the
434 /// order of desired callee-save stack frame offset. The first register is
435 /// closed to the incoming stack pointer if stack grows down, and vice versa.
436 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
439 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
440 /// register classes to spill each callee saved register with. The order and
441 /// length of this list match the getCalleeSaveRegs() list.
442 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
443 const MachineFunction *MF) const =0;
445 /// getReservedRegs - Returns a bitset indexed by physical register number
446 /// indicating if a register is a special register that has particular uses and
447 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
448 /// register scavenger to determine what registers are free.
449 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
451 /// getSubReg - Returns the physical register number of sub-register "Index"
452 /// for physical register RegNo.
453 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
455 //===--------------------------------------------------------------------===//
456 // Register Class Information
459 /// Register class iterators
461 regclass_iterator regclass_begin() const { return RegClassBegin; }
462 regclass_iterator regclass_end() const { return RegClassEnd; }
464 unsigned getNumRegClasses() const {
465 return regclass_end()-regclass_begin();
468 /// getRegClass - Returns the register class associated with the enumeration
469 /// value. See class TargetOperandInfo.
470 const TargetRegisterClass *getRegClass(unsigned i) const {
471 assert(i <= getNumRegClasses() && "Register Class ID out of range");
472 return i ? RegClassBegin[i - 1] : NULL;
475 //===--------------------------------------------------------------------===//
476 // Interfaces used by the register allocator and stack frame
477 // manipulation passes to move data around between registers,
478 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
481 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved
482 /// registers and returns true if it isn't possible / profitable to do so by
483 /// issuing a series of store instructions via storeRegToStackSlot(). Returns
485 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
486 MachineBasicBlock::iterator MI,
487 const std::vector<CalleeSavedInfo> &CSI) const {
491 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
492 /// saved registers and returns true if it isn't possible / profitable to do
493 /// so by issuing a series of load instructions via loadRegToStackSlot().
494 /// Returns false otherwise.
495 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
496 MachineBasicBlock::iterator MI,
497 const std::vector<CalleeSavedInfo> &CSI) const {
501 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
502 MachineBasicBlock::iterator MI,
503 unsigned SrcReg, int FrameIndex,
504 const TargetRegisterClass *RC) const = 0;
506 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
507 MachineBasicBlock::iterator MI,
508 unsigned DestReg, int FrameIndex,
509 const TargetRegisterClass *RC) const = 0;
511 virtual void copyRegToReg(MachineBasicBlock &MBB,
512 MachineBasicBlock::iterator MI,
513 unsigned DestReg, unsigned SrcReg,
514 const TargetRegisterClass *DestRC,
515 const TargetRegisterClass *SrcRC) const = 0;
517 /// getCrossCopyRegClass - Returns a legal register class to copy a register
518 /// in the specified class to or from. Returns NULL if it is possible to copy
519 /// between a two registers of the specified class.
520 virtual const TargetRegisterClass *
521 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
525 /// reMaterialize - Re-issue the specified 'original' instruction at the
526 /// specific location targeting a new destination register.
527 virtual void reMaterialize(MachineBasicBlock &MBB,
528 MachineBasicBlock::iterator MI,
530 const MachineInstr *Orig) const = 0;
532 /// foldMemoryOperand - Attempt to fold a load or store of the
533 /// specified stack slot into the specified machine instruction for
534 /// the specified operand. If this is possible, a new instruction
535 /// is returned with the specified operand folded, otherwise NULL is
536 /// returned. The client is responsible for removing the old
537 /// instruction and adding the new one in the instruction stream
538 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
540 int FrameIndex) const {
544 /// foldMemoryOperand - Same as the previous version except it allows folding
545 /// of any load and store from / to any address, not just from a specific
547 virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
549 MachineInstr* LoadMI) const {
553 /// targetHandlesStackFrameRounding - Returns true if the target is responsible
554 /// for rounding up the stack frame (probably at emitPrologue time).
555 virtual bool targetHandlesStackFrameRounding() const {
559 /// requiresRegisterScavenging - returns true if the target requires (and
560 /// can make use of) the register scavenger.
561 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
565 /// hasFP - Return true if the specified function should have a dedicated frame
566 /// pointer register. For most targets this is true only if the function has
567 /// variable sized allocas or if frame pointer elimination is disabled.
568 virtual bool hasFP(const MachineFunction &MF) const = 0;
570 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
571 // not required, we reserve argument space for call sites in the function
572 // immediately on entry to the current function. This eliminates the need for
573 // add/sub sp brackets around call sites. Returns true if the call frame is
574 // included as part of the stack frame.
575 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
579 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
580 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
581 /// targets use pseudo instructions in order to abstract away the difference
582 /// between operating with a frame pointer and operating without, through the
583 /// use of these two instructions.
585 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
586 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
589 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
590 /// code insertion to eliminate call frame setup and destroy pseudo
591 /// instructions (but only if the Target is using them). It is responsible
592 /// for eliminating these instructions, replacing them with concrete
593 /// instructions. This method need only be implemented if using call frame
594 /// setup/destroy pseudo instructions.
597 eliminateCallFramePseudoInstr(MachineFunction &MF,
598 MachineBasicBlock &MBB,
599 MachineBasicBlock::iterator MI) const {
600 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
601 "eliminateCallFramePseudoInstr must be implemented if using"
602 " call frame setup/destroy pseudo instructions!");
603 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
606 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
607 /// before PrologEpilogInserter scans the physical registers used to determine
608 /// what callee saved registers should be spilled. This method is optional.
609 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
610 RegScavenger *RS = NULL) const {
614 /// processFunctionBeforeFrameFinalized - This method is called immediately
615 /// before the specified functions frame layout (MF.getFrameInfo()) is
616 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
617 /// replaced with direct constants. This method is optional.
619 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
622 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
623 /// frame indices from instructions which may use them. The instruction
624 /// referenced by the iterator contains an MO_FrameIndex operand which must be
625 /// eliminated by this method. This method may modify or replace the
626 /// specified instruction, as long as it keeps the iterator pointing the the
627 /// finished product. SPAdj is the SP adjustment due to call frame setup
628 /// instruction. The return value is the number of instructions added to
629 /// (negative if removed from) the basic block.
631 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
632 int SPAdj, RegScavenger *RS=NULL) const = 0;
634 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
635 /// the function. The return value is the number of instructions
636 /// added to (negative if removed from) the basic block (entry for prologue).
638 virtual void emitPrologue(MachineFunction &MF) const = 0;
639 virtual void emitEpilogue(MachineFunction &MF,
640 MachineBasicBlock &MBB) const = 0;
642 //===--------------------------------------------------------------------===//
643 /// Debug information queries.
645 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
646 /// number. Returns -1 if there is no equivalent value.
647 virtual int getDwarfRegNum(unsigned RegNum) const = 0;
649 /// getFrameRegister - This method should return the register used as a base
650 /// for values allocated in the current stack frame.
651 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
653 /// getRARegister - This method should return the register where the return
654 /// address can be found.
655 virtual unsigned getRARegister() const = 0;
657 /// getLocation - This method should return the actual location of a frame
658 /// variable given the frame index. The location is returned in ML.
659 /// Subclasses should override this method for special handling of frame
660 /// variables and call MRegisterInfo::getLocation for the default action.
661 virtual void getLocation(MachineFunction &MF, unsigned Index,
662 MachineLocation &ML) const;
664 /// getInitialFrameState - Returns a list of machine moves that are assumed
665 /// on entry to all functions. Note that LabelID is ignored (assumed to be
666 /// the beginning of the function.)
667 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
670 // This is useful when building IndexedMaps keyed on virtual registers
671 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
672 unsigned operator()(unsigned Reg) const {
673 return Reg - MRegisterInfo::FirstVirtualRegister;
677 } // End llvm namespace