include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41 def int_arm_clrex : Intrinsic<[]>;
  42
  43 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  44     llvm_ptr_ty]>;
  45 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  46
  47 //===----------------------------------------------------------------------===//
  48 // VFP
  49
  50 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  51                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  52 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  53                        Intrinsic<[], [llvm_i32_ty], []>;
  54 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  55                                   [IntrNoMem]>;
  56 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  57                                   [IntrNoMem]>;
  58
  59 //===----------------------------------------------------------------------===//
  60 // Coprocessor
  61
  62 // Move to coprocessor
  63 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  64    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  65                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  66 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  67    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  68                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  69
  70 // Move from coprocessor
  71 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  72    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  73                              llvm_i32_ty, llvm_i32_ty], []>;
  74 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  75    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  76                              llvm_i32_ty, llvm_i32_ty], []>;
  77
  78 // Coprocessor data processing
  79 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  80    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  82 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  83    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  84                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  85
  86 // Move from two registers to coprocessor
  87 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
  88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                   llvm_i32_ty, llvm_i32_ty], []>;
  90 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
  91    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  92                   llvm_i32_ty, llvm_i32_ty], []>;
  93
  94 //===----------------------------------------------------------------------===//
  95 // Advanced SIMD (NEON)
  96
  97 // The following classes do not correspond directly to GCC builtins.
  98 class Neon_1Arg_Intrinsic
  99   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 100 class Neon_1Arg_Narrow_Intrinsic
 101   : Intrinsic<[llvm_anyvector_ty],
 102               [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
 103 class Neon_2Arg_Intrinsic
 104   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 105               [IntrNoMem]>;
 106 class Neon_2Arg_Narrow_Intrinsic
 107   : Intrinsic<[llvm_anyvector_ty],
 108               [LLVMExtendedElementVectorType<0>,
 109                LLVMExtendedElementVectorType<0>],
 110               [IntrNoMem]>;
 111 class Neon_2Arg_Long_Intrinsic
 112   : Intrinsic<[llvm_anyvector_ty],
 113               [LLVMTruncatedElementVectorType<0>,
 114                LLVMTruncatedElementVectorType<0>],
 115               [IntrNoMem]>;
 116 class Neon_3Arg_Intrinsic
 117   : Intrinsic<[llvm_anyvector_ty],
 118               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 119               [IntrNoMem]>;
 120 class Neon_3Arg_Long_Intrinsic
 121   : Intrinsic<[llvm_anyvector_ty],
 122               [LLVMMatchType<0>,
 123                LLVMTruncatedElementVectorType<0>,
 124                LLVMTruncatedElementVectorType<0>],
 125               [IntrNoMem]>;
 126 class Neon_CvtFxToFP_Intrinsic
 127   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 128 class Neon_CvtFPToFx_Intrinsic
 129   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 130 class Neon_CvtFPtoInt_1Arg_Intrinsic
 131   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 132
 133 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 134 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 135 // Overall, the classes range from 2 to 6 v8i8 arguments.
 136 class Neon_Tbl2Arg_Intrinsic
 137   : Intrinsic<[llvm_v8i8_ty],
 138               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 139 class Neon_Tbl3Arg_Intrinsic
 140   : Intrinsic<[llvm_v8i8_ty],
 141               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 142 class Neon_Tbl4Arg_Intrinsic
 143   : Intrinsic<[llvm_v8i8_ty],
 144               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 145               [IntrNoMem]>;
 146 class Neon_Tbl5Arg_Intrinsic
 147   : Intrinsic<[llvm_v8i8_ty],
 148               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 149                llvm_v8i8_ty], [IntrNoMem]>;
 150 class Neon_Tbl6Arg_Intrinsic
 151   : Intrinsic<[llvm_v8i8_ty],
 152               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 153                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 154
 155 // Arithmetic ops
 156
 157 let Properties = [IntrNoMem, Commutative] in {
 158
 159   // Vector Add.
 160   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 161   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 162   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 163   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 164   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 165   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 166   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 167
 168   // Vector Multiply.
 169   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 170   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 171   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 172   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 173   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 174   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 175   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 176
 177   // Vector Maximum.
 178   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 179   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 180   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 181
 182   // Vector Minimum.
 183   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 184   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 185   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 186
 187   // Vector Reciprocal Step.
 188   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 189
 190   // Vector Reciprocal Square Root Step.
 191   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 192 }
 193
 194 // Vector Subtract.
 195 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 196 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 197 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 198 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 199 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 200
 201 // Vector Absolute Compare.
 202 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
 203                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 204                                     [IntrNoMem]>;
 205 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
 206                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 207                                     [IntrNoMem]>;
 208 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
 209                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 210                                     [IntrNoMem]>;
 211 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
 212                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 213                                     [IntrNoMem]>;
 214
 215 // Vector Absolute Differences.
 216 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 217 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 218
 219 // Vector Pairwise Add.
 220 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 221
 222 // Vector Pairwise Add Long.
 223 // Note: This is different than the other "long" NEON intrinsics because
 224 // the result vector has half as many elements as the source vector.
 225 // The source and destination vector types must be specified separately.
 226 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 227                                      [IntrNoMem]>;
 228 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 229                                      [IntrNoMem]>;
 230
 231 // Vector Pairwise Add and Accumulate Long.
 232 // Note: This is similar to vpaddl but the destination vector also appears
 233 // as the first argument.
 234 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 235                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 236                                      [IntrNoMem]>;
 237 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 238                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 239                                      [IntrNoMem]>;
 240
 241 // Vector Pairwise Maximum and Minimum.
 242 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 243 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 244 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 245 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 246
 247 // Vector Shifts:
 248 //
 249 // The various saturating and rounding vector shift operations need to be
 250 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 251 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 252 // be used for both left and right shifts, or even combinations of the two,
 253 // depending on the signs of the shift amounts.  It also has well-defined
 254 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 255 // by constants can be represented with LLVM's shift operators.
 256 //
 257 // The shift counts for these intrinsics are always vectors, even for constant
 258 // shifts, where the constant is replicated.  For consistency with VSHL (and
 259 // other variable shift instructions), left shifts have positive shift counts
 260 // and right shifts have negative shift counts.  This convention is also used
 261 // for constant right shift intrinsics, and to help preserve sanity, the
 262 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 263 // applicable, signed and unsigned versions of the intrinsics are
 264 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 265 // such as VQSHLU, take signed operands but produce unsigned results; these
 266 // use a "su" suffix.
 267
 268 // Vector Shift.
 269 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 270 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 271 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
 272 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
 273 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
 274
 275 // Vector Rounding Shift.
 276 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 277 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 278 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 279
 280 // Vector Saturating Shift.
 281 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 282 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 283 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 284 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 285 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 286 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 287
 288 // Vector Saturating Rounding Shift.
 289 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 290 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 291 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 292 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 293 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 294
 295 // Vector Shift and Insert.
 296 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 297
 298 // Vector Absolute Value and Saturating Absolute Value.
 299 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 300 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 301
 302 // Vector Saturating Negate.
 303 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 304
 305 // Vector Count Leading Sign/Zero Bits.
 306 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 307 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 308
 309 // Vector Count One Bits.
 310 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 311
 312 // Vector Reciprocal Estimate.
 313 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 314
 315 // Vector Reciprocal Square Root Estimate.
 316 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 317
 318 // Vector Conversions Between Floating-point and Integer
 319 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 320 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 321 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 322 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 323 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 324 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 325 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 326 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 327
 328 // Vector Conversions Between Floating-point and Fixed-point.
 329 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 330 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 331 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 332 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 333
 334 // Vector Conversions Between Half-Precision and Single-Precision.
 335 def int_arm_neon_vcvtfp2hf
 336     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 337 def int_arm_neon_vcvthf2fp
 338     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 339
 340 // Narrowing Saturating Vector Moves.
 341 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 342 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 343 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 344
 345 // Vector Table Lookup.
 346 // The first 1-4 arguments are the table.
 347 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 348 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 349 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 350 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 351
 352 // Vector Table Extension.
 353 // Some elements of the destination vector may not be updated, so the original
 354 // value of that vector is passed as the first argument.  The next 1-4
 355 // arguments after that are the table.
 356 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 357 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 358 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 359 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 360
 361 // Vector Rounding
 362 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 363 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 364 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 365 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 366 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 367 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 368
 369 // De-interleaving vector loads from N-element structures.
 370 // Source operands are the address and alignment.
 371 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 372                                   [llvm_ptr_ty, llvm_i32_ty],
 373                                   [IntrReadArgMem]>;
 374 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 375                                   [llvm_ptr_ty, llvm_i32_ty],
 376                                   [IntrReadArgMem]>;
 377 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 378                                    LLVMMatchType<0>],
 379                                   [llvm_ptr_ty, llvm_i32_ty],
 380                                   [IntrReadArgMem]>;
 381 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 382                                    LLVMMatchType<0>, LLVMMatchType<0>],
 383                                   [llvm_ptr_ty, llvm_i32_ty],
 384                                   [IntrReadArgMem]>;
 385
 386 // Vector load N-element structure to one lane.
 387 // Source operands are: the address, the N input vectors (since only one
 388 // lane is assigned), the lane number, and the alignment.
 389 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 390                                       [llvm_ptr_ty, LLVMMatchType<0>,
 391                                        LLVMMatchType<0>, llvm_i32_ty,
 392                                        llvm_i32_ty], [IntrReadArgMem]>;
 393 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 394                                        LLVMMatchType<0>],
 395                                       [llvm_ptr_ty, LLVMMatchType<0>,
 396                                        LLVMMatchType<0>, LLVMMatchType<0>,
 397                                        llvm_i32_ty, llvm_i32_ty],
 398                                       [IntrReadArgMem]>;
 399 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 400                                        LLVMMatchType<0>, LLVMMatchType<0>],
 401                                       [llvm_ptr_ty, LLVMMatchType<0>,
 402                                        LLVMMatchType<0>, LLVMMatchType<0>,
 403                                        LLVMMatchType<0>, llvm_i32_ty,
 404                                        llvm_i32_ty], [IntrReadArgMem]>;
 405
 406 // Interleaving vector stores from N-element structures.
 407 // Source operands are: the address, the N vectors, and the alignment.
 408 def int_arm_neon_vst1 : Intrinsic<[],
 409                                   [llvm_ptr_ty, llvm_anyvector_ty,
 410                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 411 def int_arm_neon_vst2 : Intrinsic<[],
 412                                   [llvm_ptr_ty, llvm_anyvector_ty,
 413                                    LLVMMatchType<0>, llvm_i32_ty],
 414                                   [IntrReadWriteArgMem]>;
 415 def int_arm_neon_vst3 : Intrinsic<[],
 416                                   [llvm_ptr_ty, llvm_anyvector_ty,
 417                                    LLVMMatchType<0>, LLVMMatchType<0>,
 418                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 419 def int_arm_neon_vst4 : Intrinsic<[],
 420                                   [llvm_ptr_ty, llvm_anyvector_ty,
 421                                    LLVMMatchType<0>, LLVMMatchType<0>,
 422                                    LLVMMatchType<0>, llvm_i32_ty],
 423                                   [IntrReadWriteArgMem]>;
 424
 425 // Vector store N-element structure from one lane.
 426 // Source operands are: the address, the N vectors, the lane number, and
 427 // the alignment.
 428 def int_arm_neon_vst2lane : Intrinsic<[],
 429                                       [llvm_ptr_ty, llvm_anyvector_ty,
 430                                        LLVMMatchType<0>, llvm_i32_ty,
 431                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 432 def int_arm_neon_vst3lane : Intrinsic<[],
 433                                       [llvm_ptr_ty, llvm_anyvector_ty,
 434                                        LLVMMatchType<0>, LLVMMatchType<0>,
 435                                        llvm_i32_ty, llvm_i32_ty],
 436                                       [IntrReadWriteArgMem]>;
 437 def int_arm_neon_vst4lane : Intrinsic<[],
 438                                       [llvm_ptr_ty, llvm_anyvector_ty,
 439                                        LLVMMatchType<0>, LLVMMatchType<0>,
 440                                        LLVMMatchType<0>, llvm_i32_ty,
 441                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 442
 443 // Vector bitwise select.
 444 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 445                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 446                         [IntrNoMem]>;
 447
 448 } // end TargetPrefix