include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41
  42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  44
  45 def int_arm_clrex : Intrinsic<[]>;
  46
  47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  48     llvm_ptr_ty]>;
  49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  50
  51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Data barrier instructions
  57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>;
  58 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // VFP
  62
  63 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  64                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  65 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  66                        Intrinsic<[], [llvm_i32_ty], []>;
  67 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  68                                   [IntrNoMem]>;
  69 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  70                                   [IntrNoMem]>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Coprocessor
  74
  75 // Move to coprocessor
  76 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  77    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  79 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  80    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  82
  83 // Move from coprocessor
  84 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  85    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                              llvm_i32_ty, llvm_i32_ty], []>;
  87 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  88    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                              llvm_i32_ty, llvm_i32_ty], []>;
  90
  91 // Coprocessor data processing
  92 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  94                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  95 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  96    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 // Move from two registers to coprocessor
 100 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 //===----------------------------------------------------------------------===//
 108 // CRC32
 109
 110 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 111     [IntrNoMem]>;
 112 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 113     [IntrNoMem]>;
 114 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 115     [IntrNoMem]>;
 116 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 117     [IntrNoMem]>;
 118 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 119     [IntrNoMem]>;
 120 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 121     [IntrNoMem]>;
 122
 123 //===----------------------------------------------------------------------===//
 124 // HINT
 125
 126 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 127
 128 //===----------------------------------------------------------------------===//
 129 // UND (reserved undefined sequence)
 130
 131 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 132
 133 //===----------------------------------------------------------------------===//
 134 // Advanced SIMD (NEON)
 135
 136 // The following classes do not correspond directly to GCC builtins.
 137 class Neon_1Arg_Intrinsic
 138   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 139 class Neon_1Arg_Narrow_Intrinsic
 140   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 141 class Neon_2Arg_Intrinsic
 142   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 143               [IntrNoMem]>;
 144 class Neon_2Arg_Narrow_Intrinsic
 145   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 146               [IntrNoMem]>;
 147 class Neon_2Arg_Long_Intrinsic
 148   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 149               [IntrNoMem]>;
 150 class Neon_3Arg_Intrinsic
 151   : Intrinsic<[llvm_anyvector_ty],
 152               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 153               [IntrNoMem]>;
 154 class Neon_3Arg_Long_Intrinsic
 155   : Intrinsic<[llvm_anyvector_ty],
 156               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 157               [IntrNoMem]>;
 158 class Neon_CvtFxToFP_Intrinsic
 159   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 160 class Neon_CvtFPToFx_Intrinsic
 161   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 162 class Neon_CvtFPtoInt_1Arg_Intrinsic
 163   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 164
 165 class Neon_Compare_Intrinsic
 166   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 167               [IntrNoMem]>;
 168
 169 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 170 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 171 // Overall, the classes range from 2 to 6 v8i8 arguments.
 172 class Neon_Tbl2Arg_Intrinsic
 173   : Intrinsic<[llvm_v8i8_ty],
 174               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 175 class Neon_Tbl3Arg_Intrinsic
 176   : Intrinsic<[llvm_v8i8_ty],
 177               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 178 class Neon_Tbl4Arg_Intrinsic
 179   : Intrinsic<[llvm_v8i8_ty],
 180               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 181               [IntrNoMem]>;
 182 class Neon_Tbl5Arg_Intrinsic
 183   : Intrinsic<[llvm_v8i8_ty],
 184               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 185                llvm_v8i8_ty], [IntrNoMem]>;
 186 class Neon_Tbl6Arg_Intrinsic
 187   : Intrinsic<[llvm_v8i8_ty],
 188               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 189                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 190
 191 // Arithmetic ops
 192
 193 let Properties = [IntrNoMem, Commutative] in {
 194
 195   // Vector Add.
 196   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 197   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 198   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 199   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 200   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 201   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 202   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 203
 204   // Vector Multiply.
 205   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 206   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 207   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 208   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 209   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 210   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 211   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 212
 213   // Vector Maximum.
 214   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 215   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 216   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 217
 218   // Vector Minimum.
 219   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 220   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 221   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 222
 223   // Vector Reciprocal Step.
 224   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 225
 226   // Vector Reciprocal Square Root Step.
 227   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 228 }
 229
 230 // Vector Subtract.
 231 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 232 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 233 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 234 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 235 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 236
 237 // Vector Absolute Compare.
 238 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 239 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 240
 241 // Vector Absolute Differences.
 242 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 243 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 244
 245 // Vector Pairwise Add.
 246 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 247
 248 // Vector Pairwise Add Long.
 249 // Note: This is different than the other "long" NEON intrinsics because
 250 // the result vector has half as many elements as the source vector.
 251 // The source and destination vector types must be specified separately.
 252 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 253                                      [IntrNoMem]>;
 254 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 255                                      [IntrNoMem]>;
 256
 257 // Vector Pairwise Add and Accumulate Long.
 258 // Note: This is similar to vpaddl but the destination vector also appears
 259 // as the first argument.
 260 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 261                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 262                                      [IntrNoMem]>;
 263 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 264                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 265                                      [IntrNoMem]>;
 266
 267 // Vector Pairwise Maximum and Minimum.
 268 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 269 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 270 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 271 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 272
 273 // Vector Shifts:
 274 //
 275 // The various saturating and rounding vector shift operations need to be
 276 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 277 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 278 // be used for both left and right shifts, or even combinations of the two,
 279 // depending on the signs of the shift amounts.  It also has well-defined
 280 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 281 // by constants can be represented with LLVM's shift operators.
 282 //
 283 // The shift counts for these intrinsics are always vectors, even for constant
 284 // shifts, where the constant is replicated.  For consistency with VSHL (and
 285 // other variable shift instructions), left shifts have positive shift counts
 286 // and right shifts have negative shift counts.  This convention is also used
 287 // for constant right shift intrinsics, and to help preserve sanity, the
 288 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 289 // applicable, signed and unsigned versions of the intrinsics are
 290 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 291 // such as VQSHLU, take signed operands but produce unsigned results; these
 292 // use a "su" suffix.
 293
 294 // Vector Shift.
 295 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 296 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 297
 298 // Vector Rounding Shift.
 299 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 300 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 301 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 302
 303 // Vector Saturating Shift.
 304 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 305 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 306 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 307 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 308 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 309 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 310
 311 // Vector Saturating Rounding Shift.
 312 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 313 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 314 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 315 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 316 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 317
 318 // Vector Shift and Insert.
 319 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 320
 321 // Vector Absolute Value and Saturating Absolute Value.
 322 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 323 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 324
 325 // Vector Saturating Negate.
 326 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 327
 328 // Vector Count Leading Sign/Zero Bits.
 329 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 330 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 331
 332 // Vector Count One Bits.
 333 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 334
 335 // Vector Reciprocal Estimate.
 336 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 337
 338 // Vector Reciprocal Square Root Estimate.
 339 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 340
 341 // Vector Conversions Between Floating-point and Integer
 342 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 343 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 344 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 345 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 346 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 347 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 348 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 349 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 350
 351 // Vector Conversions Between Floating-point and Fixed-point.
 352 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 353 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 354 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 355 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 356
 357 // Vector Conversions Between Half-Precision and Single-Precision.
 358 def int_arm_neon_vcvtfp2hf
 359     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 360 def int_arm_neon_vcvthf2fp
 361     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 362
 363 // Narrowing Saturating Vector Moves.
 364 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 365 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 366 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 367
 368 // Vector Table Lookup.
 369 // The first 1-4 arguments are the table.
 370 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 371 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 372 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 373 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 374
 375 // Vector Table Extension.
 376 // Some elements of the destination vector may not be updated, so the original
 377 // value of that vector is passed as the first argument.  The next 1-4
 378 // arguments after that are the table.
 379 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 380 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 381 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 382 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 383
 384 // Vector Rounding
 385 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 386 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 387 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 388 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 389 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 390 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 391
 392 // De-interleaving vector loads from N-element structures.
 393 // Source operands are the address and alignment.
 394 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 395                                   [llvm_ptr_ty, llvm_i32_ty],
 396                                   [IntrReadArgMem]>;
 397 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 398                                   [llvm_ptr_ty, llvm_i32_ty],
 399                                   [IntrReadArgMem]>;
 400 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 401                                    LLVMMatchType<0>],
 402                                   [llvm_ptr_ty, llvm_i32_ty],
 403                                   [IntrReadArgMem]>;
 404 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 405                                    LLVMMatchType<0>, LLVMMatchType<0>],
 406                                   [llvm_ptr_ty, llvm_i32_ty],
 407                                   [IntrReadArgMem]>;
 408
 409 // Vector load N-element structure to one lane.
 410 // Source operands are: the address, the N input vectors (since only one
 411 // lane is assigned), the lane number, and the alignment.
 412 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 413                                       [llvm_ptr_ty, LLVMMatchType<0>,
 414                                        LLVMMatchType<0>, llvm_i32_ty,
 415                                        llvm_i32_ty], [IntrReadArgMem]>;
 416 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 417                                        LLVMMatchType<0>],
 418                                       [llvm_ptr_ty, LLVMMatchType<0>,
 419                                        LLVMMatchType<0>, LLVMMatchType<0>,
 420                                        llvm_i32_ty, llvm_i32_ty],
 421                                       [IntrReadArgMem]>;
 422 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 423                                        LLVMMatchType<0>, LLVMMatchType<0>],
 424                                       [llvm_ptr_ty, LLVMMatchType<0>,
 425                                        LLVMMatchType<0>, LLVMMatchType<0>,
 426                                        LLVMMatchType<0>, llvm_i32_ty,
 427                                        llvm_i32_ty], [IntrReadArgMem]>;
 428
 429 // Interleaving vector stores from N-element structures.
 430 // Source operands are: the address, the N vectors, and the alignment.
 431 def int_arm_neon_vst1 : Intrinsic<[],
 432                                   [llvm_ptr_ty, llvm_anyvector_ty,
 433                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 434 def int_arm_neon_vst2 : Intrinsic<[],
 435                                   [llvm_ptr_ty, llvm_anyvector_ty,
 436                                    LLVMMatchType<0>, llvm_i32_ty],
 437                                   [IntrReadWriteArgMem]>;
 438 def int_arm_neon_vst3 : Intrinsic<[],
 439                                   [llvm_ptr_ty, llvm_anyvector_ty,
 440                                    LLVMMatchType<0>, LLVMMatchType<0>,
 441                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 442 def int_arm_neon_vst4 : Intrinsic<[],
 443                                   [llvm_ptr_ty, llvm_anyvector_ty,
 444                                    LLVMMatchType<0>, LLVMMatchType<0>,
 445                                    LLVMMatchType<0>, llvm_i32_ty],
 446                                   [IntrReadWriteArgMem]>;
 447
 448 // Vector store N-element structure from one lane.
 449 // Source operands are: the address, the N vectors, the lane number, and
 450 // the alignment.
 451 def int_arm_neon_vst2lane : Intrinsic<[],
 452                                       [llvm_ptr_ty, llvm_anyvector_ty,
 453                                        LLVMMatchType<0>, llvm_i32_ty,
 454                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 455 def int_arm_neon_vst3lane : Intrinsic<[],
 456                                       [llvm_ptr_ty, llvm_anyvector_ty,
 457                                        LLVMMatchType<0>, LLVMMatchType<0>,
 458                                        llvm_i32_ty, llvm_i32_ty],
 459                                       [IntrReadWriteArgMem]>;
 460 def int_arm_neon_vst4lane : Intrinsic<[],
 461                                       [llvm_ptr_ty, llvm_anyvector_ty,
 462                                        LLVMMatchType<0>, LLVMMatchType<0>,
 463                                        LLVMMatchType<0>, llvm_i32_ty,
 464                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 465
 466 // Vector bitwise select.
 467 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 468                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 469                         [IntrNoMem]>;
 470
 471
 472 // Crypto instructions
 473 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 474                                      [llvm_v16i8_ty], [IntrNoMem]>;
 475 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 476                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 477                                      [IntrNoMem]>;
 478
 479 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 480                                      [IntrNoMem]>;
 481 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 482                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 483                                      [IntrNoMem]>;
 484 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 485                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 486                                    [IntrNoMem]>;
 487 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 488                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 489                                    [IntrNoMem]>;
 490
 491 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 492 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 493 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 494 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 495 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 496 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 497 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 498 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 499 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 500 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 501 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 502 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 503 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 504 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 505
 506 } // end TargetPrefix