1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines all of the ARM-specific intrinsics.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
21 Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28 [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
32 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
34 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
36 //===----------------------------------------------------------------------===//
37 // Load, Store and Clear exclusive
39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
41 def int_arm_clrex : Intrinsic<[]>;
43 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
45 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
47 //===----------------------------------------------------------------------===//
50 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
51 Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
52 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
53 Intrinsic<[], [llvm_i32_ty], []>;
54 def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
56 def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
59 //===----------------------------------------------------------------------===//
62 // Move to coprocessor
63 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
64 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
65 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
66 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
67 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
68 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
70 // Move from coprocessor
71 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
72 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
73 llvm_i32_ty, llvm_i32_ty], []>;
74 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
75 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
76 llvm_i32_ty, llvm_i32_ty], []>;
78 // Coprocessor data processing
79 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
80 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
81 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
82 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
83 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
84 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
86 // Move from two registers to coprocessor
87 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
88 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
89 llvm_i32_ty, llvm_i32_ty], []>;
90 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
91 Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
92 llvm_i32_ty, llvm_i32_ty], []>;
94 //===----------------------------------------------------------------------===//
95 // Advanced SIMD (NEON)
97 // The following classes do not correspond directly to GCC builtins.
98 class Neon_1Arg_Intrinsic
99 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
100 class Neon_1Arg_Narrow_Intrinsic
101 : Intrinsic<[llvm_anyvector_ty],
102 [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
103 class Neon_2Arg_Intrinsic
104 : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
106 class Neon_2Arg_Narrow_Intrinsic
107 : Intrinsic<[llvm_anyvector_ty],
108 [LLVMExtendedElementVectorType<0>,
109 LLVMExtendedElementVectorType<0>],
111 class Neon_2Arg_Long_Intrinsic
112 : Intrinsic<[llvm_anyvector_ty],
113 [LLVMTruncatedElementVectorType<0>,
114 LLVMTruncatedElementVectorType<0>],
116 class Neon_3Arg_Intrinsic
117 : Intrinsic<[llvm_anyvector_ty],
118 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
120 class Neon_3Arg_Long_Intrinsic
121 : Intrinsic<[llvm_anyvector_ty],
123 LLVMTruncatedElementVectorType<0>,
124 LLVMTruncatedElementVectorType<0>],
126 class Neon_CvtFxToFP_Intrinsic
127 : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
128 class Neon_CvtFPToFx_Intrinsic
129 : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
130 class Neon_CvtFPtoInt_1Arg_Intrinsic
131 : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
133 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
134 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
135 // Overall, the classes range from 2 to 6 v8i8 arguments.
136 class Neon_Tbl2Arg_Intrinsic
137 : Intrinsic<[llvm_v8i8_ty],
138 [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
139 class Neon_Tbl3Arg_Intrinsic
140 : Intrinsic<[llvm_v8i8_ty],
141 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
142 class Neon_Tbl4Arg_Intrinsic
143 : Intrinsic<[llvm_v8i8_ty],
144 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
146 class Neon_Tbl5Arg_Intrinsic
147 : Intrinsic<[llvm_v8i8_ty],
148 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
149 llvm_v8i8_ty], [IntrNoMem]>;
150 class Neon_Tbl6Arg_Intrinsic
151 : Intrinsic<[llvm_v8i8_ty],
152 [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
153 llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
157 let Properties = [IntrNoMem, Commutative] in {
160 def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
161 def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
162 def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
163 def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
164 def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
165 def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
166 def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
167 def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
170 def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
171 def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
172 def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
173 def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
174 def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
175 def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
176 def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
178 // Vector Multiply and Accumulate/Subtract.
179 def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
180 def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
183 def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
184 def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
185 def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
188 def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
189 def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
190 def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
192 // Vector Reciprocal Step.
193 def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
195 // Vector Reciprocal Square Root Step.
196 def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
200 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
201 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
202 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
203 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
204 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
205 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
207 // Vector Absolute Compare.
208 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
209 [llvm_v2f32_ty, llvm_v2f32_ty],
211 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
212 [llvm_v4f32_ty, llvm_v4f32_ty],
214 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
215 [llvm_v2f32_ty, llvm_v2f32_ty],
217 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
218 [llvm_v4f32_ty, llvm_v4f32_ty],
221 // Vector Absolute Differences.
222 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
223 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
225 // Vector Pairwise Add.
226 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
228 // Vector Pairwise Add Long.
229 // Note: This is different than the other "long" NEON intrinsics because
230 // the result vector has half as many elements as the source vector.
231 // The source and destination vector types must be specified separately.
232 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
234 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
237 // Vector Pairwise Add and Accumulate Long.
238 // Note: This is similar to vpaddl but the destination vector also appears
239 // as the first argument.
240 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
241 [LLVMMatchType<0>, llvm_anyvector_ty],
243 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
244 [LLVMMatchType<0>, llvm_anyvector_ty],
247 // Vector Pairwise Maximum and Minimum.
248 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
249 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
250 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
251 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
255 // The various saturating and rounding vector shift operations need to be
256 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
257 // operation cannot be safely translated to LLVM's shift operators. VSHL can
258 // be used for both left and right shifts, or even combinations of the two,
259 // depending on the signs of the shift amounts. It also has well-defined
260 // behavior for shift amounts that LLVM leaves undefined. Only basic shifts
261 // by constants can be represented with LLVM's shift operators.
263 // The shift counts for these intrinsics are always vectors, even for constant
264 // shifts, where the constant is replicated. For consistency with VSHL (and
265 // other variable shift instructions), left shifts have positive shift counts
266 // and right shifts have negative shift counts. This convention is also used
267 // for constant right shift intrinsics, and to help preserve sanity, the
268 // intrinsic names use "shift" instead of either "shl" or "shr". Where
269 // applicable, signed and unsigned versions of the intrinsics are
270 // distinguished with "s" and "u" suffixes. A few NEON shift instructions,
271 // such as VQSHLU, take signed operands but produce unsigned results; these
272 // use a "su" suffix.
275 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
276 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
277 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
278 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
279 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
281 // Vector Rounding Shift.
282 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
283 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
284 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
286 // Vector Saturating Shift.
287 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
288 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
289 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
290 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
291 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
292 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
294 // Vector Saturating Rounding Shift.
295 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
296 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
297 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
298 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
299 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
301 // Vector Shift and Insert.
302 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
304 // Vector Absolute Value and Saturating Absolute Value.
305 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
306 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
308 // Vector Saturating Negate.
309 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
311 // Vector Count Leading Sign/Zero Bits.
312 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
313 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
315 // Vector Count One Bits.
316 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
318 // Vector Reciprocal Estimate.
319 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
321 // Vector Reciprocal Square Root Estimate.
322 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
324 // Vector Conversions Between Floating-point and Integer
325 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
326 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
327 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
328 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
329 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
330 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
331 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
332 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
334 // Vector Conversions Between Floating-point and Fixed-point.
335 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
336 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
337 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
338 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
340 // Vector Conversions Between Half-Precision and Single-Precision.
341 def int_arm_neon_vcvtfp2hf
342 : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
343 def int_arm_neon_vcvthf2fp
344 : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
346 // Narrowing Saturating Vector Moves.
347 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
348 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
349 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
351 // Vector Table Lookup.
352 // The first 1-4 arguments are the table.
353 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
354 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
355 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
356 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
358 // Vector Table Extension.
359 // Some elements of the destination vector may not be updated, so the original
360 // value of that vector is passed as the first argument. The next 1-4
361 // arguments after that are the table.
362 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
363 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
364 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
365 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
368 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
369 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
370 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
371 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
372 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
373 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
375 // De-interleaving vector loads from N-element structures.
376 // Source operands are the address and alignment.
377 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
378 [llvm_ptr_ty, llvm_i32_ty],
380 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
381 [llvm_ptr_ty, llvm_i32_ty],
383 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
385 [llvm_ptr_ty, llvm_i32_ty],
387 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
388 LLVMMatchType<0>, LLVMMatchType<0>],
389 [llvm_ptr_ty, llvm_i32_ty],
392 // Vector load N-element structure to one lane.
393 // Source operands are: the address, the N input vectors (since only one
394 // lane is assigned), the lane number, and the alignment.
395 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
396 [llvm_ptr_ty, LLVMMatchType<0>,
397 LLVMMatchType<0>, llvm_i32_ty,
398 llvm_i32_ty], [IntrReadArgMem]>;
399 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
401 [llvm_ptr_ty, LLVMMatchType<0>,
402 LLVMMatchType<0>, LLVMMatchType<0>,
403 llvm_i32_ty, llvm_i32_ty],
405 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
406 LLVMMatchType<0>, LLVMMatchType<0>],
407 [llvm_ptr_ty, LLVMMatchType<0>,
408 LLVMMatchType<0>, LLVMMatchType<0>,
409 LLVMMatchType<0>, llvm_i32_ty,
410 llvm_i32_ty], [IntrReadArgMem]>;
412 // Interleaving vector stores from N-element structures.
413 // Source operands are: the address, the N vectors, and the alignment.
414 def int_arm_neon_vst1 : Intrinsic<[],
415 [llvm_ptr_ty, llvm_anyvector_ty,
416 llvm_i32_ty], [IntrReadWriteArgMem]>;
417 def int_arm_neon_vst2 : Intrinsic<[],
418 [llvm_ptr_ty, llvm_anyvector_ty,
419 LLVMMatchType<0>, llvm_i32_ty],
420 [IntrReadWriteArgMem]>;
421 def int_arm_neon_vst3 : Intrinsic<[],
422 [llvm_ptr_ty, llvm_anyvector_ty,
423 LLVMMatchType<0>, LLVMMatchType<0>,
424 llvm_i32_ty], [IntrReadWriteArgMem]>;
425 def int_arm_neon_vst4 : Intrinsic<[],
426 [llvm_ptr_ty, llvm_anyvector_ty,
427 LLVMMatchType<0>, LLVMMatchType<0>,
428 LLVMMatchType<0>, llvm_i32_ty],
429 [IntrReadWriteArgMem]>;
431 // Vector store N-element structure from one lane.
432 // Source operands are: the address, the N vectors, the lane number, and
434 def int_arm_neon_vst2lane : Intrinsic<[],
435 [llvm_ptr_ty, llvm_anyvector_ty,
436 LLVMMatchType<0>, llvm_i32_ty,
437 llvm_i32_ty], [IntrReadWriteArgMem]>;
438 def int_arm_neon_vst3lane : Intrinsic<[],
439 [llvm_ptr_ty, llvm_anyvector_ty,
440 LLVMMatchType<0>, LLVMMatchType<0>,
441 llvm_i32_ty, llvm_i32_ty],
442 [IntrReadWriteArgMem]>;
443 def int_arm_neon_vst4lane : Intrinsic<[],
444 [llvm_ptr_ty, llvm_anyvector_ty,
445 LLVMMatchType<0>, LLVMMatchType<0>,
446 LLVMMatchType<0>, llvm_i32_ty,
447 llvm_i32_ty], [IntrReadWriteArgMem]>;
449 // Vector bitwise select.
450 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
451 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
454 } // end TargetPrefix