ARM: mark matching ARM intrinsics as MSBuiltin
[oota-llvm.git] / include / llvm / IR / IntrinsicsARM.td
1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines all of the ARM-specific intrinsics.
11 //
12 //===----------------------------------------------------------------------===//
13
14
15 //===----------------------------------------------------------------------===//
16 // TLS
17
18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
19
20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
22
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
25
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28     [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
35
36 //===----------------------------------------------------------------------===//
37 // Load, Store and Clear exclusive
38
39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
41
42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
44
45 def int_arm_clrex : Intrinsic<[]>;
46
47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
48     llvm_ptr_ty]>;
49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
50
51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
54
55 //===----------------------------------------------------------------------===//
56 // Data barrier instructions
57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
58                   Intrinsic<[], [llvm_i32_ty]>;
59 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
60                   Intrinsic<[], [llvm_i32_ty]>;
61 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
62                   Intrinsic<[], [llvm_i32_ty]>;
63
64 //===----------------------------------------------------------------------===//
65 // VFP
66
67 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
68                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
69 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
70                        Intrinsic<[], [llvm_i32_ty], []>;
71 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
72                                   [IntrNoMem]>;
73 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
74                                   [IntrNoMem]>;
75
76 //===----------------------------------------------------------------------===//
77 // Coprocessor
78
79 // Move to coprocessor
80 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
81                   MSBuiltin<"_MoveToCoprocessor">,
82    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
83                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
84 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
85                    MSBuiltin<"_MoveToCoprocessor2">,
86    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
87                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
88
89 // Move from coprocessor
90 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
91                   MSBuiltin<"_MoveFromCoprocessor">,
92    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
93                              llvm_i32_ty, llvm_i32_ty], []>;
94 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
95                    MSBuiltin<"_MoveFromCoprocessor2">,
96    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
97                              llvm_i32_ty, llvm_i32_ty], []>;
98
99 // Coprocessor data processing
100 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
102                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
103 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
105                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
106
107 // Move from two registers to coprocessor
108 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
109    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
110                   llvm_i32_ty, llvm_i32_ty], []>;
111 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
112    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
113                   llvm_i32_ty, llvm_i32_ty], []>;
114
115 //===----------------------------------------------------------------------===//
116 // CRC32
117
118 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
119     [IntrNoMem]>;
120 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
121     [IntrNoMem]>;
122 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
123     [IntrNoMem]>;
124 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
125     [IntrNoMem]>;
126 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
127     [IntrNoMem]>;
128 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
129     [IntrNoMem]>;
130
131 //===----------------------------------------------------------------------===//
132 // HINT
133
134 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
135
136 //===----------------------------------------------------------------------===//
137 // RBIT
138
139 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
140
141 //===----------------------------------------------------------------------===//
142 // UND (reserved undefined sequence)
143
144 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
145
146 //===----------------------------------------------------------------------===//
147 // Advanced SIMD (NEON)
148
149 // The following classes do not correspond directly to GCC builtins.
150 class Neon_1Arg_Intrinsic
151   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
152 class Neon_1Arg_Narrow_Intrinsic
153   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
154 class Neon_2Arg_Intrinsic
155   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
156               [IntrNoMem]>;
157 class Neon_2Arg_Narrow_Intrinsic
158   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
159               [IntrNoMem]>;
160 class Neon_2Arg_Long_Intrinsic
161   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
162               [IntrNoMem]>;
163 class Neon_3Arg_Intrinsic
164   : Intrinsic<[llvm_anyvector_ty],
165               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
166               [IntrNoMem]>;
167 class Neon_3Arg_Long_Intrinsic
168   : Intrinsic<[llvm_anyvector_ty],
169               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
170               [IntrNoMem]>;
171 class Neon_CvtFxToFP_Intrinsic
172   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
173 class Neon_CvtFPToFx_Intrinsic
174   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
175 class Neon_CvtFPtoInt_1Arg_Intrinsic
176   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
177
178 class Neon_Compare_Intrinsic
179   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
180               [IntrNoMem]>;
181
182 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
183 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
184 // Overall, the classes range from 2 to 6 v8i8 arguments.
185 class Neon_Tbl2Arg_Intrinsic
186   : Intrinsic<[llvm_v8i8_ty],
187               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
188 class Neon_Tbl3Arg_Intrinsic
189   : Intrinsic<[llvm_v8i8_ty],
190               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
191 class Neon_Tbl4Arg_Intrinsic
192   : Intrinsic<[llvm_v8i8_ty],
193               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
194               [IntrNoMem]>;
195 class Neon_Tbl5Arg_Intrinsic
196   : Intrinsic<[llvm_v8i8_ty],
197               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
198                llvm_v8i8_ty], [IntrNoMem]>;
199 class Neon_Tbl6Arg_Intrinsic
200   : Intrinsic<[llvm_v8i8_ty],
201               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
202                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
203
204 // Arithmetic ops
205
206 let Properties = [IntrNoMem, Commutative] in {
207
208   // Vector Add.
209   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
210   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
211   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
212   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
213   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
214   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
215   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
216
217   // Vector Multiply.
218   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
219   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
220   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
221   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
222   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
223   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
224   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
225
226   // Vector Maximum.
227   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
228   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
229   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
230
231   // Vector Minimum.
232   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
233   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
234   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
235
236   // Vector Reciprocal Step.
237   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
238
239   // Vector Reciprocal Square Root Step.
240   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
241 }
242
243 // Vector Subtract.
244 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
245 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
246 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
247 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
248 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
249
250 // Vector Absolute Compare.
251 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
252 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
253
254 // Vector Absolute Differences.
255 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
256 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
257
258 // Vector Pairwise Add.
259 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
260
261 // Vector Pairwise Add Long.
262 // Note: This is different than the other "long" NEON intrinsics because
263 // the result vector has half as many elements as the source vector.
264 // The source and destination vector types must be specified separately.
265 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
266                                      [IntrNoMem]>;
267 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
268                                      [IntrNoMem]>;
269
270 // Vector Pairwise Add and Accumulate Long.
271 // Note: This is similar to vpaddl but the destination vector also appears
272 // as the first argument.
273 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
274                                      [LLVMMatchType<0>, llvm_anyvector_ty],
275                                      [IntrNoMem]>;
276 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
277                                      [LLVMMatchType<0>, llvm_anyvector_ty],
278                                      [IntrNoMem]>;
279
280 // Vector Pairwise Maximum and Minimum.
281 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
282 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
283 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
284 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
285
286 // Vector Shifts:
287 //
288 // The various saturating and rounding vector shift operations need to be
289 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
290 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
291 // be used for both left and right shifts, or even combinations of the two,
292 // depending on the signs of the shift amounts.  It also has well-defined
293 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
294 // by constants can be represented with LLVM's shift operators.
295 //
296 // The shift counts for these intrinsics are always vectors, even for constant
297 // shifts, where the constant is replicated.  For consistency with VSHL (and
298 // other variable shift instructions), left shifts have positive shift counts
299 // and right shifts have negative shift counts.  This convention is also used
300 // for constant right shift intrinsics, and to help preserve sanity, the
301 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
302 // applicable, signed and unsigned versions of the intrinsics are
303 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
304 // such as VQSHLU, take signed operands but produce unsigned results; these
305 // use a "su" suffix.
306
307 // Vector Shift.
308 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
309 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
310
311 // Vector Rounding Shift.
312 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
313 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
314 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
315
316 // Vector Saturating Shift.
317 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
318 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
319 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
320 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
321 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
322 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
323
324 // Vector Saturating Rounding Shift.
325 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
326 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
327 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
328 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
329 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
330
331 // Vector Shift and Insert.
332 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
333
334 // Vector Absolute Value and Saturating Absolute Value.
335 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
336 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
337
338 // Vector Saturating Negate.
339 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
340
341 // Vector Count Leading Sign/Zero Bits.
342 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
343 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
344
345 // Vector Count One Bits.
346 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
347
348 // Vector Reciprocal Estimate.
349 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
350
351 // Vector Reciprocal Square Root Estimate.
352 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
353
354 // Vector Conversions Between Floating-point and Integer
355 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
356 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
357 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
358 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
359 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
360 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
361 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
362 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
363
364 // Vector Conversions Between Floating-point and Fixed-point.
365 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
366 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
367 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
368 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
369
370 // Vector Conversions Between Half-Precision and Single-Precision.
371 def int_arm_neon_vcvtfp2hf
372     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
373 def int_arm_neon_vcvthf2fp
374     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
375
376 // Narrowing Saturating Vector Moves.
377 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
378 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
379 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
380
381 // Vector Table Lookup.
382 // The first 1-4 arguments are the table.
383 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
384 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
385 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
386 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
387
388 // Vector Table Extension.
389 // Some elements of the destination vector may not be updated, so the original
390 // value of that vector is passed as the first argument.  The next 1-4
391 // arguments after that are the table.
392 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
393 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
394 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
395 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
396
397 // Vector Rounding
398 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
399 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
400 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
401 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
402 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
403 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
404
405 // De-interleaving vector loads from N-element structures.
406 // Source operands are the address and alignment.
407 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
408                                   [llvm_ptr_ty, llvm_i32_ty],
409                                   [IntrReadArgMem]>;
410 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
411                                   [llvm_ptr_ty, llvm_i32_ty],
412                                   [IntrReadArgMem]>;
413 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
414                                    LLVMMatchType<0>],
415                                   [llvm_ptr_ty, llvm_i32_ty],
416                                   [IntrReadArgMem]>;
417 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
418                                    LLVMMatchType<0>, LLVMMatchType<0>],
419                                   [llvm_ptr_ty, llvm_i32_ty],
420                                   [IntrReadArgMem]>;
421
422 // Vector load N-element structure to one lane.
423 // Source operands are: the address, the N input vectors (since only one
424 // lane is assigned), the lane number, and the alignment.
425 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
426                                       [llvm_ptr_ty, LLVMMatchType<0>,
427                                        LLVMMatchType<0>, llvm_i32_ty,
428                                        llvm_i32_ty], [IntrReadArgMem]>;
429 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
430                                        LLVMMatchType<0>],
431                                       [llvm_ptr_ty, LLVMMatchType<0>,
432                                        LLVMMatchType<0>, LLVMMatchType<0>,
433                                        llvm_i32_ty, llvm_i32_ty],
434                                       [IntrReadArgMem]>;
435 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
436                                        LLVMMatchType<0>, LLVMMatchType<0>],
437                                       [llvm_ptr_ty, LLVMMatchType<0>,
438                                        LLVMMatchType<0>, LLVMMatchType<0>,
439                                        LLVMMatchType<0>, llvm_i32_ty,
440                                        llvm_i32_ty], [IntrReadArgMem]>;
441
442 // Interleaving vector stores from N-element structures.
443 // Source operands are: the address, the N vectors, and the alignment.
444 def int_arm_neon_vst1 : Intrinsic<[],
445                                   [llvm_ptr_ty, llvm_anyvector_ty,
446                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
447 def int_arm_neon_vst2 : Intrinsic<[],
448                                   [llvm_ptr_ty, llvm_anyvector_ty,
449                                    LLVMMatchType<0>, llvm_i32_ty],
450                                   [IntrReadWriteArgMem]>;
451 def int_arm_neon_vst3 : Intrinsic<[],
452                                   [llvm_ptr_ty, llvm_anyvector_ty,
453                                    LLVMMatchType<0>, LLVMMatchType<0>,
454                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
455 def int_arm_neon_vst4 : Intrinsic<[],
456                                   [llvm_ptr_ty, llvm_anyvector_ty,
457                                    LLVMMatchType<0>, LLVMMatchType<0>,
458                                    LLVMMatchType<0>, llvm_i32_ty],
459                                   [IntrReadWriteArgMem]>;
460
461 // Vector store N-element structure from one lane.
462 // Source operands are: the address, the N vectors, the lane number, and
463 // the alignment.
464 def int_arm_neon_vst2lane : Intrinsic<[],
465                                       [llvm_ptr_ty, llvm_anyvector_ty,
466                                        LLVMMatchType<0>, llvm_i32_ty,
467                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
468 def int_arm_neon_vst3lane : Intrinsic<[],
469                                       [llvm_ptr_ty, llvm_anyvector_ty,
470                                        LLVMMatchType<0>, LLVMMatchType<0>,
471                                        llvm_i32_ty, llvm_i32_ty],
472                                       [IntrReadWriteArgMem]>;
473 def int_arm_neon_vst4lane : Intrinsic<[],
474                                       [llvm_ptr_ty, llvm_anyvector_ty,
475                                        LLVMMatchType<0>, LLVMMatchType<0>,
476                                        LLVMMatchType<0>, llvm_i32_ty,
477                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
478
479 // Vector bitwise select.
480 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
481                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
482                         [IntrNoMem]>;
483
484
485 // Crypto instructions
486 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
487                                      [llvm_v16i8_ty], [IntrNoMem]>;
488 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
489                                      [llvm_v16i8_ty, llvm_v16i8_ty],
490                                      [IntrNoMem]>;
491
492 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
493                                      [IntrNoMem]>;
494 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
495                                      [llvm_v4i32_ty, llvm_v4i32_ty],
496                                      [IntrNoMem]>;
497 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
498                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
499                                    [IntrNoMem]>;
500 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
501                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
502                                    [IntrNoMem]>;
503
504 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
505 def int_arm_neon_aese : AES_2Arg_Intrinsic;
506 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
507 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
508 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
509 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
510 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
511 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
512 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
513 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
514 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
515 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
516 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
517 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
518
519 } // end TargetPrefix