include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41 def int_arm_clrex : Intrinsic<[]>;
  42
  43 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  44     llvm_ptr_ty]>;
  45 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  46
  47 //===----------------------------------------------------------------------===//
  48 // Data barrier instructions
  49 def int_arm_dmb : Intrinsic<[], [llvm_i32_ty]>;
  50 def int_arm_dsb : Intrinsic<[], [llvm_i32_ty]>;
  51
  52 //===----------------------------------------------------------------------===//
  53 // VFP
  54
  55 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  56                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  57 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  58                        Intrinsic<[], [llvm_i32_ty], []>;
  59 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  60                                   [IntrNoMem]>;
  61 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  62                                   [IntrNoMem]>;
  63
  64 //===----------------------------------------------------------------------===//
  65 // Coprocessor
  66
  67 // Move to coprocessor
  68 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  69    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  70                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  71 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  72    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  73                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  74
  75 // Move from coprocessor
  76 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  77    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                              llvm_i32_ty, llvm_i32_ty], []>;
  79 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  80    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                              llvm_i32_ty, llvm_i32_ty], []>;
  82
  83 // Coprocessor data processing
  84 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  85    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  87 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  90
  91 // Move from two registers to coprocessor
  92 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  94                   llvm_i32_ty, llvm_i32_ty], []>;
  95 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
  96    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                   llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 //===----------------------------------------------------------------------===//
 100 // CRC32
 101
 102 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 103     [IntrNoMem]>;
 104 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 105     [IntrNoMem]>;
 106 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 107     [IntrNoMem]>;
 108 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 109     [IntrNoMem]>;
 110 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 111     [IntrNoMem]>;
 112 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 113     [IntrNoMem]>;
 114
 115 //===----------------------------------------------------------------------===//
 116 // Advanced SIMD (NEON)
 117
 118 // The following classes do not correspond directly to GCC builtins.
 119 class Neon_1Arg_Intrinsic
 120   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 121 class Neon_1Arg_Narrow_Intrinsic
 122   : Intrinsic<[llvm_anyvector_ty],
 123               [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
 124 class Neon_2Arg_Intrinsic
 125   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 126               [IntrNoMem]>;
 127 class Neon_2Arg_Narrow_Intrinsic
 128   : Intrinsic<[llvm_anyvector_ty],
 129               [LLVMExtendedElementVectorType<0>,
 130                LLVMExtendedElementVectorType<0>],
 131               [IntrNoMem]>;
 132 class Neon_2Arg_Long_Intrinsic
 133   : Intrinsic<[llvm_anyvector_ty],
 134               [LLVMTruncatedElementVectorType<0>,
 135                LLVMTruncatedElementVectorType<0>],
 136               [IntrNoMem]>;
 137 class Neon_3Arg_Intrinsic
 138   : Intrinsic<[llvm_anyvector_ty],
 139               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 140               [IntrNoMem]>;
 141 class Neon_3Arg_Long_Intrinsic
 142   : Intrinsic<[llvm_anyvector_ty],
 143               [LLVMMatchType<0>,
 144                LLVMTruncatedElementVectorType<0>,
 145                LLVMTruncatedElementVectorType<0>],
 146               [IntrNoMem]>;
 147 class Neon_CvtFxToFP_Intrinsic
 148   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 149 class Neon_CvtFPToFx_Intrinsic
 150   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 151 class Neon_CvtFPtoInt_1Arg_Intrinsic
 152   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 153
 154 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 155 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 156 // Overall, the classes range from 2 to 6 v8i8 arguments.
 157 class Neon_Tbl2Arg_Intrinsic
 158   : Intrinsic<[llvm_v8i8_ty],
 159               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 160 class Neon_Tbl3Arg_Intrinsic
 161   : Intrinsic<[llvm_v8i8_ty],
 162               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 163 class Neon_Tbl4Arg_Intrinsic
 164   : Intrinsic<[llvm_v8i8_ty],
 165               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 166               [IntrNoMem]>;
 167 class Neon_Tbl5Arg_Intrinsic
 168   : Intrinsic<[llvm_v8i8_ty],
 169               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 170                llvm_v8i8_ty], [IntrNoMem]>;
 171 class Neon_Tbl6Arg_Intrinsic
 172   : Intrinsic<[llvm_v8i8_ty],
 173               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 174                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 175
 176 // Arithmetic ops
 177
 178 let Properties = [IntrNoMem, Commutative] in {
 179
 180   // Vector Add.
 181   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 182   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 183   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 184   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 185   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 186   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 187   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 188
 189   // Vector Multiply.
 190   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 191   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 192   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 193   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 194   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 195   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 196   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 197
 198   // Vector Maximum.
 199   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 200   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 201   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 202
 203   // Vector Minimum.
 204   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 205   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 206   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 207
 208   // Vector Reciprocal Step.
 209   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 210
 211   // Vector Reciprocal Square Root Step.
 212   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 213 }
 214
 215 // Vector Subtract.
 216 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 217 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 218 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 219 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 220 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 221
 222 // Vector Absolute Compare.
 223 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
 224                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 225                                     [IntrNoMem]>;
 226 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
 227                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 228                                     [IntrNoMem]>;
 229 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
 230                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 231                                     [IntrNoMem]>;
 232 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
 233                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 234                                     [IntrNoMem]>;
 235
 236 // Vector Absolute Differences.
 237 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 238 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 239
 240 // Vector Pairwise Add.
 241 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 242
 243 // Vector Pairwise Add Long.
 244 // Note: This is different than the other "long" NEON intrinsics because
 245 // the result vector has half as many elements as the source vector.
 246 // The source and destination vector types must be specified separately.
 247 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 248                                      [IntrNoMem]>;
 249 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 250                                      [IntrNoMem]>;
 251
 252 // Vector Pairwise Add and Accumulate Long.
 253 // Note: This is similar to vpaddl but the destination vector also appears
 254 // as the first argument.
 255 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 256                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 257                                      [IntrNoMem]>;
 258 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 259                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 260                                      [IntrNoMem]>;
 261
 262 // Vector Pairwise Maximum and Minimum.
 263 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 264 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 265 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 266 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 267
 268 // Vector Shifts:
 269 //
 270 // The various saturating and rounding vector shift operations need to be
 271 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 272 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 273 // be used for both left and right shifts, or even combinations of the two,
 274 // depending on the signs of the shift amounts.  It also has well-defined
 275 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 276 // by constants can be represented with LLVM's shift operators.
 277 //
 278 // The shift counts for these intrinsics are always vectors, even for constant
 279 // shifts, where the constant is replicated.  For consistency with VSHL (and
 280 // other variable shift instructions), left shifts have positive shift counts
 281 // and right shifts have negative shift counts.  This convention is also used
 282 // for constant right shift intrinsics, and to help preserve sanity, the
 283 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 284 // applicable, signed and unsigned versions of the intrinsics are
 285 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 286 // such as VQSHLU, take signed operands but produce unsigned results; these
 287 // use a "su" suffix.
 288
 289 // Vector Shift.
 290 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 291 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 292 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
 293 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
 294 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
 295
 296 // Vector Rounding Shift.
 297 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 298 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 299 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 300
 301 // Vector Saturating Shift.
 302 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 303 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 304 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 305 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 306 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 307 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 308
 309 // Vector Saturating Rounding Shift.
 310 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 311 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 312 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 313 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 314 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 315
 316 // Vector Shift and Insert.
 317 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 318
 319 // Vector Absolute Value and Saturating Absolute Value.
 320 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 321 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 322
 323 // Vector Saturating Negate.
 324 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 325
 326 // Vector Count Leading Sign/Zero Bits.
 327 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 328 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 329
 330 // Vector Count One Bits.
 331 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 332
 333 // Vector Reciprocal Estimate.
 334 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 335
 336 // Vector Reciprocal Square Root Estimate.
 337 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 338
 339 // Vector Conversions Between Floating-point and Integer
 340 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 341 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 342 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 343 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 344 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 345 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 346 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 347 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 348
 349 // Vector Conversions Between Floating-point and Fixed-point.
 350 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 351 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 352 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 353 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 354
 355 // Vector Conversions Between Half-Precision and Single-Precision.
 356 def int_arm_neon_vcvtfp2hf
 357     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 358 def int_arm_neon_vcvthf2fp
 359     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 360
 361 // Narrowing Saturating Vector Moves.
 362 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 363 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 364 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 365
 366 // Vector Table Lookup.
 367 // The first 1-4 arguments are the table.
 368 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 369 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 370 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 371 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 372
 373 // Vector Table Extension.
 374 // Some elements of the destination vector may not be updated, so the original
 375 // value of that vector is passed as the first argument.  The next 1-4
 376 // arguments after that are the table.
 377 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 378 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 379 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 380 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 381
 382 // Vector Rounding
 383 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 384 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 385 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 386 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 387 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 388 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 389
 390 // De-interleaving vector loads from N-element structures.
 391 // Source operands are the address and alignment.
 392 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 393                                   [llvm_ptr_ty, llvm_i32_ty],
 394                                   [IntrReadArgMem]>;
 395 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 396                                   [llvm_ptr_ty, llvm_i32_ty],
 397                                   [IntrReadArgMem]>;
 398 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 399                                    LLVMMatchType<0>],
 400                                   [llvm_ptr_ty, llvm_i32_ty],
 401                                   [IntrReadArgMem]>;
 402 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 403                                    LLVMMatchType<0>, LLVMMatchType<0>],
 404                                   [llvm_ptr_ty, llvm_i32_ty],
 405                                   [IntrReadArgMem]>;
 406
 407 // Vector load N-element structure to one lane.
 408 // Source operands are: the address, the N input vectors (since only one
 409 // lane is assigned), the lane number, and the alignment.
 410 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 411                                       [llvm_ptr_ty, LLVMMatchType<0>,
 412                                        LLVMMatchType<0>, llvm_i32_ty,
 413                                        llvm_i32_ty], [IntrReadArgMem]>;
 414 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 415                                        LLVMMatchType<0>],
 416                                       [llvm_ptr_ty, LLVMMatchType<0>,
 417                                        LLVMMatchType<0>, LLVMMatchType<0>,
 418                                        llvm_i32_ty, llvm_i32_ty],
 419                                       [IntrReadArgMem]>;
 420 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 421                                        LLVMMatchType<0>, LLVMMatchType<0>],
 422                                       [llvm_ptr_ty, LLVMMatchType<0>,
 423                                        LLVMMatchType<0>, LLVMMatchType<0>,
 424                                        LLVMMatchType<0>, llvm_i32_ty,
 425                                        llvm_i32_ty], [IntrReadArgMem]>;
 426
 427 // Interleaving vector stores from N-element structures.
 428 // Source operands are: the address, the N vectors, and the alignment.
 429 def int_arm_neon_vst1 : Intrinsic<[],
 430                                   [llvm_ptr_ty, llvm_anyvector_ty,
 431                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 432 def int_arm_neon_vst2 : Intrinsic<[],
 433                                   [llvm_ptr_ty, llvm_anyvector_ty,
 434                                    LLVMMatchType<0>, llvm_i32_ty],
 435                                   [IntrReadWriteArgMem]>;
 436 def int_arm_neon_vst3 : Intrinsic<[],
 437                                   [llvm_ptr_ty, llvm_anyvector_ty,
 438                                    LLVMMatchType<0>, LLVMMatchType<0>,
 439                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 440 def int_arm_neon_vst4 : Intrinsic<[],
 441                                   [llvm_ptr_ty, llvm_anyvector_ty,
 442                                    LLVMMatchType<0>, LLVMMatchType<0>,
 443                                    LLVMMatchType<0>, llvm_i32_ty],
 444                                   [IntrReadWriteArgMem]>;
 445
 446 // Vector store N-element structure from one lane.
 447 // Source operands are: the address, the N vectors, the lane number, and
 448 // the alignment.
 449 def int_arm_neon_vst2lane : Intrinsic<[],
 450                                       [llvm_ptr_ty, llvm_anyvector_ty,
 451                                        LLVMMatchType<0>, llvm_i32_ty,
 452                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 453 def int_arm_neon_vst3lane : Intrinsic<[],
 454                                       [llvm_ptr_ty, llvm_anyvector_ty,
 455                                        LLVMMatchType<0>, LLVMMatchType<0>,
 456                                        llvm_i32_ty, llvm_i32_ty],
 457                                       [IntrReadWriteArgMem]>;
 458 def int_arm_neon_vst4lane : Intrinsic<[],
 459                                       [llvm_ptr_ty, llvm_anyvector_ty,
 460                                        LLVMMatchType<0>, LLVMMatchType<0>,
 461                                        LLVMMatchType<0>, llvm_i32_ty,
 462                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 463
 464 // Vector bitwise select.
 465 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 466                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 467                         [IntrNoMem]>;
 468
 469
 470 // Crypto instructions
 471 def int_arm_neon_aesd : Neon_2Arg_Intrinsic;
 472 def int_arm_neon_aese : Neon_2Arg_Intrinsic;
 473 def int_arm_neon_aesimc : Neon_1Arg_Intrinsic;
 474 def int_arm_neon_aesmc : Neon_1Arg_Intrinsic;
 475 def int_arm_neon_sha1h : Neon_1Arg_Intrinsic;
 476 def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic;
 477 def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic;
 478 def int_arm_neon_sha1c : Neon_3Arg_Intrinsic;
 479 def int_arm_neon_sha1m : Neon_3Arg_Intrinsic;
 480 def int_arm_neon_sha1p : Neon_3Arg_Intrinsic;
 481 def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic;
 482 def int_arm_neon_sha256h: Neon_3Arg_Intrinsic;
 483 def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic;
 484 def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic;
 485
 486 } // end TargetPrefix