include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41
  42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  44
  45 def int_arm_clrex : Intrinsic<[]>;
  46
  47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  48     llvm_ptr_ty]>;
  49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  50
  51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Data barrier instructions
  57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>;
  58 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // VFP
  62
  63 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  64                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  65 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  66                        Intrinsic<[], [llvm_i32_ty], []>;
  67 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  68                                   [IntrNoMem]>;
  69 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  70                                   [IntrNoMem]>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Coprocessor
  74
  75 // Move to coprocessor
  76 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  77    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  79 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  80    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  82
  83 // Move from coprocessor
  84 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  85    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                              llvm_i32_ty, llvm_i32_ty], []>;
  87 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  88    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                              llvm_i32_ty, llvm_i32_ty], []>;
  90
  91 // Coprocessor data processing
  92 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  94                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  95 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  96    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 // Move from two registers to coprocessor
 100 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 //===----------------------------------------------------------------------===//
 108 // CRC32
 109
 110 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 111     [IntrNoMem]>;
 112 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 113     [IntrNoMem]>;
 114 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 115     [IntrNoMem]>;
 116 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 117     [IntrNoMem]>;
 118 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 119     [IntrNoMem]>;
 120 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 121     [IntrNoMem]>;
 122
 123 //===----------------------------------------------------------------------===//
 124 // HINT
 125
 126 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 127
 128 //===----------------------------------------------------------------------===//
 129 // RBIT
 130
 131 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 132
 133 //===----------------------------------------------------------------------===//
 134 // UND (reserved undefined sequence)
 135
 136 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 137
 138 //===----------------------------------------------------------------------===//
 139 // Advanced SIMD (NEON)
 140
 141 // The following classes do not correspond directly to GCC builtins.
 142 class Neon_1Arg_Intrinsic
 143   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 144 class Neon_1Arg_Narrow_Intrinsic
 145   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 146 class Neon_2Arg_Intrinsic
 147   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 148               [IntrNoMem]>;
 149 class Neon_2Arg_Narrow_Intrinsic
 150   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 151               [IntrNoMem]>;
 152 class Neon_2Arg_Long_Intrinsic
 153   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 154               [IntrNoMem]>;
 155 class Neon_3Arg_Intrinsic
 156   : Intrinsic<[llvm_anyvector_ty],
 157               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 158               [IntrNoMem]>;
 159 class Neon_3Arg_Long_Intrinsic
 160   : Intrinsic<[llvm_anyvector_ty],
 161               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 162               [IntrNoMem]>;
 163 class Neon_CvtFxToFP_Intrinsic
 164   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 165 class Neon_CvtFPToFx_Intrinsic
 166   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 167 class Neon_CvtFPtoInt_1Arg_Intrinsic
 168   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 169
 170 class Neon_Compare_Intrinsic
 171   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 172               [IntrNoMem]>;
 173
 174 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 175 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 176 // Overall, the classes range from 2 to 6 v8i8 arguments.
 177 class Neon_Tbl2Arg_Intrinsic
 178   : Intrinsic<[llvm_v8i8_ty],
 179               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 180 class Neon_Tbl3Arg_Intrinsic
 181   : Intrinsic<[llvm_v8i8_ty],
 182               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 183 class Neon_Tbl4Arg_Intrinsic
 184   : Intrinsic<[llvm_v8i8_ty],
 185               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 186               [IntrNoMem]>;
 187 class Neon_Tbl5Arg_Intrinsic
 188   : Intrinsic<[llvm_v8i8_ty],
 189               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 190                llvm_v8i8_ty], [IntrNoMem]>;
 191 class Neon_Tbl6Arg_Intrinsic
 192   : Intrinsic<[llvm_v8i8_ty],
 193               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 194                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 195
 196 // Arithmetic ops
 197
 198 let Properties = [IntrNoMem, Commutative] in {
 199
 200   // Vector Add.
 201   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 202   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 203   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 204   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 205   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 206   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 207   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 208
 209   // Vector Multiply.
 210   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 211   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 212   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 213   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 214   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 215   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 216   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 217
 218   // Vector Maximum.
 219   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 220   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 221   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 222
 223   // Vector Minimum.
 224   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 225   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 226   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 227
 228   // Vector Reciprocal Step.
 229   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 230
 231   // Vector Reciprocal Square Root Step.
 232   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 233 }
 234
 235 // Vector Subtract.
 236 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 237 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 238 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 239 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 240 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 241
 242 // Vector Absolute Compare.
 243 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 244 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 245
 246 // Vector Absolute Differences.
 247 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 248 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 249
 250 // Vector Pairwise Add.
 251 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 252
 253 // Vector Pairwise Add Long.
 254 // Note: This is different than the other "long" NEON intrinsics because
 255 // the result vector has half as many elements as the source vector.
 256 // The source and destination vector types must be specified separately.
 257 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 258                                      [IntrNoMem]>;
 259 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 260                                      [IntrNoMem]>;
 261
 262 // Vector Pairwise Add and Accumulate Long.
 263 // Note: This is similar to vpaddl but the destination vector also appears
 264 // as the first argument.
 265 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 266                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 267                                      [IntrNoMem]>;
 268 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 269                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 270                                      [IntrNoMem]>;
 271
 272 // Vector Pairwise Maximum and Minimum.
 273 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 274 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 275 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 276 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 277
 278 // Vector Shifts:
 279 //
 280 // The various saturating and rounding vector shift operations need to be
 281 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 282 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 283 // be used for both left and right shifts, or even combinations of the two,
 284 // depending on the signs of the shift amounts.  It also has well-defined
 285 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 286 // by constants can be represented with LLVM's shift operators.
 287 //
 288 // The shift counts for these intrinsics are always vectors, even for constant
 289 // shifts, where the constant is replicated.  For consistency with VSHL (and
 290 // other variable shift instructions), left shifts have positive shift counts
 291 // and right shifts have negative shift counts.  This convention is also used
 292 // for constant right shift intrinsics, and to help preserve sanity, the
 293 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 294 // applicable, signed and unsigned versions of the intrinsics are
 295 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 296 // such as VQSHLU, take signed operands but produce unsigned results; these
 297 // use a "su" suffix.
 298
 299 // Vector Shift.
 300 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 301 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 302
 303 // Vector Rounding Shift.
 304 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 305 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 306 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 307
 308 // Vector Saturating Shift.
 309 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 310 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 311 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 312 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 313 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 314 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 315
 316 // Vector Saturating Rounding Shift.
 317 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 318 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 319 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 320 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 321 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 322
 323 // Vector Shift and Insert.
 324 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 325
 326 // Vector Absolute Value and Saturating Absolute Value.
 327 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 328 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 329
 330 // Vector Saturating Negate.
 331 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 332
 333 // Vector Count Leading Sign/Zero Bits.
 334 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 335 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 336
 337 // Vector Count One Bits.
 338 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 339
 340 // Vector Reciprocal Estimate.
 341 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 342
 343 // Vector Reciprocal Square Root Estimate.
 344 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 345
 346 // Vector Conversions Between Floating-point and Integer
 347 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 348 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 349 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 350 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 351 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 352 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 353 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 354 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 355
 356 // Vector Conversions Between Floating-point and Fixed-point.
 357 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 358 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 359 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 360 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 361
 362 // Vector Conversions Between Half-Precision and Single-Precision.
 363 def int_arm_neon_vcvtfp2hf
 364     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 365 def int_arm_neon_vcvthf2fp
 366     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 367
 368 // Narrowing Saturating Vector Moves.
 369 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 370 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 371 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 372
 373 // Vector Table Lookup.
 374 // The first 1-4 arguments are the table.
 375 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 376 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 377 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 378 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 379
 380 // Vector Table Extension.
 381 // Some elements of the destination vector may not be updated, so the original
 382 // value of that vector is passed as the first argument.  The next 1-4
 383 // arguments after that are the table.
 384 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 385 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 386 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 387 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 388
 389 // Vector Rounding
 390 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 391 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 392 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 393 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 394 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 395 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 396
 397 // De-interleaving vector loads from N-element structures.
 398 // Source operands are the address and alignment.
 399 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 400                                   [llvm_ptr_ty, llvm_i32_ty],
 401                                   [IntrReadArgMem]>;
 402 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 403                                   [llvm_ptr_ty, llvm_i32_ty],
 404                                   [IntrReadArgMem]>;
 405 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 406                                    LLVMMatchType<0>],
 407                                   [llvm_ptr_ty, llvm_i32_ty],
 408                                   [IntrReadArgMem]>;
 409 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 410                                    LLVMMatchType<0>, LLVMMatchType<0>],
 411                                   [llvm_ptr_ty, llvm_i32_ty],
 412                                   [IntrReadArgMem]>;
 413
 414 // Vector load N-element structure to one lane.
 415 // Source operands are: the address, the N input vectors (since only one
 416 // lane is assigned), the lane number, and the alignment.
 417 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 418                                       [llvm_ptr_ty, LLVMMatchType<0>,
 419                                        LLVMMatchType<0>, llvm_i32_ty,
 420                                        llvm_i32_ty], [IntrReadArgMem]>;
 421 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 422                                        LLVMMatchType<0>],
 423                                       [llvm_ptr_ty, LLVMMatchType<0>,
 424                                        LLVMMatchType<0>, LLVMMatchType<0>,
 425                                        llvm_i32_ty, llvm_i32_ty],
 426                                       [IntrReadArgMem]>;
 427 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 428                                        LLVMMatchType<0>, LLVMMatchType<0>],
 429                                       [llvm_ptr_ty, LLVMMatchType<0>,
 430                                        LLVMMatchType<0>, LLVMMatchType<0>,
 431                                        LLVMMatchType<0>, llvm_i32_ty,
 432                                        llvm_i32_ty], [IntrReadArgMem]>;
 433
 434 // Interleaving vector stores from N-element structures.
 435 // Source operands are: the address, the N vectors, and the alignment.
 436 def int_arm_neon_vst1 : Intrinsic<[],
 437                                   [llvm_ptr_ty, llvm_anyvector_ty,
 438                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 439 def int_arm_neon_vst2 : Intrinsic<[],
 440                                   [llvm_ptr_ty, llvm_anyvector_ty,
 441                                    LLVMMatchType<0>, llvm_i32_ty],
 442                                   [IntrReadWriteArgMem]>;
 443 def int_arm_neon_vst3 : Intrinsic<[],
 444                                   [llvm_ptr_ty, llvm_anyvector_ty,
 445                                    LLVMMatchType<0>, LLVMMatchType<0>,
 446                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 447 def int_arm_neon_vst4 : Intrinsic<[],
 448                                   [llvm_ptr_ty, llvm_anyvector_ty,
 449                                    LLVMMatchType<0>, LLVMMatchType<0>,
 450                                    LLVMMatchType<0>, llvm_i32_ty],
 451                                   [IntrReadWriteArgMem]>;
 452
 453 // Vector store N-element structure from one lane.
 454 // Source operands are: the address, the N vectors, the lane number, and
 455 // the alignment.
 456 def int_arm_neon_vst2lane : Intrinsic<[],
 457                                       [llvm_ptr_ty, llvm_anyvector_ty,
 458                                        LLVMMatchType<0>, llvm_i32_ty,
 459                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 460 def int_arm_neon_vst3lane : Intrinsic<[],
 461                                       [llvm_ptr_ty, llvm_anyvector_ty,
 462                                        LLVMMatchType<0>, LLVMMatchType<0>,
 463                                        llvm_i32_ty, llvm_i32_ty],
 464                                       [IntrReadWriteArgMem]>;
 465 def int_arm_neon_vst4lane : Intrinsic<[],
 466                                       [llvm_ptr_ty, llvm_anyvector_ty,
 467                                        LLVMMatchType<0>, LLVMMatchType<0>,
 468                                        LLVMMatchType<0>, llvm_i32_ty,
 469                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 470
 471 // Vector bitwise select.
 472 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 473                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 474                         [IntrNoMem]>;
 475
 476
 477 // Crypto instructions
 478 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 479                                      [llvm_v16i8_ty], [IntrNoMem]>;
 480 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 481                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 482                                      [IntrNoMem]>;
 483
 484 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 485                                      [IntrNoMem]>;
 486 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 487                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 488                                      [IntrNoMem]>;
 489 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 490                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 491                                    [IntrNoMem]>;
 492 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 493                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 494                                    [IntrNoMem]>;
 495
 496 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 497 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 498 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 499 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 500 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 501 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 502 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 503 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 504 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 505 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 506 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 507 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 508 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 509 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 510
 511 } // end TargetPrefix