include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41 def int_arm_clrex : Intrinsic<[]>;
  42
  43 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  44     llvm_ptr_ty]>;
  45 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  46
  47 //===----------------------------------------------------------------------===//
  48 // Data barrier instructions
  49 def int_arm_dmb : Intrinsic<[], [llvm_i32_ty]>;
  50 def int_arm_dsb : Intrinsic<[], [llvm_i32_ty]>;
  51
  52 //===----------------------------------------------------------------------===//
  53 // VFP
  54
  55 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  56                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  57 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  58                        Intrinsic<[], [llvm_i32_ty], []>;
  59 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  60                                   [IntrNoMem]>;
  61 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  62                                   [IntrNoMem]>;
  63
  64 //===----------------------------------------------------------------------===//
  65 // Coprocessor
  66
  67 // Move to coprocessor
  68 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  69    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  70                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  71 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  72    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  73                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  74
  75 // Move from coprocessor
  76 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  77    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                              llvm_i32_ty, llvm_i32_ty], []>;
  79 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  80    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                              llvm_i32_ty, llvm_i32_ty], []>;
  82
  83 // Coprocessor data processing
  84 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  85    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  87 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  90
  91 // Move from two registers to coprocessor
  92 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  94                   llvm_i32_ty, llvm_i32_ty], []>;
  95 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
  96    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                   llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 //===----------------------------------------------------------------------===//
 100 // Advanced SIMD (NEON)
 101
 102 // The following classes do not correspond directly to GCC builtins.
 103 class Neon_1Arg_Intrinsic
 104   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 105 class Neon_1Arg_Narrow_Intrinsic
 106   : Intrinsic<[llvm_anyvector_ty],
 107               [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
 108 class Neon_2Arg_Intrinsic
 109   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 110               [IntrNoMem]>;
 111 class Neon_2Arg_Narrow_Intrinsic
 112   : Intrinsic<[llvm_anyvector_ty],
 113               [LLVMExtendedElementVectorType<0>,
 114                LLVMExtendedElementVectorType<0>],
 115               [IntrNoMem]>;
 116 class Neon_2Arg_Long_Intrinsic
 117   : Intrinsic<[llvm_anyvector_ty],
 118               [LLVMTruncatedElementVectorType<0>,
 119                LLVMTruncatedElementVectorType<0>],
 120               [IntrNoMem]>;
 121 class Neon_3Arg_Intrinsic
 122   : Intrinsic<[llvm_anyvector_ty],
 123               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 124               [IntrNoMem]>;
 125 class Neon_3Arg_Long_Intrinsic
 126   : Intrinsic<[llvm_anyvector_ty],
 127               [LLVMMatchType<0>,
 128                LLVMTruncatedElementVectorType<0>,
 129                LLVMTruncatedElementVectorType<0>],
 130               [IntrNoMem]>;
 131 class Neon_CvtFxToFP_Intrinsic
 132   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 133 class Neon_CvtFPToFx_Intrinsic
 134   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 135 class Neon_CvtFPtoInt_1Arg_Intrinsic
 136   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 137
 138 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 139 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 140 // Overall, the classes range from 2 to 6 v8i8 arguments.
 141 class Neon_Tbl2Arg_Intrinsic
 142   : Intrinsic<[llvm_v8i8_ty],
 143               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 144 class Neon_Tbl3Arg_Intrinsic
 145   : Intrinsic<[llvm_v8i8_ty],
 146               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 147 class Neon_Tbl4Arg_Intrinsic
 148   : Intrinsic<[llvm_v8i8_ty],
 149               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 150               [IntrNoMem]>;
 151 class Neon_Tbl5Arg_Intrinsic
 152   : Intrinsic<[llvm_v8i8_ty],
 153               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 154                llvm_v8i8_ty], [IntrNoMem]>;
 155 class Neon_Tbl6Arg_Intrinsic
 156   : Intrinsic<[llvm_v8i8_ty],
 157               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 158                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 159
 160 // Arithmetic ops
 161
 162 let Properties = [IntrNoMem, Commutative] in {
 163
 164   // Vector Add.
 165   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 166   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 167   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 168   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 169   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 170   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 171   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 172
 173   // Vector Multiply.
 174   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 175   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 176   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 177   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 178   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 179   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 180   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 181
 182   // Vector Maximum.
 183   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 184   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 185   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 186
 187   // Vector Minimum.
 188   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 189   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 190   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 191
 192   // Vector Reciprocal Step.
 193   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 194
 195   // Vector Reciprocal Square Root Step.
 196   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 197 }
 198
 199 // Vector Subtract.
 200 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 201 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 202 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 203 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 204 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 205
 206 // Vector Absolute Compare.
 207 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
 208                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 209                                     [IntrNoMem]>;
 210 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
 211                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 212                                     [IntrNoMem]>;
 213 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
 214                                     [llvm_v2f32_ty, llvm_v2f32_ty],
 215                                     [IntrNoMem]>;
 216 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
 217                                     [llvm_v4f32_ty, llvm_v4f32_ty],
 218                                     [IntrNoMem]>;
 219
 220 // Vector Absolute Differences.
 221 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 222 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 223
 224 // Vector Pairwise Add.
 225 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 226
 227 // Vector Pairwise Add Long.
 228 // Note: This is different than the other "long" NEON intrinsics because
 229 // the result vector has half as many elements as the source vector.
 230 // The source and destination vector types must be specified separately.
 231 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 232                                      [IntrNoMem]>;
 233 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 234                                      [IntrNoMem]>;
 235
 236 // Vector Pairwise Add and Accumulate Long.
 237 // Note: This is similar to vpaddl but the destination vector also appears
 238 // as the first argument.
 239 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 240                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 241                                      [IntrNoMem]>;
 242 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 243                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 244                                      [IntrNoMem]>;
 245
 246 // Vector Pairwise Maximum and Minimum.
 247 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 248 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 249 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 250 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 251
 252 // Vector Shifts:
 253 //
 254 // The various saturating and rounding vector shift operations need to be
 255 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 256 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 257 // be used for both left and right shifts, or even combinations of the two,
 258 // depending on the signs of the shift amounts.  It also has well-defined
 259 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 260 // by constants can be represented with LLVM's shift operators.
 261 //
 262 // The shift counts for these intrinsics are always vectors, even for constant
 263 // shifts, where the constant is replicated.  For consistency with VSHL (and
 264 // other variable shift instructions), left shifts have positive shift counts
 265 // and right shifts have negative shift counts.  This convention is also used
 266 // for constant right shift intrinsics, and to help preserve sanity, the
 267 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 268 // applicable, signed and unsigned versions of the intrinsics are
 269 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 270 // such as VQSHLU, take signed operands but produce unsigned results; these
 271 // use a "su" suffix.
 272
 273 // Vector Shift.
 274 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 275 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 276 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
 277 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
 278 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
 279
 280 // Vector Rounding Shift.
 281 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 282 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 283 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 284
 285 // Vector Saturating Shift.
 286 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 287 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 288 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 289 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 290 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 291 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 292
 293 // Vector Saturating Rounding Shift.
 294 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 295 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 296 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 297 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 298 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 299
 300 // Vector Shift and Insert.
 301 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 302
 303 // Vector Absolute Value and Saturating Absolute Value.
 304 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 305 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 306
 307 // Vector Saturating Negate.
 308 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 309
 310 // Vector Count Leading Sign/Zero Bits.
 311 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 312 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 313
 314 // Vector Count One Bits.
 315 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 316
 317 // Vector Reciprocal Estimate.
 318 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 319
 320 // Vector Reciprocal Square Root Estimate.
 321 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 322
 323 // Vector Conversions Between Floating-point and Integer
 324 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 325 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 326 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 327 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 328 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 329 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 330 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 331 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 332
 333 // Vector Conversions Between Floating-point and Fixed-point.
 334 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 335 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 336 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 337 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 338
 339 // Vector Conversions Between Half-Precision and Single-Precision.
 340 def int_arm_neon_vcvtfp2hf
 341     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 342 def int_arm_neon_vcvthf2fp
 343     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 344
 345 // Narrowing Saturating Vector Moves.
 346 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 347 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 348 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 349
 350 // Vector Table Lookup.
 351 // The first 1-4 arguments are the table.
 352 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 353 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 354 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 355 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 356
 357 // Vector Table Extension.
 358 // Some elements of the destination vector may not be updated, so the original
 359 // value of that vector is passed as the first argument.  The next 1-4
 360 // arguments after that are the table.
 361 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 362 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 363 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 364 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 365
 366 // Vector Rounding
 367 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 368 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 369 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 370 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 371 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 372 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 373
 374 // De-interleaving vector loads from N-element structures.
 375 // Source operands are the address and alignment.
 376 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 377                                   [llvm_ptr_ty, llvm_i32_ty],
 378                                   [IntrReadArgMem]>;
 379 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 380                                   [llvm_ptr_ty, llvm_i32_ty],
 381                                   [IntrReadArgMem]>;
 382 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 383                                    LLVMMatchType<0>],
 384                                   [llvm_ptr_ty, llvm_i32_ty],
 385                                   [IntrReadArgMem]>;
 386 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 387                                    LLVMMatchType<0>, LLVMMatchType<0>],
 388                                   [llvm_ptr_ty, llvm_i32_ty],
 389                                   [IntrReadArgMem]>;
 390
 391 // Vector load N-element structure to one lane.
 392 // Source operands are: the address, the N input vectors (since only one
 393 // lane is assigned), the lane number, and the alignment.
 394 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 395                                       [llvm_ptr_ty, LLVMMatchType<0>,
 396                                        LLVMMatchType<0>, llvm_i32_ty,
 397                                        llvm_i32_ty], [IntrReadArgMem]>;
 398 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 399                                        LLVMMatchType<0>],
 400                                       [llvm_ptr_ty, LLVMMatchType<0>,
 401                                        LLVMMatchType<0>, LLVMMatchType<0>,
 402                                        llvm_i32_ty, llvm_i32_ty],
 403                                       [IntrReadArgMem]>;
 404 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 405                                        LLVMMatchType<0>, LLVMMatchType<0>],
 406                                       [llvm_ptr_ty, LLVMMatchType<0>,
 407                                        LLVMMatchType<0>, LLVMMatchType<0>,
 408                                        LLVMMatchType<0>, llvm_i32_ty,
 409                                        llvm_i32_ty], [IntrReadArgMem]>;
 410
 411 // Interleaving vector stores from N-element structures.
 412 // Source operands are: the address, the N vectors, and the alignment.
 413 def int_arm_neon_vst1 : Intrinsic<[],
 414                                   [llvm_ptr_ty, llvm_anyvector_ty,
 415                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 416 def int_arm_neon_vst2 : Intrinsic<[],
 417                                   [llvm_ptr_ty, llvm_anyvector_ty,
 418                                    LLVMMatchType<0>, llvm_i32_ty],
 419                                   [IntrReadWriteArgMem]>;
 420 def int_arm_neon_vst3 : Intrinsic<[],
 421                                   [llvm_ptr_ty, llvm_anyvector_ty,
 422                                    LLVMMatchType<0>, LLVMMatchType<0>,
 423                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 424 def int_arm_neon_vst4 : Intrinsic<[],
 425                                   [llvm_ptr_ty, llvm_anyvector_ty,
 426                                    LLVMMatchType<0>, LLVMMatchType<0>,
 427                                    LLVMMatchType<0>, llvm_i32_ty],
 428                                   [IntrReadWriteArgMem]>;
 429
 430 // Vector store N-element structure from one lane.
 431 // Source operands are: the address, the N vectors, the lane number, and
 432 // the alignment.
 433 def int_arm_neon_vst2lane : Intrinsic<[],
 434                                       [llvm_ptr_ty, llvm_anyvector_ty,
 435                                        LLVMMatchType<0>, llvm_i32_ty,
 436                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 437 def int_arm_neon_vst3lane : Intrinsic<[],
 438                                       [llvm_ptr_ty, llvm_anyvector_ty,
 439                                        LLVMMatchType<0>, LLVMMatchType<0>,
 440                                        llvm_i32_ty, llvm_i32_ty],
 441                                       [IntrReadWriteArgMem]>;
 442 def int_arm_neon_vst4lane : Intrinsic<[],
 443                                       [llvm_ptr_ty, llvm_anyvector_ty,
 444                                        LLVMMatchType<0>, LLVMMatchType<0>,
 445                                        LLVMMatchType<0>, llvm_i32_ty,
 446                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 447
 448 // Vector bitwise select.
 449 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 450                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 451                         [IntrNoMem]>;
 452
 453 } // end TargetPrefix