include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmetic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41
  42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  44
  45 def int_arm_clrex : Intrinsic<[]>;
  46
  47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  48     llvm_ptr_ty]>;
  49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  50
  51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Data barrier instructions
  57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
  58                   Intrinsic<[], [llvm_i32_ty]>;
  59 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
  60                   Intrinsic<[], [llvm_i32_ty]>;
  61 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
  62                   Intrinsic<[], [llvm_i32_ty]>;
  63
  64 //===----------------------------------------------------------------------===//
  65 // VFP
  66
  67 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  68                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  69 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  70                        Intrinsic<[], [llvm_i32_ty], []>;
  71 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  72                                   [IntrNoMem]>;
  73 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  74                                   [IntrNoMem]>;
  75
  76 //===----------------------------------------------------------------------===//
  77 // Coprocessor
  78
  79 // Move to coprocessor
  80 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  81                   MSBuiltin<"_MoveToCoprocessor">,
  82    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  83                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  84 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  85                    MSBuiltin<"_MoveToCoprocessor2">,
  86    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  87                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  88
  89 // Move from coprocessor
  90 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  91                   MSBuiltin<"_MoveFromCoprocessor">,
  92    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  93                              llvm_i32_ty, llvm_i32_ty], []>;
  94 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  95                    MSBuiltin<"_MoveFromCoprocessor2">,
  96    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                              llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 // Coprocessor data processing
 100 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 // Move from two registers to coprocessor
 108 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 109    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 110                   llvm_i32_ty, llvm_i32_ty], []>;
 111 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 112    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 113                   llvm_i32_ty, llvm_i32_ty], []>;
 114
 115 //===----------------------------------------------------------------------===//
 116 // CRC32
 117
 118 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 119     [IntrNoMem]>;
 120 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 121     [IntrNoMem]>;
 122 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 123     [IntrNoMem]>;
 124 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 125     [IntrNoMem]>;
 126 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 127     [IntrNoMem]>;
 128 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 129     [IntrNoMem]>;
 130
 131 //===----------------------------------------------------------------------===//
 132 // HINT
 133
 134 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 135 def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
 136
 137 //===----------------------------------------------------------------------===//
 138 // RBIT
 139
 140 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 141
 142 //===----------------------------------------------------------------------===//
 143 // UND (reserved undefined sequence)
 144
 145 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 146
 147 //===----------------------------------------------------------------------===//
 148 // Advanced SIMD (NEON)
 149
 150 // The following classes do not correspond directly to GCC builtins.
 151 class Neon_1Arg_Intrinsic
 152   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 153 class Neon_1Arg_Narrow_Intrinsic
 154   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 155 class Neon_2Arg_Intrinsic
 156   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 157               [IntrNoMem]>;
 158 class Neon_2Arg_Narrow_Intrinsic
 159   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 160               [IntrNoMem]>;
 161 class Neon_2Arg_Long_Intrinsic
 162   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 163               [IntrNoMem]>;
 164 class Neon_3Arg_Intrinsic
 165   : Intrinsic<[llvm_anyvector_ty],
 166               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 167               [IntrNoMem]>;
 168 class Neon_3Arg_Long_Intrinsic
 169   : Intrinsic<[llvm_anyvector_ty],
 170               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 171               [IntrNoMem]>;
 172 class Neon_CvtFxToFP_Intrinsic
 173   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 174 class Neon_CvtFPToFx_Intrinsic
 175   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 176 class Neon_CvtFPtoInt_1Arg_Intrinsic
 177   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 178
 179 class Neon_Compare_Intrinsic
 180   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 181               [IntrNoMem]>;
 182
 183 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 184 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 185 // Overall, the classes range from 2 to 6 v8i8 arguments.
 186 class Neon_Tbl2Arg_Intrinsic
 187   : Intrinsic<[llvm_v8i8_ty],
 188               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 189 class Neon_Tbl3Arg_Intrinsic
 190   : Intrinsic<[llvm_v8i8_ty],
 191               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 192 class Neon_Tbl4Arg_Intrinsic
 193   : Intrinsic<[llvm_v8i8_ty],
 194               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 195               [IntrNoMem]>;
 196 class Neon_Tbl5Arg_Intrinsic
 197   : Intrinsic<[llvm_v8i8_ty],
 198               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 199                llvm_v8i8_ty], [IntrNoMem]>;
 200 class Neon_Tbl6Arg_Intrinsic
 201   : Intrinsic<[llvm_v8i8_ty],
 202               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 203                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 204
 205 // Arithmetic ops
 206
 207 let Properties = [IntrNoMem, Commutative] in {
 208
 209   // Vector Add.
 210   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 211   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 212   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 213   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 214   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 215   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 216   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 217
 218   // Vector Multiply.
 219   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 220   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 221   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 222   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 223   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 224   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 225   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 226
 227   // Vector Maximum.
 228   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 229   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 230   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 231
 232   // Vector Minimum.
 233   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 234   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 235   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 236
 237   // Vector Reciprocal Step.
 238   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 239
 240   // Vector Reciprocal Square Root Step.
 241   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 242 }
 243
 244 // Vector Subtract.
 245 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 246 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 247 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 248 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 249 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 250
 251 // Vector Absolute Compare.
 252 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 253 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 254
 255 // Vector Absolute Differences.
 256 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 257 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 258
 259 // Vector Pairwise Add.
 260 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 261
 262 // Vector Pairwise Add Long.
 263 // Note: This is different than the other "long" NEON intrinsics because
 264 // the result vector has half as many elements as the source vector.
 265 // The source and destination vector types must be specified separately.
 266 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 267                                      [IntrNoMem]>;
 268 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 269                                      [IntrNoMem]>;
 270
 271 // Vector Pairwise Add and Accumulate Long.
 272 // Note: This is similar to vpaddl but the destination vector also appears
 273 // as the first argument.
 274 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 275                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 276                                      [IntrNoMem]>;
 277 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 278                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 279                                      [IntrNoMem]>;
 280
 281 // Vector Pairwise Maximum and Minimum.
 282 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 283 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 284 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 285 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 286
 287 // Vector Shifts:
 288 //
 289 // The various saturating and rounding vector shift operations need to be
 290 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 291 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 292 // be used for both left and right shifts, or even combinations of the two,
 293 // depending on the signs of the shift amounts.  It also has well-defined
 294 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 295 // by constants can be represented with LLVM's shift operators.
 296 //
 297 // The shift counts for these intrinsics are always vectors, even for constant
 298 // shifts, where the constant is replicated.  For consistency with VSHL (and
 299 // other variable shift instructions), left shifts have positive shift counts
 300 // and right shifts have negative shift counts.  This convention is also used
 301 // for constant right shift intrinsics, and to help preserve sanity, the
 302 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 303 // applicable, signed and unsigned versions of the intrinsics are
 304 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 305 // such as VQSHLU, take signed operands but produce unsigned results; these
 306 // use a "su" suffix.
 307
 308 // Vector Shift.
 309 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 310 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 311
 312 // Vector Rounding Shift.
 313 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 314 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 315 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 316
 317 // Vector Saturating Shift.
 318 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 319 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 320 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 321 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 322 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 323 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 324
 325 // Vector Saturating Rounding Shift.
 326 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 327 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 328 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 329 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 330 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 331
 332 // Vector Shift and Insert.
 333 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 334
 335 // Vector Absolute Value and Saturating Absolute Value.
 336 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 337 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 338
 339 // Vector Saturating Negate.
 340 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 341
 342 // Vector Count Leading Sign/Zero Bits.
 343 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 344
 345 // Vector Reciprocal Estimate.
 346 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 347
 348 // Vector Reciprocal Square Root Estimate.
 349 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 350
 351 // Vector Conversions Between Floating-point and Integer
 352 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 353 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 354 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 355 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 356 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 357 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 358 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 359 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 360
 361 // Vector Conversions Between Floating-point and Fixed-point.
 362 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 363 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 364 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 365 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 366
 367 // Vector Conversions Between Half-Precision and Single-Precision.
 368 def int_arm_neon_vcvtfp2hf
 369     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 370 def int_arm_neon_vcvthf2fp
 371     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 372
 373 // Narrowing Saturating Vector Moves.
 374 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 375 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 376 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 377
 378 // Vector Table Lookup.
 379 // The first 1-4 arguments are the table.
 380 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 381 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 382 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 383 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 384
 385 // Vector Table Extension.
 386 // Some elements of the destination vector may not be updated, so the original
 387 // value of that vector is passed as the first argument.  The next 1-4
 388 // arguments after that are the table.
 389 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 390 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 391 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 392 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 393
 394 // Vector Rounding
 395 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 396 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 397 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 398 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 399 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 400 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 401
 402 // De-interleaving vector loads from N-element structures.
 403 // Source operands are the address and alignment.
 404 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 405                                   [llvm_ptr_ty, llvm_i32_ty],
 406                                   [IntrReadArgMem]>;
 407 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 408                                   [llvm_ptr_ty, llvm_i32_ty],
 409                                   [IntrReadArgMem]>;
 410 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 411                                    LLVMMatchType<0>],
 412                                   [llvm_ptr_ty, llvm_i32_ty],
 413                                   [IntrReadArgMem]>;
 414 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 415                                    LLVMMatchType<0>, LLVMMatchType<0>],
 416                                   [llvm_ptr_ty, llvm_i32_ty],
 417                                   [IntrReadArgMem]>;
 418
 419 // Vector load N-element structure to one lane.
 420 // Source operands are: the address, the N input vectors (since only one
 421 // lane is assigned), the lane number, and the alignment.
 422 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 423                                       [llvm_ptr_ty, LLVMMatchType<0>,
 424                                        LLVMMatchType<0>, llvm_i32_ty,
 425                                        llvm_i32_ty], [IntrReadArgMem]>;
 426 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 427                                        LLVMMatchType<0>],
 428                                       [llvm_ptr_ty, LLVMMatchType<0>,
 429                                        LLVMMatchType<0>, LLVMMatchType<0>,
 430                                        llvm_i32_ty, llvm_i32_ty],
 431                                       [IntrReadArgMem]>;
 432 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 433                                        LLVMMatchType<0>, LLVMMatchType<0>],
 434                                       [llvm_ptr_ty, LLVMMatchType<0>,
 435                                        LLVMMatchType<0>, LLVMMatchType<0>,
 436                                        LLVMMatchType<0>, llvm_i32_ty,
 437                                        llvm_i32_ty], [IntrReadArgMem]>;
 438
 439 // Interleaving vector stores from N-element structures.
 440 // Source operands are: the address, the N vectors, and the alignment.
 441 def int_arm_neon_vst1 : Intrinsic<[],
 442                                   [llvm_ptr_ty, llvm_anyvector_ty,
 443                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 444 def int_arm_neon_vst2 : Intrinsic<[],
 445                                   [llvm_ptr_ty, llvm_anyvector_ty,
 446                                    LLVMMatchType<0>, llvm_i32_ty],
 447                                   [IntrReadWriteArgMem]>;
 448 def int_arm_neon_vst3 : Intrinsic<[],
 449                                   [llvm_ptr_ty, llvm_anyvector_ty,
 450                                    LLVMMatchType<0>, LLVMMatchType<0>,
 451                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 452 def int_arm_neon_vst4 : Intrinsic<[],
 453                                   [llvm_ptr_ty, llvm_anyvector_ty,
 454                                    LLVMMatchType<0>, LLVMMatchType<0>,
 455                                    LLVMMatchType<0>, llvm_i32_ty],
 456                                   [IntrReadWriteArgMem]>;
 457
 458 // Vector store N-element structure from one lane.
 459 // Source operands are: the address, the N vectors, the lane number, and
 460 // the alignment.
 461 def int_arm_neon_vst2lane : Intrinsic<[],
 462                                       [llvm_ptr_ty, llvm_anyvector_ty,
 463                                        LLVMMatchType<0>, llvm_i32_ty,
 464                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 465 def int_arm_neon_vst3lane : Intrinsic<[],
 466                                       [llvm_ptr_ty, llvm_anyvector_ty,
 467                                        LLVMMatchType<0>, LLVMMatchType<0>,
 468                                        llvm_i32_ty, llvm_i32_ty],
 469                                       [IntrReadWriteArgMem]>;
 470 def int_arm_neon_vst4lane : Intrinsic<[],
 471                                       [llvm_ptr_ty, llvm_anyvector_ty,
 472                                        LLVMMatchType<0>, LLVMMatchType<0>,
 473                                        LLVMMatchType<0>, llvm_i32_ty,
 474                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 475
 476 // Vector bitwise select.
 477 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 478                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 479                         [IntrNoMem]>;
 480
 481
 482 // Crypto instructions
 483 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 484                                      [llvm_v16i8_ty], [IntrNoMem]>;
 485 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 486                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 487                                      [IntrNoMem]>;
 488
 489 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 490                                      [IntrNoMem]>;
 491 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 492                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 493                                      [IntrNoMem]>;
 494 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 495                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 496                                    [IntrNoMem]>;
 497 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 498                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 499                                    [IntrNoMem]>;
 500
 501 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 502 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 503 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 504 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 505 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 506 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 507 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 508 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 509 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 510 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 511 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 512 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 513 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 514 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 515
 516 } // end TargetPrefix