Move all of the header files which are involved in modelling the LLVM IR
[oota-llvm.git] / include / llvm / IR / IntrinsicsARM.td
1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines all of the ARM-specific intrinsics.
11 //
12 //===----------------------------------------------------------------------===//
13
14
15 //===----------------------------------------------------------------------===//
16 // TLS
17
18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
19
20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
22
23 //===----------------------------------------------------------------------===//
24 // Saturating Arithmentic
25
26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
28     [IntrNoMem, Commutative]>;
29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
35
36 //===----------------------------------------------------------------------===//
37 // Load and Store exclusive doubleword
38
39 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
40     llvm_ptr_ty], [IntrReadWriteArgMem]>;
41 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
42     [IntrReadArgMem]>;
43
44 //===----------------------------------------------------------------------===//
45 // VFP
46
47 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
48                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
49 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
50                        Intrinsic<[], [llvm_i32_ty], []>;
51 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
52                                   [IntrNoMem]>;
53 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
54                                   [IntrNoMem]>;
55
56 //===----------------------------------------------------------------------===//
57 // Coprocessor
58
59 // Move to coprocessor
60 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
61    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
62                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
63 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
64    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
65                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
66
67 // Move from coprocessor
68 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
69    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
70                              llvm_i32_ty, llvm_i32_ty], []>;
71 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
72    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
73                              llvm_i32_ty, llvm_i32_ty], []>;
74
75 // Coprocessor data processing
76 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
77    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
78                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
79 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
80    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
81                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
82
83 // Move from two registers to coprocessor
84 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
85    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
86                   llvm_i32_ty, llvm_i32_ty], []>;
87 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
88    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
89                   llvm_i32_ty, llvm_i32_ty], []>;
90
91 //===----------------------------------------------------------------------===//
92 // Advanced SIMD (NEON)
93
94 // The following classes do not correspond directly to GCC builtins.
95 class Neon_1Arg_Intrinsic
96   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
97 class Neon_1Arg_Narrow_Intrinsic
98   : Intrinsic<[llvm_anyvector_ty],
99               [LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
100 class Neon_2Arg_Intrinsic
101   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
102               [IntrNoMem]>;
103 class Neon_2Arg_Narrow_Intrinsic
104   : Intrinsic<[llvm_anyvector_ty],
105               [LLVMExtendedElementVectorType<0>,
106                LLVMExtendedElementVectorType<0>],
107               [IntrNoMem]>;
108 class Neon_2Arg_Long_Intrinsic
109   : Intrinsic<[llvm_anyvector_ty],
110               [LLVMTruncatedElementVectorType<0>,
111                LLVMTruncatedElementVectorType<0>],
112               [IntrNoMem]>;
113 class Neon_3Arg_Intrinsic
114   : Intrinsic<[llvm_anyvector_ty],
115               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
116               [IntrNoMem]>;
117 class Neon_3Arg_Long_Intrinsic
118   : Intrinsic<[llvm_anyvector_ty],
119               [LLVMMatchType<0>,
120                LLVMTruncatedElementVectorType<0>,
121                LLVMTruncatedElementVectorType<0>],
122               [IntrNoMem]>;
123 class Neon_CvtFxToFP_Intrinsic
124   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
125 class Neon_CvtFPToFx_Intrinsic
126   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
127
128 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
129 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
130 // Overall, the classes range from 2 to 6 v8i8 arguments.
131 class Neon_Tbl2Arg_Intrinsic
132   : Intrinsic<[llvm_v8i8_ty],
133               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
134 class Neon_Tbl3Arg_Intrinsic
135   : Intrinsic<[llvm_v8i8_ty],
136               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
137 class Neon_Tbl4Arg_Intrinsic
138   : Intrinsic<[llvm_v8i8_ty],
139               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
140               [IntrNoMem]>;
141 class Neon_Tbl5Arg_Intrinsic
142   : Intrinsic<[llvm_v8i8_ty],
143               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
144                llvm_v8i8_ty], [IntrNoMem]>;
145 class Neon_Tbl6Arg_Intrinsic
146   : Intrinsic<[llvm_v8i8_ty],
147               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
148                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
149
150 // Arithmetic ops
151
152 let Properties = [IntrNoMem, Commutative] in {
153
154   // Vector Add.
155   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
156   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
157   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
158   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
159   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
160   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
161   def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
162   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
163
164   // Vector Multiply.
165   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
166   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
167   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
168   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
169   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
170   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
171   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
172
173   // Vector Multiply and Accumulate/Subtract.
174   def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
175   def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
176
177   // Vector Maximum.
178   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
179   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
180
181   // Vector Minimum.
182   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
183   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
184
185   // Vector Reciprocal Step.
186   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
187
188   // Vector Reciprocal Square Root Step.
189   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
190 }
191
192 // Vector Subtract.
193 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
194 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
195 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
196 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
197 def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
198 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
199
200 // Vector Absolute Compare.
201 def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
202                                     [llvm_v2f32_ty, llvm_v2f32_ty],
203                                     [IntrNoMem]>;
204 def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
205                                     [llvm_v4f32_ty, llvm_v4f32_ty],
206                                     [IntrNoMem]>;
207 def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
208                                     [llvm_v2f32_ty, llvm_v2f32_ty],
209                                     [IntrNoMem]>;
210 def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
211                                     [llvm_v4f32_ty, llvm_v4f32_ty],
212                                     [IntrNoMem]>;
213
214 // Vector Absolute Differences.
215 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
216 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
217
218 // Vector Pairwise Add.
219 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
220
221 // Vector Pairwise Add Long.
222 // Note: This is different than the other "long" NEON intrinsics because
223 // the result vector has half as many elements as the source vector.
224 // The source and destination vector types must be specified separately.
225 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
226                                      [IntrNoMem]>;
227 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
228                                      [IntrNoMem]>;
229
230 // Vector Pairwise Add and Accumulate Long.
231 // Note: This is similar to vpaddl but the destination vector also appears
232 // as the first argument.
233 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
234                                      [LLVMMatchType<0>, llvm_anyvector_ty],
235                                      [IntrNoMem]>;
236 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
237                                      [LLVMMatchType<0>, llvm_anyvector_ty],
238                                      [IntrNoMem]>;
239
240 // Vector Pairwise Maximum and Minimum.
241 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
242 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
243 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
244 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
245
246 // Vector Shifts:
247 //
248 // The various saturating and rounding vector shift operations need to be
249 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
250 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
251 // be used for both left and right shifts, or even combinations of the two,
252 // depending on the signs of the shift amounts.  It also has well-defined
253 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
254 // by constants can be represented with LLVM's shift operators.
255 //
256 // The shift counts for these intrinsics are always vectors, even for constant
257 // shifts, where the constant is replicated.  For consistency with VSHL (and
258 // other variable shift instructions), left shifts have positive shift counts
259 // and right shifts have negative shift counts.  This convention is also used
260 // for constant right shift intrinsics, and to help preserve sanity, the
261 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
262 // applicable, signed and unsigned versions of the intrinsics are
263 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
264 // such as VQSHLU, take signed operands but produce unsigned results; these
265 // use a "su" suffix.
266
267 // Vector Shift.
268 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
269 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
270 def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic;
271 def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic;
272 def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic;
273
274 // Vector Rounding Shift.
275 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
276 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
277 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
278
279 // Vector Saturating Shift.
280 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
281 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
282 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
283 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
284 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
285 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
286
287 // Vector Saturating Rounding Shift.
288 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
289 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
290 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
291 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
292 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
293
294 // Vector Shift and Insert.
295 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
296
297 // Vector Absolute Value and Saturating Absolute Value.
298 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
299 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
300
301 // Vector Saturating Negate.
302 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
303
304 // Vector Count Leading Sign/Zero Bits.
305 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
306 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
307
308 // Vector Count One Bits.
309 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
310
311 // Vector Reciprocal Estimate.
312 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
313
314 // Vector Reciprocal Square Root Estimate.
315 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
316
317 // Vector Conversions Between Floating-point and Fixed-point.
318 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
319 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
320 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
321 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
322
323 // Vector Conversions Between Half-Precision and Single-Precision.
324 def int_arm_neon_vcvtfp2hf
325     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
326 def int_arm_neon_vcvthf2fp
327     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
328
329 // Narrowing Saturating Vector Moves.
330 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
331 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
332 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
333
334 // Vector Table Lookup.
335 // The first 1-4 arguments are the table.
336 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
337 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
338 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
339 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
340
341 // Vector Table Extension.
342 // Some elements of the destination vector may not be updated, so the original
343 // value of that vector is passed as the first argument.  The next 1-4
344 // arguments after that are the table.
345 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
346 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
347 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
348 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
349
350 // De-interleaving vector loads from N-element structures.
351 // Source operands are the address and alignment.
352 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
353                                   [llvm_ptr_ty, llvm_i32_ty],
354                                   [IntrReadArgMem]>;
355 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
356                                   [llvm_ptr_ty, llvm_i32_ty],
357                                   [IntrReadArgMem]>;
358 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
359                                    LLVMMatchType<0>],
360                                   [llvm_ptr_ty, llvm_i32_ty],
361                                   [IntrReadArgMem]>;
362 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
363                                    LLVMMatchType<0>, LLVMMatchType<0>],
364                                   [llvm_ptr_ty, llvm_i32_ty],
365                                   [IntrReadArgMem]>;
366
367 // Vector load N-element structure to one lane.
368 // Source operands are: the address, the N input vectors (since only one
369 // lane is assigned), the lane number, and the alignment.
370 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
371                                       [llvm_ptr_ty, LLVMMatchType<0>,
372                                        LLVMMatchType<0>, llvm_i32_ty,
373                                        llvm_i32_ty], [IntrReadArgMem]>;
374 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
375                                        LLVMMatchType<0>],
376                                       [llvm_ptr_ty, LLVMMatchType<0>,
377                                        LLVMMatchType<0>, LLVMMatchType<0>,
378                                        llvm_i32_ty, llvm_i32_ty],
379                                       [IntrReadArgMem]>;
380 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
381                                        LLVMMatchType<0>, LLVMMatchType<0>],
382                                       [llvm_ptr_ty, LLVMMatchType<0>,
383                                        LLVMMatchType<0>, LLVMMatchType<0>,
384                                        LLVMMatchType<0>, llvm_i32_ty,
385                                        llvm_i32_ty], [IntrReadArgMem]>;
386
387 // Interleaving vector stores from N-element structures.
388 // Source operands are: the address, the N vectors, and the alignment.
389 def int_arm_neon_vst1 : Intrinsic<[],
390                                   [llvm_ptr_ty, llvm_anyvector_ty,
391                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
392 def int_arm_neon_vst2 : Intrinsic<[],
393                                   [llvm_ptr_ty, llvm_anyvector_ty,
394                                    LLVMMatchType<0>, llvm_i32_ty],
395                                   [IntrReadWriteArgMem]>;
396 def int_arm_neon_vst3 : Intrinsic<[],
397                                   [llvm_ptr_ty, llvm_anyvector_ty,
398                                    LLVMMatchType<0>, LLVMMatchType<0>,
399                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
400 def int_arm_neon_vst4 : Intrinsic<[],
401                                   [llvm_ptr_ty, llvm_anyvector_ty,
402                                    LLVMMatchType<0>, LLVMMatchType<0>,
403                                    LLVMMatchType<0>, llvm_i32_ty],
404                                   [IntrReadWriteArgMem]>;
405
406 // Vector store N-element structure from one lane.
407 // Source operands are: the address, the N vectors, the lane number, and
408 // the alignment.
409 def int_arm_neon_vst2lane : Intrinsic<[],
410                                       [llvm_ptr_ty, llvm_anyvector_ty,
411                                        LLVMMatchType<0>, llvm_i32_ty,
412                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
413 def int_arm_neon_vst3lane : Intrinsic<[],
414                                       [llvm_ptr_ty, llvm_anyvector_ty,
415                                        LLVMMatchType<0>, LLVMMatchType<0>,
416                                        llvm_i32_ty, llvm_i32_ty],
417                                       [IntrReadWriteArgMem]>;
418 def int_arm_neon_vst4lane : Intrinsic<[],
419                                       [llvm_ptr_ty, llvm_anyvector_ty,
420                                        LLVMMatchType<0>, LLVMMatchType<0>,
421                                        LLVMMatchType<0>, llvm_i32_ty,
422                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
423
424 // Vector bitwise select.
425 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
426                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
427                         [IntrNoMem]>;
428
429 } // end TargetPrefix