include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41
  42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  44
  45 def int_arm_clrex : Intrinsic<[]>;
  46
  47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  48     llvm_ptr_ty]>;
  49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  50
  51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Data barrier instructions
  57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>;
  58 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>;
  59 def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, Intrinsic<[], [llvm_i32_ty]>;
  60
  61 //===----------------------------------------------------------------------===//
  62 // VFP
  63
  64 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  65                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  66 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  67                        Intrinsic<[], [llvm_i32_ty], []>;
  68 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  69                                   [IntrNoMem]>;
  70 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  71                                   [IntrNoMem]>;
  72
  73 //===----------------------------------------------------------------------===//
  74 // Coprocessor
  75
  76 // Move to coprocessor
  77 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  78    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  79                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  80 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  81    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  82                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  83
  84 // Move from coprocessor
  85 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  86    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  87                              llvm_i32_ty, llvm_i32_ty], []>;
  88 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  89    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  90                              llvm_i32_ty, llvm_i32_ty], []>;
  91
  92 // Coprocessor data processing
  93 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  94    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  95                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  96 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  97    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  98                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  99
 100 // Move from two registers to coprocessor
 101 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 102    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 103                   llvm_i32_ty, llvm_i32_ty], []>;
 104 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 105    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 106                   llvm_i32_ty, llvm_i32_ty], []>;
 107
 108 //===----------------------------------------------------------------------===//
 109 // CRC32
 110
 111 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 112     [IntrNoMem]>;
 113 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 114     [IntrNoMem]>;
 115 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 116     [IntrNoMem]>;
 117 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 118     [IntrNoMem]>;
 119 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 120     [IntrNoMem]>;
 121 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 122     [IntrNoMem]>;
 123
 124 //===----------------------------------------------------------------------===//
 125 // HINT
 126
 127 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 128
 129 //===----------------------------------------------------------------------===//
 130 // RBIT
 131
 132 def int_arm_rbit : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 133
 134 //===----------------------------------------------------------------------===//
 135 // UND (reserved undefined sequence)
 136
 137 def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
 138
 139 //===----------------------------------------------------------------------===//
 140 // Advanced SIMD (NEON)
 141
 142 // The following classes do not correspond directly to GCC builtins.
 143 class Neon_1Arg_Intrinsic
 144   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 145 class Neon_1Arg_Narrow_Intrinsic
 146   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 147 class Neon_2Arg_Intrinsic
 148   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 149               [IntrNoMem]>;
 150 class Neon_2Arg_Narrow_Intrinsic
 151   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 152               [IntrNoMem]>;
 153 class Neon_2Arg_Long_Intrinsic
 154   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 155               [IntrNoMem]>;
 156 class Neon_3Arg_Intrinsic
 157   : Intrinsic<[llvm_anyvector_ty],
 158               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 159               [IntrNoMem]>;
 160 class Neon_3Arg_Long_Intrinsic
 161   : Intrinsic<[llvm_anyvector_ty],
 162               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 163               [IntrNoMem]>;
 164 class Neon_CvtFxToFP_Intrinsic
 165   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 166 class Neon_CvtFPToFx_Intrinsic
 167   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 168 class Neon_CvtFPtoInt_1Arg_Intrinsic
 169   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 170
 171 class Neon_Compare_Intrinsic
 172   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 173               [IntrNoMem]>;
 174
 175 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 176 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 177 // Overall, the classes range from 2 to 6 v8i8 arguments.
 178 class Neon_Tbl2Arg_Intrinsic
 179   : Intrinsic<[llvm_v8i8_ty],
 180               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 181 class Neon_Tbl3Arg_Intrinsic
 182   : Intrinsic<[llvm_v8i8_ty],
 183               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 184 class Neon_Tbl4Arg_Intrinsic
 185   : Intrinsic<[llvm_v8i8_ty],
 186               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 187               [IntrNoMem]>;
 188 class Neon_Tbl5Arg_Intrinsic
 189   : Intrinsic<[llvm_v8i8_ty],
 190               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 191                llvm_v8i8_ty], [IntrNoMem]>;
 192 class Neon_Tbl6Arg_Intrinsic
 193   : Intrinsic<[llvm_v8i8_ty],
 194               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 195                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 196
 197 // Arithmetic ops
 198
 199 let Properties = [IntrNoMem, Commutative] in {
 200
 201   // Vector Add.
 202   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 203   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 204   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 205   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 206   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 207   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 208   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 209
 210   // Vector Multiply.
 211   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 212   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 213   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 214   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 215   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 216   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 217   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 218
 219   // Vector Maximum.
 220   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 221   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 222   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 223
 224   // Vector Minimum.
 225   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 226   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 227   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 228
 229   // Vector Reciprocal Step.
 230   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 231
 232   // Vector Reciprocal Square Root Step.
 233   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 234 }
 235
 236 // Vector Subtract.
 237 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 238 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 239 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 240 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 241 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 242
 243 // Vector Absolute Compare.
 244 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 245 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 246
 247 // Vector Absolute Differences.
 248 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 249 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 250
 251 // Vector Pairwise Add.
 252 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 253
 254 // Vector Pairwise Add Long.
 255 // Note: This is different than the other "long" NEON intrinsics because
 256 // the result vector has half as many elements as the source vector.
 257 // The source and destination vector types must be specified separately.
 258 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 259                                      [IntrNoMem]>;
 260 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 261                                      [IntrNoMem]>;
 262
 263 // Vector Pairwise Add and Accumulate Long.
 264 // Note: This is similar to vpaddl but the destination vector also appears
 265 // as the first argument.
 266 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 267                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 268                                      [IntrNoMem]>;
 269 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 270                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 271                                      [IntrNoMem]>;
 272
 273 // Vector Pairwise Maximum and Minimum.
 274 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 275 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 276 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 277 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 278
 279 // Vector Shifts:
 280 //
 281 // The various saturating and rounding vector shift operations need to be
 282 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 283 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 284 // be used for both left and right shifts, or even combinations of the two,
 285 // depending on the signs of the shift amounts.  It also has well-defined
 286 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 287 // by constants can be represented with LLVM's shift operators.
 288 //
 289 // The shift counts for these intrinsics are always vectors, even for constant
 290 // shifts, where the constant is replicated.  For consistency with VSHL (and
 291 // other variable shift instructions), left shifts have positive shift counts
 292 // and right shifts have negative shift counts.  This convention is also used
 293 // for constant right shift intrinsics, and to help preserve sanity, the
 294 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 295 // applicable, signed and unsigned versions of the intrinsics are
 296 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 297 // such as VQSHLU, take signed operands but produce unsigned results; these
 298 // use a "su" suffix.
 299
 300 // Vector Shift.
 301 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 302 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 303
 304 // Vector Rounding Shift.
 305 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 306 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 307 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 308
 309 // Vector Saturating Shift.
 310 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 311 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 312 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 313 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 314 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 315 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 316
 317 // Vector Saturating Rounding Shift.
 318 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 319 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 320 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 321 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 322 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 323
 324 // Vector Shift and Insert.
 325 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 326
 327 // Vector Absolute Value and Saturating Absolute Value.
 328 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 329 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 330
 331 // Vector Saturating Negate.
 332 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 333
 334 // Vector Count Leading Sign/Zero Bits.
 335 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 336 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 337
 338 // Vector Count One Bits.
 339 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 340
 341 // Vector Reciprocal Estimate.
 342 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 343
 344 // Vector Reciprocal Square Root Estimate.
 345 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 346
 347 // Vector Conversions Between Floating-point and Integer
 348 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 349 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 350 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 351 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 352 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 353 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 354 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 355 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 356
 357 // Vector Conversions Between Floating-point and Fixed-point.
 358 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 359 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 360 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 361 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 362
 363 // Vector Conversions Between Half-Precision and Single-Precision.
 364 def int_arm_neon_vcvtfp2hf
 365     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 366 def int_arm_neon_vcvthf2fp
 367     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 368
 369 // Narrowing Saturating Vector Moves.
 370 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 371 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 372 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 373
 374 // Vector Table Lookup.
 375 // The first 1-4 arguments are the table.
 376 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 377 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 378 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 379 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 380
 381 // Vector Table Extension.
 382 // Some elements of the destination vector may not be updated, so the original
 383 // value of that vector is passed as the first argument.  The next 1-4
 384 // arguments after that are the table.
 385 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 386 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 387 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 388 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 389
 390 // Vector Rounding
 391 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 392 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 393 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 394 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 395 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 396 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 397
 398 // De-interleaving vector loads from N-element structures.
 399 // Source operands are the address and alignment.
 400 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 401                                   [llvm_ptr_ty, llvm_i32_ty],
 402                                   [IntrReadArgMem]>;
 403 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 404                                   [llvm_ptr_ty, llvm_i32_ty],
 405                                   [IntrReadArgMem]>;
 406 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 407                                    LLVMMatchType<0>],
 408                                   [llvm_ptr_ty, llvm_i32_ty],
 409                                   [IntrReadArgMem]>;
 410 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 411                                    LLVMMatchType<0>, LLVMMatchType<0>],
 412                                   [llvm_ptr_ty, llvm_i32_ty],
 413                                   [IntrReadArgMem]>;
 414
 415 // Vector load N-element structure to one lane.
 416 // Source operands are: the address, the N input vectors (since only one
 417 // lane is assigned), the lane number, and the alignment.
 418 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 419                                       [llvm_ptr_ty, LLVMMatchType<0>,
 420                                        LLVMMatchType<0>, llvm_i32_ty,
 421                                        llvm_i32_ty], [IntrReadArgMem]>;
 422 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 423                                        LLVMMatchType<0>],
 424                                       [llvm_ptr_ty, LLVMMatchType<0>,
 425                                        LLVMMatchType<0>, LLVMMatchType<0>,
 426                                        llvm_i32_ty, llvm_i32_ty],
 427                                       [IntrReadArgMem]>;
 428 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 429                                        LLVMMatchType<0>, LLVMMatchType<0>],
 430                                       [llvm_ptr_ty, LLVMMatchType<0>,
 431                                        LLVMMatchType<0>, LLVMMatchType<0>,
 432                                        LLVMMatchType<0>, llvm_i32_ty,
 433                                        llvm_i32_ty], [IntrReadArgMem]>;
 434
 435 // Interleaving vector stores from N-element structures.
 436 // Source operands are: the address, the N vectors, and the alignment.
 437 def int_arm_neon_vst1 : Intrinsic<[],
 438                                   [llvm_ptr_ty, llvm_anyvector_ty,
 439                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 440 def int_arm_neon_vst2 : Intrinsic<[],
 441                                   [llvm_ptr_ty, llvm_anyvector_ty,
 442                                    LLVMMatchType<0>, llvm_i32_ty],
 443                                   [IntrReadWriteArgMem]>;
 444 def int_arm_neon_vst3 : Intrinsic<[],
 445                                   [llvm_ptr_ty, llvm_anyvector_ty,
 446                                    LLVMMatchType<0>, LLVMMatchType<0>,
 447                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 448 def int_arm_neon_vst4 : Intrinsic<[],
 449                                   [llvm_ptr_ty, llvm_anyvector_ty,
 450                                    LLVMMatchType<0>, LLVMMatchType<0>,
 451                                    LLVMMatchType<0>, llvm_i32_ty],
 452                                   [IntrReadWriteArgMem]>;
 453
 454 // Vector store N-element structure from one lane.
 455 // Source operands are: the address, the N vectors, the lane number, and
 456 // the alignment.
 457 def int_arm_neon_vst2lane : Intrinsic<[],
 458                                       [llvm_ptr_ty, llvm_anyvector_ty,
 459                                        LLVMMatchType<0>, llvm_i32_ty,
 460                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 461 def int_arm_neon_vst3lane : Intrinsic<[],
 462                                       [llvm_ptr_ty, llvm_anyvector_ty,
 463                                        LLVMMatchType<0>, LLVMMatchType<0>,
 464                                        llvm_i32_ty, llvm_i32_ty],
 465                                       [IntrReadWriteArgMem]>;
 466 def int_arm_neon_vst4lane : Intrinsic<[],
 467                                       [llvm_ptr_ty, llvm_anyvector_ty,
 468                                        LLVMMatchType<0>, LLVMMatchType<0>,
 469                                        LLVMMatchType<0>, llvm_i32_ty,
 470                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 471
 472 // Vector bitwise select.
 473 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 474                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 475                         [IntrNoMem]>;
 476
 477
 478 // Crypto instructions
 479 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 480                                      [llvm_v16i8_ty], [IntrNoMem]>;
 481 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 482                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 483                                      [IntrNoMem]>;
 484
 485 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 486                                      [IntrNoMem]>;
 487 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 488                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 489                                      [IntrNoMem]>;
 490 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 491                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 492                                    [IntrNoMem]>;
 493 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 494                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 495                                    [IntrNoMem]>;
 496
 497 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 498 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 499 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 500 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 501 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 502 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 503 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 504 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 505 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 506 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 507 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 508 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 509 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 510 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 511
 512 } // end TargetPrefix