include/llvm/IR/IntrinsicsARM.td

   1 //===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the ARM-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14
  15 //===----------------------------------------------------------------------===//
  16 // TLS
  17
  18 let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
  19
  20 def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
  21             Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
  22
  23 //===----------------------------------------------------------------------===//
  24 // Saturating Arithmentic
  25
  26 def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
  27     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
  28     [IntrNoMem, Commutative]>;
  29 def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
  30     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  31 def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
  32     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  33 def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
  34     Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
  35
  36 //===----------------------------------------------------------------------===//
  37 // Load, Store and Clear exclusive
  38
  39 def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  40 def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  41
  42 def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
  43 def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
  44
  45 def int_arm_clrex : Intrinsic<[]>;
  46
  47 def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
  48     llvm_ptr_ty]>;
  49 def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  50
  51 def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
  52                                [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
  53 def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
  54
  55 //===----------------------------------------------------------------------===//
  56 // Data barrier instructions
  57 def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>;
  58 def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // VFP
  62
  63 def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
  64                        Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
  65 def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
  66                        Intrinsic<[], [llvm_i32_ty], []>;
  67 def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  68                                   [IntrNoMem]>;
  69 def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
  70                                   [IntrNoMem]>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Coprocessor
  74
  75 // Move to coprocessor
  76 def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
  77    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  78                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  79 def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
  80    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  81                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  82
  83 // Move from coprocessor
  84 def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
  85    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  86                              llvm_i32_ty, llvm_i32_ty], []>;
  87 def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
  88    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  89                              llvm_i32_ty, llvm_i32_ty], []>;
  90
  91 // Coprocessor data processing
  92 def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
  93    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  94                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  95 def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
  96    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
  97                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
  98
  99 // Move from two registers to coprocessor
 100 def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
 101    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 102                   llvm_i32_ty, llvm_i32_ty], []>;
 103 def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
 104    Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
 105                   llvm_i32_ty, llvm_i32_ty], []>;
 106
 107 //===----------------------------------------------------------------------===//
 108 // CRC32
 109
 110 def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 111     [IntrNoMem]>;
 112 def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 113     [IntrNoMem]>;
 114 def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 115     [IntrNoMem]>;
 116 def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 117     [IntrNoMem]>;
 118 def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 119     [IntrNoMem]>;
 120 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 121     [IntrNoMem]>;
 122
 123 //===----------------------------------------------------------------------===//
 124 // HINT
 125 def int_arm_sevl : Intrinsic<[], []>;
 126 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 127
 128 //===----------------------------------------------------------------------===//
 129 // Advanced SIMD (NEON)
 130
 131 // The following classes do not correspond directly to GCC builtins.
 132 class Neon_1Arg_Intrinsic
 133   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 134 class Neon_1Arg_Narrow_Intrinsic
 135   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
 136 class Neon_2Arg_Intrinsic
 137   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
 138               [IntrNoMem]>;
 139 class Neon_2Arg_Narrow_Intrinsic
 140   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
 141               [IntrNoMem]>;
 142 class Neon_2Arg_Long_Intrinsic
 143   : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 144               [IntrNoMem]>;
 145 class Neon_3Arg_Intrinsic
 146   : Intrinsic<[llvm_anyvector_ty],
 147               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 148               [IntrNoMem]>;
 149 class Neon_3Arg_Long_Intrinsic
 150   : Intrinsic<[llvm_anyvector_ty],
 151               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
 152               [IntrNoMem]>;
 153 class Neon_CvtFxToFP_Intrinsic
 154   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 155 class Neon_CvtFPToFx_Intrinsic
 156   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 157 class Neon_CvtFPtoInt_1Arg_Intrinsic
 158   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 159
 160 class Neon_Compare_Intrinsic
 161   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
 162               [IntrNoMem]>;
 163
 164 // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
 165 // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
 166 // Overall, the classes range from 2 to 6 v8i8 arguments.
 167 class Neon_Tbl2Arg_Intrinsic
 168   : Intrinsic<[llvm_v8i8_ty],
 169               [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 170 class Neon_Tbl3Arg_Intrinsic
 171   : Intrinsic<[llvm_v8i8_ty],
 172               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 173 class Neon_Tbl4Arg_Intrinsic
 174   : Intrinsic<[llvm_v8i8_ty],
 175               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
 176               [IntrNoMem]>;
 177 class Neon_Tbl5Arg_Intrinsic
 178   : Intrinsic<[llvm_v8i8_ty],
 179               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 180                llvm_v8i8_ty], [IntrNoMem]>;
 181 class Neon_Tbl6Arg_Intrinsic
 182   : Intrinsic<[llvm_v8i8_ty],
 183               [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
 184                llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
 185
 186 // Arithmetic ops
 187
 188 let Properties = [IntrNoMem, Commutative] in {
 189
 190   // Vector Add.
 191   def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
 192   def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
 193   def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
 194   def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
 195   def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
 196   def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
 197   def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
 198
 199   // Vector Multiply.
 200   def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
 201   def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
 202   def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
 203   def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
 204   def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
 205   def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
 206   def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
 207
 208   // Vector Maximum.
 209   def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
 210   def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
 211   def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
 212
 213   // Vector Minimum.
 214   def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
 215   def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
 216   def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
 217
 218   // Vector Reciprocal Step.
 219   def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
 220
 221   // Vector Reciprocal Square Root Step.
 222   def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
 223 }
 224
 225 // Vector Subtract.
 226 def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
 227 def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
 228 def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
 229 def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
 230 def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
 231
 232 // Vector Absolute Compare.
 233 def int_arm_neon_vacge : Neon_Compare_Intrinsic;
 234 def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
 235
 236 // Vector Absolute Differences.
 237 def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
 238 def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
 239
 240 // Vector Pairwise Add.
 241 def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
 242
 243 // Vector Pairwise Add Long.
 244 // Note: This is different than the other "long" NEON intrinsics because
 245 // the result vector has half as many elements as the source vector.
 246 // The source and destination vector types must be specified separately.
 247 def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 248                                      [IntrNoMem]>;
 249 def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
 250                                      [IntrNoMem]>;
 251
 252 // Vector Pairwise Add and Accumulate Long.
 253 // Note: This is similar to vpaddl but the destination vector also appears
 254 // as the first argument.
 255 def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
 256                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 257                                      [IntrNoMem]>;
 258 def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
 259                                      [LLVMMatchType<0>, llvm_anyvector_ty],
 260                                      [IntrNoMem]>;
 261
 262 // Vector Pairwise Maximum and Minimum.
 263 def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
 264 def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
 265 def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
 266 def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
 267
 268 // Vector Shifts:
 269 //
 270 // The various saturating and rounding vector shift operations need to be
 271 // represented by intrinsics in LLVM, and even the basic VSHL variable shift
 272 // operation cannot be safely translated to LLVM's shift operators.  VSHL can
 273 // be used for both left and right shifts, or even combinations of the two,
 274 // depending on the signs of the shift amounts.  It also has well-defined
 275 // behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
 276 // by constants can be represented with LLVM's shift operators.
 277 //
 278 // The shift counts for these intrinsics are always vectors, even for constant
 279 // shifts, where the constant is replicated.  For consistency with VSHL (and
 280 // other variable shift instructions), left shifts have positive shift counts
 281 // and right shifts have negative shift counts.  This convention is also used
 282 // for constant right shift intrinsics, and to help preserve sanity, the
 283 // intrinsic names use "shift" instead of either "shl" or "shr".  Where
 284 // applicable, signed and unsigned versions of the intrinsics are
 285 // distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
 286 // such as VQSHLU, take signed operands but produce unsigned results; these
 287 // use a "su" suffix.
 288
 289 // Vector Shift.
 290 def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
 291 def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
 292
 293 // Vector Rounding Shift.
 294 def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
 295 def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
 296 def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
 297
 298 // Vector Saturating Shift.
 299 def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
 300 def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
 301 def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
 302 def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
 303 def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
 304 def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 305
 306 // Vector Saturating Rounding Shift.
 307 def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
 308 def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
 309 def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
 310 def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
 311 def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
 312
 313 // Vector Shift and Insert.
 314 def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
 315
 316 // Vector Absolute Value and Saturating Absolute Value.
 317 def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
 318 def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
 319
 320 // Vector Saturating Negate.
 321 def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
 322
 323 // Vector Count Leading Sign/Zero Bits.
 324 def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
 325 def int_arm_neon_vclz : Neon_1Arg_Intrinsic;
 326
 327 // Vector Count One Bits.
 328 def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
 329
 330 // Vector Reciprocal Estimate.
 331 def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
 332
 333 // Vector Reciprocal Square Root Estimate.
 334 def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
 335
 336 // Vector Conversions Between Floating-point and Integer
 337 def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
 338 def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
 339 def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 340 def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
 341 def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 342 def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
 343 def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
 344 def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
 345
 346 // Vector Conversions Between Floating-point and Fixed-point.
 347 def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
 348 def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
 349 def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
 350 def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
 351
 352 // Vector Conversions Between Half-Precision and Single-Precision.
 353 def int_arm_neon_vcvtfp2hf
 354     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 355 def int_arm_neon_vcvthf2fp
 356     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 357
 358 // Narrowing Saturating Vector Moves.
 359 def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
 360 def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
 361 def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
 362
 363 // Vector Table Lookup.
 364 // The first 1-4 arguments are the table.
 365 def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
 366 def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
 367 def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
 368 def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
 369
 370 // Vector Table Extension.
 371 // Some elements of the destination vector may not be updated, so the original
 372 // value of that vector is passed as the first argument.  The next 1-4
 373 // arguments after that are the table.
 374 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 375 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 376 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 377 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 378
 379 // Vector Rounding
 380 def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
 381 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 382 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 383 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 384 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 385 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 386
 387 // De-interleaving vector loads from N-element structures.
 388 // Source operands are the address and alignment.
 389 def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
 390                                   [llvm_ptr_ty, llvm_i32_ty],
 391                                   [IntrReadArgMem]>;
 392 def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 393                                   [llvm_ptr_ty, llvm_i32_ty],
 394                                   [IntrReadArgMem]>;
 395 def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 396                                    LLVMMatchType<0>],
 397                                   [llvm_ptr_ty, llvm_i32_ty],
 398                                   [IntrReadArgMem]>;
 399 def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 400                                    LLVMMatchType<0>, LLVMMatchType<0>],
 401                                   [llvm_ptr_ty, llvm_i32_ty],
 402                                   [IntrReadArgMem]>;
 403
 404 // Vector load N-element structure to one lane.
 405 // Source operands are: the address, the N input vectors (since only one
 406 // lane is assigned), the lane number, and the alignment.
 407 def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 408                                       [llvm_ptr_ty, LLVMMatchType<0>,
 409                                        LLVMMatchType<0>, llvm_i32_ty,
 410                                        llvm_i32_ty], [IntrReadArgMem]>;
 411 def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 412                                        LLVMMatchType<0>],
 413                                       [llvm_ptr_ty, LLVMMatchType<0>,
 414                                        LLVMMatchType<0>, LLVMMatchType<0>,
 415                                        llvm_i32_ty, llvm_i32_ty],
 416                                       [IntrReadArgMem]>;
 417 def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 418                                        LLVMMatchType<0>, LLVMMatchType<0>],
 419                                       [llvm_ptr_ty, LLVMMatchType<0>,
 420                                        LLVMMatchType<0>, LLVMMatchType<0>,
 421                                        LLVMMatchType<0>, llvm_i32_ty,
 422                                        llvm_i32_ty], [IntrReadArgMem]>;
 423
 424 // Interleaving vector stores from N-element structures.
 425 // Source operands are: the address, the N vectors, and the alignment.
 426 def int_arm_neon_vst1 : Intrinsic<[],
 427                                   [llvm_ptr_ty, llvm_anyvector_ty,
 428                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 429 def int_arm_neon_vst2 : Intrinsic<[],
 430                                   [llvm_ptr_ty, llvm_anyvector_ty,
 431                                    LLVMMatchType<0>, llvm_i32_ty],
 432                                   [IntrReadWriteArgMem]>;
 433 def int_arm_neon_vst3 : Intrinsic<[],
 434                                   [llvm_ptr_ty, llvm_anyvector_ty,
 435                                    LLVMMatchType<0>, LLVMMatchType<0>,
 436                                    llvm_i32_ty], [IntrReadWriteArgMem]>;
 437 def int_arm_neon_vst4 : Intrinsic<[],
 438                                   [llvm_ptr_ty, llvm_anyvector_ty,
 439                                    LLVMMatchType<0>, LLVMMatchType<0>,
 440                                    LLVMMatchType<0>, llvm_i32_ty],
 441                                   [IntrReadWriteArgMem]>;
 442
 443 // Vector store N-element structure from one lane.
 444 // Source operands are: the address, the N vectors, the lane number, and
 445 // the alignment.
 446 def int_arm_neon_vst2lane : Intrinsic<[],
 447                                       [llvm_ptr_ty, llvm_anyvector_ty,
 448                                        LLVMMatchType<0>, llvm_i32_ty,
 449                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 450 def int_arm_neon_vst3lane : Intrinsic<[],
 451                                       [llvm_ptr_ty, llvm_anyvector_ty,
 452                                        LLVMMatchType<0>, LLVMMatchType<0>,
 453                                        llvm_i32_ty, llvm_i32_ty],
 454                                       [IntrReadWriteArgMem]>;
 455 def int_arm_neon_vst4lane : Intrinsic<[],
 456                                       [llvm_ptr_ty, llvm_anyvector_ty,
 457                                        LLVMMatchType<0>, LLVMMatchType<0>,
 458                                        LLVMMatchType<0>, llvm_i32_ty,
 459                                        llvm_i32_ty], [IntrReadWriteArgMem]>;
 460
 461 // Vector bitwise select.
 462 def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
 463                         [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 464                         [IntrNoMem]>;
 465
 466
 467 // Crypto instructions
 468 class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 469                                      [llvm_v16i8_ty], [IntrNoMem]>;
 470 class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
 471                                      [llvm_v16i8_ty, llvm_v16i8_ty],
 472                                      [IntrNoMem]>;
 473
 474 class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
 475                                      [IntrNoMem]>;
 476 class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 477                                      [llvm_v4i32_ty, llvm_v4i32_ty],
 478                                      [IntrNoMem]>;
 479 class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 480                                    [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 481                                    [IntrNoMem]>;
 482 class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
 483                                    [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
 484                                    [IntrNoMem]>;
 485
 486 def int_arm_neon_aesd : AES_2Arg_Intrinsic;
 487 def int_arm_neon_aese : AES_2Arg_Intrinsic;
 488 def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
 489 def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
 490 def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
 491 def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
 492 def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
 493 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 494 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 495 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 496 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 497 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 498 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 499 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 500
 501 } // end TargetPrefix