include/llvm/IR/IntrinsicsAArch64.td

   1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines all of the AARCH64-specific intrinsics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 let TargetPrefix = "aarch64" in {
  15
  16 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
  18 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  19 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
  20
  21 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  22 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
  23 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
  24                                [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  25 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
  26                                 [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>;
  27
  28 def int_aarch64_clrex : Intrinsic<[]>;
  29
  30 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  31                                 LLVMMatchType<0>], [IntrNoMem]>;
  32 def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
  33                                 LLVMMatchType<0>], [IntrNoMem]>;
  34
  35 //===----------------------------------------------------------------------===//
  36 // RBIT
  37
  38 def int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>],
  39                                  [IntrNoMem]>;
  40
  41 }
  42
  43 //===----------------------------------------------------------------------===//
  44 // Advanced SIMD (NEON)
  45
  46 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
  47   class AdvSIMD_2Scalar_Float_Intrinsic
  48     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  49                 [IntrNoMem]>;
  50
  51   class AdvSIMD_FPToIntRounding_Intrinsic
  52     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
  53
  54   class AdvSIMD_1IntArg_Intrinsic
  55     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  56   class AdvSIMD_1FloatArg_Intrinsic
  57     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  58   class AdvSIMD_1VectorArg_Intrinsic
  59     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
  60   class AdvSIMD_1VectorArg_Expand_Intrinsic
  61     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  62   class AdvSIMD_1VectorArg_Long_Intrinsic
  63     : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>;
  64   class AdvSIMD_1IntArg_Narrow_Intrinsic
  65     : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>;
  66   class AdvSIMD_1VectorArg_Narrow_Intrinsic
  67     : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
  68   class AdvSIMD_1VectorArg_Int_Across_Intrinsic
  69     : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  70   class AdvSIMD_1VectorArg_Float_Across_Intrinsic
  71     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>;
  72
  73   class AdvSIMD_2IntArg_Intrinsic
  74     : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  75                 [IntrNoMem]>;
  76   class AdvSIMD_2FloatArg_Intrinsic
  77     : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  78                 [IntrNoMem]>;
  79   class AdvSIMD_2VectorArg_Intrinsic
  80     : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
  81                 [IntrNoMem]>;
  82   class AdvSIMD_2VectorArg_Compare_Intrinsic
  83     : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
  84                 [IntrNoMem]>;
  85   class AdvSIMD_2Arg_FloatCompare_Intrinsic
  86     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>],
  87                 [IntrNoMem]>;
  88   class AdvSIMD_2VectorArg_Long_Intrinsic
  89     : Intrinsic<[llvm_anyvector_ty],
  90                 [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
  91                 [IntrNoMem]>;
  92   class AdvSIMD_2VectorArg_Wide_Intrinsic
  93     : Intrinsic<[llvm_anyvector_ty],
  94                 [LLVMMatchType<0>, LLVMTruncatedType<0>],
  95                 [IntrNoMem]>;
  96   class AdvSIMD_2VectorArg_Narrow_Intrinsic
  97     : Intrinsic<[llvm_anyvector_ty],
  98                 [LLVMExtendedType<0>, LLVMExtendedType<0>],
  99                 [IntrNoMem]>;
 100   class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic
 101     : Intrinsic<[llvm_anyint_ty],
 102                 [LLVMExtendedType<0>, llvm_i32_ty],
 103                 [IntrNoMem]>;
 104   class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic
 105     : Intrinsic<[llvm_anyvector_ty],
 106                 [llvm_anyvector_ty],
 107                 [IntrNoMem]>;
 108   class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic
 109     : Intrinsic<[llvm_anyvector_ty],
 110                 [LLVMTruncatedType<0>],
 111                 [IntrNoMem]>;
 112   class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic
 113     : Intrinsic<[llvm_anyvector_ty],
 114                 [LLVMTruncatedType<0>, llvm_i32_ty],
 115                 [IntrNoMem]>;
 116   class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic
 117     : Intrinsic<[llvm_anyvector_ty],
 118                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty],
 119                 [IntrNoMem]>;
 120
 121   class AdvSIMD_3VectorArg_Intrinsic
 122       : Intrinsic<[llvm_anyvector_ty],
 123                [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
 124                [IntrNoMem]>;
 125   class AdvSIMD_3VectorArg_Scalar_Intrinsic
 126       : Intrinsic<[llvm_anyvector_ty],
 127                [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
 128                [IntrNoMem]>;
 129   class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic
 130       : Intrinsic<[llvm_anyvector_ty],
 131                [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty,
 132                 LLVMMatchType<1>], [IntrNoMem]>;
 133   class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic
 134     : Intrinsic<[llvm_anyvector_ty],
 135                 [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty],
 136                 [IntrNoMem]>;
 137   class AdvSIMD_CvtFxToFP_Intrinsic
 138     : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty],
 139                 [IntrNoMem]>;
 140   class AdvSIMD_CvtFPToFx_Intrinsic
 141     : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty],
 142                 [IntrNoMem]>;
 143 }
 144
 145 // Arithmetic ops
 146
 147 let Properties = [IntrNoMem] in {
 148   // Vector Add Across Lanes
 149   def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 150   def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 151   def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 152
 153   // Vector Long Add Across Lanes
 154   def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 155   def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 156
 157   // Vector Halving Add
 158   def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic;
 159   def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic;
 160
 161   // Vector Rounding Halving Add
 162   def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic;
 163   def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic;
 164
 165   // Vector Saturating Add
 166   def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic;
 167   def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic;
 168   def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic;
 169   def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic;
 170
 171   // Vector Add High-Half
 172   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 173   // header is no longer supported.
 174   def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 175
 176   // Vector Rounding Add High-Half
 177   def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 178
 179   // Vector Saturating Doubling Multiply High
 180   def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic;
 181
 182   // Vector Saturating Rounding Doubling Multiply High
 183   def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic;
 184
 185   // Vector Polynominal Multiply
 186   def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic;
 187
 188   // Vector Long Multiply
 189   def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic;
 190   def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic;
 191   def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 192
 193   // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
 194   // it with a v16i8.
 195   def int_aarch64_neon_pmull64 :
 196         Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
 197
 198   // Vector Extending Multiply
 199   def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic {
 200     let Properties = [IntrNoMem, Commutative];
 201   }
 202
 203   // Vector Saturating Doubling Long Multiply
 204   def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic;
 205   def int_aarch64_neon_sqdmulls_scalar
 206     : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
 207
 208   // Vector Halving Subtract
 209   def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic;
 210   def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic;
 211
 212   // Vector Saturating Subtract
 213   def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic;
 214   def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic;
 215
 216   // Vector Subtract High-Half
 217   // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that
 218   // header is no longer supported.
 219   def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 220
 221   // Vector Rounding Subtract High-Half
 222   def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic;
 223
 224   // Vector Compare Absolute Greater-than-or-equal
 225   def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 226
 227   // Vector Compare Absolute Greater-than
 228   def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic;
 229
 230   // Vector Absolute Difference
 231   def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic;
 232   def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic;
 233   def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic;
 234
 235   // Scalar Absolute Difference
 236   def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic;
 237
 238   // Vector Max
 239   def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic;
 240   def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic;
 241   def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic;
 242   def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic;
 243
 244   // Vector Max Across Lanes
 245   def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 246   def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 247   def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 248   def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 249
 250   // Vector Min
 251   def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic;
 252   def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic;
 253   def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic;
 254   def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic;
 255
 256   // Vector Min/Max Number
 257   def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic;
 258   def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic;
 259
 260   // Vector Min Across Lanes
 261   def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 262   def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic;
 263   def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 264   def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic;
 265
 266   // Pairwise Add
 267   def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic;
 268
 269   // Long Pairwise Add
 270   // FIXME: In theory, we shouldn't need intrinsics for saddlp or
 271   // uaddlp, but tblgen's type inference currently can't handle the
 272   // pattern fragments this ends up generating.
 273   def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 274   def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic;
 275
 276   // Folding Maximum
 277   def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic;
 278   def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic;
 279   def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic;
 280
 281   // Folding Minimum
 282   def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic;
 283   def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic;
 284   def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic;
 285
 286   // Reciprocal Estimate/Step
 287   def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic;
 288   def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic;
 289
 290   // Reciprocal Exponent
 291   def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic;
 292
 293   // Vector Saturating Shift Left
 294   def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic;
 295   def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic;
 296
 297   // Vector Rounding Shift Left
 298   def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic;
 299   def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic;
 300
 301   // Vector Saturating Rounding Shift Left
 302   def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic;
 303   def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic;
 304
 305   // Vector Signed->Unsigned Shift Left by Constant
 306   def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic;
 307
 308   // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
 309   def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 310
 311   // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
 312   def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 313
 314   // Vector Narrowing Shift Right by Constant
 315   def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 316   def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 317
 318   // Vector Rounding Narrowing Shift Right by Constant
 319   def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 320
 321   // Vector Rounding Narrowing Saturating Shift Right by Constant
 322   def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 323   def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic;
 324
 325   // Vector Shift Left
 326   def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic;
 327   def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic;
 328
 329   // Vector Widening Shift Left by Constant
 330   def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic;
 331   def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 332   def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic;
 333
 334   // Vector Shift Right by Constant and Insert
 335   def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 336
 337   // Vector Shift Left by Constant and Insert
 338   def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic;
 339
 340   // Vector Saturating Narrow
 341   def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic;
 342   def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic;
 343   def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 344   def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 345
 346   // Vector Saturating Extract and Unsigned Narrow
 347   def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic;
 348   def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic;
 349
 350   // Vector Absolute Value
 351   def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic;
 352
 353   // Vector Saturating Absolute Value
 354   def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic;
 355
 356   // Vector Saturating Negation
 357   def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic;
 358
 359   // Vector Count Leading Sign Bits
 360   def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic;
 361
 362   // Vector Reciprocal Estimate
 363   def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic;
 364   def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic;
 365
 366   // Vector Square Root Estimate
 367   def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic;
 368   def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic;
 369
 370   // Vector Bitwise Reverse
 371   def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic;
 372
 373   // Vector Conversions Between Half-Precision and Single-Precision.
 374   def int_aarch64_neon_vcvtfp2hf
 375     : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
 376   def int_aarch64_neon_vcvthf2fp
 377     : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
 378
 379   // Vector Conversions Between Floating-point and Fixed-point.
 380   def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic;
 381   def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic;
 382   def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 383   def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic;
 384
 385   // Vector FP->Int Conversions
 386   def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic;
 387   def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic;
 388   def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic;
 389   def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic;
 390   def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic;
 391   def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic;
 392   def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic;
 393   def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic;
 394   def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic;
 395   def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic;
 396
 397   // Vector FP Rounding: only ties to even is unrepresented by a normal
 398   // intrinsic.
 399   def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic;
 400
 401   // Scalar FP->Int conversions
 402
 403   // Vector FP Inexact Narrowing
 404   def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic;
 405
 406   // Scalar FP Inexact Narrowing
 407   def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty],
 408                                         [IntrNoMem]>;
 409 }
 410
 411 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 412   class AdvSIMD_2Vector2Index_Intrinsic
 413     : Intrinsic<[llvm_anyvector_ty],
 414                 [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty],
 415                 [IntrNoMem]>;
 416 }
 417
 418 // Vector element to element moves
 419 def int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic;
 420
 421 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 422   class AdvSIMD_1Vec_Load_Intrinsic
 423       : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>],
 424                   [IntrReadArgMem]>;
 425   class AdvSIMD_1Vec_Store_Lane_Intrinsic
 426     : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty],
 427                 [IntrReadWriteArgMem, NoCapture<2>]>;
 428
 429   class AdvSIMD_2Vec_Load_Intrinsic
 430     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 431                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 432                 [IntrReadArgMem]>;
 433   class AdvSIMD_2Vec_Load_Lane_Intrinsic
 434     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
 435                 [LLVMMatchType<0>, LLVMMatchType<0>,
 436                  llvm_i64_ty, llvm_anyptr_ty],
 437                 [IntrReadArgMem]>;
 438   class AdvSIMD_2Vec_Store_Intrinsic
 439     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 440                      LLVMAnyPointerType<LLVMMatchType<0>>],
 441                 [IntrReadWriteArgMem, NoCapture<2>]>;
 442   class AdvSIMD_2Vec_Store_Lane_Intrinsic
 443     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 444                  llvm_i64_ty, llvm_anyptr_ty],
 445                 [IntrReadWriteArgMem, NoCapture<3>]>;
 446
 447   class AdvSIMD_3Vec_Load_Intrinsic
 448     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 449                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 450                 [IntrReadArgMem]>;
 451   class AdvSIMD_3Vec_Load_Lane_Intrinsic
 452     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
 453                 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
 454                  llvm_i64_ty, llvm_anyptr_ty],
 455                 [IntrReadArgMem]>;
 456   class AdvSIMD_3Vec_Store_Intrinsic
 457     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 458                      LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>],
 459                 [IntrReadWriteArgMem, NoCapture<3>]>;
 460   class AdvSIMD_3Vec_Store_Lane_Intrinsic
 461     : Intrinsic<[], [llvm_anyvector_ty,
 462                  LLVMMatchType<0>, LLVMMatchType<0>,
 463                  llvm_i64_ty, llvm_anyptr_ty],
 464                 [IntrReadWriteArgMem, NoCapture<4>]>;
 465
 466   class AdvSIMD_4Vec_Load_Intrinsic
 467     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 468                  LLVMMatchType<0>, LLVMMatchType<0>],
 469                 [LLVMAnyPointerType<LLVMMatchType<0>>],
 470                 [IntrReadArgMem]>;
 471   class AdvSIMD_4Vec_Load_Lane_Intrinsic
 472     : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
 473                  LLVMMatchType<0>, LLVMMatchType<0>],
 474                 [LLVMMatchType<0>, LLVMMatchType<0>,
 475                  LLVMMatchType<0>, LLVMMatchType<0>,
 476                  llvm_i64_ty, llvm_anyptr_ty],
 477                 [IntrReadArgMem]>;
 478   class AdvSIMD_4Vec_Store_Intrinsic
 479     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 480                  LLVMMatchType<0>, LLVMMatchType<0>,
 481                  LLVMAnyPointerType<LLVMMatchType<0>>],
 482                 [IntrReadWriteArgMem, NoCapture<4>]>;
 483   class AdvSIMD_4Vec_Store_Lane_Intrinsic
 484     : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>,
 485                  LLVMMatchType<0>, LLVMMatchType<0>,
 486                  llvm_i64_ty, llvm_anyptr_ty],
 487                 [IntrReadWriteArgMem, NoCapture<5>]>;
 488 }
 489
 490 // Memory ops
 491
 492 def int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic;
 493 def int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic;
 494 def int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic;
 495
 496 def int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic;
 497 def int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic;
 498 def int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic;
 499
 500 def int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic;
 501 def int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic;
 502 def int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic;
 503
 504 def int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic;
 505 def int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic;
 506 def int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic;
 507
 508 def int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic;
 509 def int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic;
 510 def int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic;
 511
 512 def int_aarch64_neon_st2  : AdvSIMD_2Vec_Store_Intrinsic;
 513 def int_aarch64_neon_st3  : AdvSIMD_3Vec_Store_Intrinsic;
 514 def int_aarch64_neon_st4  : AdvSIMD_4Vec_Store_Intrinsic;
 515
 516 def int_aarch64_neon_st2lane  : AdvSIMD_2Vec_Store_Lane_Intrinsic;
 517 def int_aarch64_neon_st3lane  : AdvSIMD_3Vec_Store_Lane_Intrinsic;
 518 def int_aarch64_neon_st4lane  : AdvSIMD_4Vec_Store_Lane_Intrinsic;
 519
 520 let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
 521   class AdvSIMD_Tbl1_Intrinsic
 522     : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>],
 523                 [IntrNoMem]>;
 524   class AdvSIMD_Tbl2_Intrinsic
 525     : Intrinsic<[llvm_anyvector_ty],
 526                 [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>;
 527   class AdvSIMD_Tbl3_Intrinsic
 528     : Intrinsic<[llvm_anyvector_ty],
 529                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 530                  LLVMMatchType<0>],
 531                 [IntrNoMem]>;
 532   class AdvSIMD_Tbl4_Intrinsic
 533     : Intrinsic<[llvm_anyvector_ty],
 534                 [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty,
 535                  LLVMMatchType<0>],
 536                 [IntrNoMem]>;
 537
 538   class AdvSIMD_Tbx1_Intrinsic
 539     : Intrinsic<[llvm_anyvector_ty],
 540                 [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>],
 541                 [IntrNoMem]>;
 542   class AdvSIMD_Tbx2_Intrinsic
 543     : Intrinsic<[llvm_anyvector_ty],
 544                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 545                  LLVMMatchType<0>],
 546                 [IntrNoMem]>;
 547   class AdvSIMD_Tbx3_Intrinsic
 548     : Intrinsic<[llvm_anyvector_ty],
 549                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 550                  llvm_v16i8_ty, LLVMMatchType<0>],
 551                 [IntrNoMem]>;
 552   class AdvSIMD_Tbx4_Intrinsic
 553     : Intrinsic<[llvm_anyvector_ty],
 554                 [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty,
 555                  llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>],
 556                 [IntrNoMem]>;
 557 }
 558 def int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic;
 559 def int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic;
 560 def int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic;
 561 def int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic;
 562
 563 def int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic;
 564 def int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic;
 565 def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 566 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 567
 568 let TargetPrefix = "aarch64" in {
 569   class Crypto_AES_DataKey_Intrinsic
 570     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 571
 572   class Crypto_AES_Data_Intrinsic
 573     : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 574
 575   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 576   // (v4i32).
 577   class Crypto_SHA_5Hash4Schedule_Intrinsic
 578     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
 579                 [IntrNoMem]>;
 580
 581   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule
 582   // (v4i32).
 583   class Crypto_SHA_1Hash_Intrinsic
 584     : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
 585
 586   // SHA intrinsic taking 8 words of the schedule
 587   class Crypto_SHA_8Schedule_Intrinsic
 588     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 589
 590   // SHA intrinsic taking 12 words of the schedule
 591   class Crypto_SHA_12Schedule_Intrinsic
 592     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 593                 [IntrNoMem]>;
 594
 595   // SHA intrinsic taking 8 words of the hash and 4 of the schedule.
 596   class Crypto_SHA_8Hash4Schedule_Intrinsic
 597     : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
 598                 [IntrNoMem]>;
 599 }
 600
 601 // AES
 602 def int_aarch64_crypto_aese   : Crypto_AES_DataKey_Intrinsic;
 603 def int_aarch64_crypto_aesd   : Crypto_AES_DataKey_Intrinsic;
 604 def int_aarch64_crypto_aesmc  : Crypto_AES_Data_Intrinsic;
 605 def int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic;
 606
 607 // SHA1
 608 def int_aarch64_crypto_sha1c  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 609 def int_aarch64_crypto_sha1p  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 610 def int_aarch64_crypto_sha1m  : Crypto_SHA_5Hash4Schedule_Intrinsic;
 611 def int_aarch64_crypto_sha1h  : Crypto_SHA_1Hash_Intrinsic;
 612
 613 def int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic;
 614 def int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic;
 615
 616 // SHA256
 617 def int_aarch64_crypto_sha256h   : Crypto_SHA_8Hash4Schedule_Intrinsic;
 618 def int_aarch64_crypto_sha256h2  : Crypto_SHA_8Hash4Schedule_Intrinsic;
 619 def int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic;
 620 def int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic;
 621
 622 //===----------------------------------------------------------------------===//
 623 // CRC32
 624
 625 let TargetPrefix = "aarch64" in {
 626
 627 def int_aarch64_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 628     [IntrNoMem]>;
 629 def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 630     [IntrNoMem]>;
 631 def int_aarch64_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 632     [IntrNoMem]>;
 633 def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 634     [IntrNoMem]>;
 635 def int_aarch64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 636     [IntrNoMem]>;
 637 def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
 638     [IntrNoMem]>;
 639 def int_aarch64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 640     [IntrNoMem]>;
 641 def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
 642     [IntrNoMem]>;
 643 }