1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAGISel class, which is used as the common
11 // base class for SelectionDAG-based instruction selectors.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
16 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Pass.h"
20 #include "llvm/Constant.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
25 class SelectionDAGLowering;
27 class MachineRegisterInfo;
28 class MachineBasicBlock;
29 class MachineFunction;
31 class MachineModuleInfo;
33 class FunctionLoweringInfo;
34 class HazardRecognizer;
38 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
39 /// pattern-matching instruction selectors.
40 class SelectionDAGISel : public FunctionPass {
43 MachineRegisterInfo *RegInfo;
44 FunctionLoweringInfo *FuncInfo;
46 SelectionDAGLowering *SDL;
47 MachineBasicBlock *BB;
51 std::vector<SDNode*> TopOrder;
54 explicit SelectionDAGISel(TargetLowering &tli, bool fast = false);
55 virtual ~SelectionDAGISel();
57 TargetLowering &getTargetLowering() { return TLI; }
59 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
61 virtual bool runOnFunction(Function &Fn);
63 unsigned MakeReg(MVT VT);
65 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
66 virtual void InstructionSelect() = 0;
67 virtual void InstructionSelectPostProcessing() {}
69 void SelectRootInit() {
70 DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
73 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
74 /// addressing mode, according to the specified constraint code. If this does
75 /// not match or is not implemented, return true. The resultant operands
76 /// (which will appear in the machine instruction) should be added to the
78 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
80 std::vector<SDValue> &OutOps) {
84 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
85 /// folded during instruction selection that starts at Root?
86 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
90 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
91 /// to use for this target when scheduling the DAG.
92 virtual HazardRecognizer *CreateTargetHazardRecognizer();
95 /// DAGSize - Size of DAG being instruction selected.
99 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
100 /// by tblgen. Others should not call it.
101 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
103 // Calls to these predicates are generated by tblgen.
104 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
105 int64_t DesiredMaskS) const;
106 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
107 int64_t DesiredMaskS) const;
110 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
111 MachineModuleInfo *MMI);
112 void FinishBasicBlock();
114 void SelectBasicBlock(BasicBlock *LLVMBB,
115 BasicBlock::iterator Begin,
116 BasicBlock::iterator End);
117 void CodeGenAndEmitDAG();
118 void LowerArguments(BasicBlock *BB);
120 void ComputeLiveOutVRegInfo();
122 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
124 bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
126 /// Pick a safe ordering for instructions for each target node in the
128 ScheduleDAG *Schedule();
133 #endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */