1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
60 PassConfigImpl *Impl; // Internal data structures
61 bool Initialized; // Flagged after all passes are configured.
63 // Target Pass Options
64 // Targets provide a default setting, user flags override.
68 /// Default setting for -enable-tail-merge on this target.
72 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
76 virtual ~TargetPassConfig();
80 /// Get the right type of TargetMachine for this target.
81 template<typename TMC> TMC &getTM() const {
82 return *static_cast<TMC*>(TM);
85 const TargetLowering *getTargetLowering() const {
86 return TM->getTargetLowering();
90 void setInitialized() { Initialized = true; }
92 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
94 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
96 bool getEnableTailMerge() const { return EnableTailMerge; }
97 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
99 /// Allow the target to override a specific pass without overriding the pass
100 /// pipeline. When passes are added to the standard pipeline at the
101 /// point where StadardID is expected, add TargetID in its place.
102 void substitutePass(char &StandardID, char &TargetID);
104 /// Allow the target to enable a specific standard pass by default.
105 void enablePass(char &ID) { substitutePass(ID, ID); }
107 /// Allow the target to disable a specific standard pass by default.
108 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
110 /// Return the pass ssubtituted for StandardID by the target.
111 /// If no substitution exists, return StandardID.
112 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
114 /// Return true if the optimized regalloc pipeline is enabled.
115 bool getOptimizeRegAlloc() const;
117 /// Add common target configurable passes that perform LLVM IR to IR
118 /// transforms following machine independent optimization.
119 virtual void addIRPasses();
121 /// Add common passes that perform LLVM IR to IR transforms in preparation for
122 /// instruction selection.
123 virtual void addISelPrepare();
125 /// addInstSelector - This method should install an instruction selector pass,
126 /// which converts from LLVM code to machine instructions.
127 virtual bool addInstSelector() {
131 /// Add the complete, standard set of LLVM CodeGen passes.
132 /// Fully developed targets will not generally override this.
133 virtual void addMachinePasses();
136 // Helper to verify the analysis is really immutable.
137 void setOpt(bool &Opt, bool Val);
139 /// Methods with trivial inline returns are convenient points in the common
140 /// codegen pass pipeline where targets may insert passes. Methods with
141 /// out-of-line standard implementations are major CodeGen stages called by
142 /// addMachinePasses. Some targets may override major stages when inserting
143 /// passes is insufficient, but maintaining overriden stages is more work.
146 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
147 /// passes (which are run just before instruction selector).
148 virtual bool addPreISel() {
152 /// addMachineSSAOptimization - Add standard passes that optimize machine
153 /// instructions in SSA form.
154 virtual void addMachineSSAOptimization();
156 /// addPreRegAlloc - This method may be implemented by targets that want to
157 /// run passes immediately before register allocation. This should return
158 /// true if -print-machineinstrs should print after these passes.
159 virtual bool addPreRegAlloc() {
163 /// createTargetRegisterAllocator - Create the register allocator pass for
164 /// this target at the current optimization level.
165 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
167 /// addFastRegAlloc - Add the minimum set of target-independent passes that
168 /// are required for fast register allocation.
169 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
171 /// addOptimizedRegAlloc - Add passes related to register allocation.
172 /// LLVMTargetMachine provides standard regalloc passes for most targets.
173 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
175 /// addFinalizeRegAlloc - This method may be implemented by targets that want
176 /// to run passes within the regalloc pipeline, immediately after the register
177 /// allocation pass itself. These passes run as soon as virtual regisiters
178 /// have been rewritten to physical registers but before and other postRA
179 /// optimization happens. Targets that have marked instructions for bundling
180 /// must have finalized those bundles by the time these passes have run,
181 /// because subsequent passes are not guaranteed to be bundle-aware.
182 virtual bool addFinalizeRegAlloc() {
186 /// addPostRegAlloc - This method may be implemented by targets that want to
187 /// run passes after register allocation pass pipeline but before
188 /// prolog-epilog insertion. This should return true if -print-machineinstrs
189 /// should print after these passes.
190 virtual bool addPostRegAlloc() {
194 /// Add passes that optimize machine instructions after register allocation.
195 virtual void addMachineLateOptimization();
197 /// addPreSched2 - This method may be implemented by targets that want to
198 /// run passes after prolog-epilog insertion and before the second instruction
199 /// scheduling pass. This should return true if -print-machineinstrs should
200 /// print after these passes.
201 virtual bool addPreSched2() {
205 /// Add standard basic block placement passes.
206 virtual void addBlockPlacement();
208 /// addPreEmitPass - This pass may be implemented by targets that want to run
209 /// passes immediately before machine code is emitted. This should return
210 /// true if -print-machineinstrs should print out the code after the passes.
211 virtual bool addPreEmitPass() {
215 /// Utilities for targets to add passes to the pass manager.
218 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
219 /// Return the pass that was added, or NoPassID.
220 AnalysisID addPass(char &ID);
222 /// addMachinePasses helper to create the target-selected or overriden
224 FunctionPass *createRegAllocPass(bool Optimized);
226 /// printNoVerify - Add a pass to dump the machine function, if debugging is
229 void printNoVerify(const char *Banner) const;
231 /// printAndVerify - Add a pass to dump then verify the machine function, if
232 /// those steps are enabled.
234 void printAndVerify(const char *Banner) const;
238 /// List of target independent CodeGen pass IDs.
240 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
241 /// work well with unreachable basic blocks (what live ranges make sense for a
242 /// block that cannot be reached?). As such, a code generator should either
243 /// not instruction select unreachable blocks, or run this pass as its
244 /// last LLVM modifying pass to clean up blocks that are not reachable from
246 FunctionPass *createUnreachableBlockEliminationPass();
248 /// MachineFunctionPrinter pass - This pass prints out the machine function to
249 /// the given stream as a debugging tool.
250 MachineFunctionPass *
251 createMachineFunctionPrinterPass(raw_ostream &OS,
252 const std::string &Banner ="");
254 /// MachineLoopInfo - This pass is a loop analysis pass.
255 extern char &MachineLoopInfoID;
257 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
258 extern char &MachineLoopRangesID;
260 /// MachineDominators - This pass is a machine dominators analysis pass.
261 extern char &MachineDominatorsID;
263 /// EdgeBundles analysis - Bundle machine CFG edges.
264 extern char &EdgeBundlesID;
266 /// LiveVariables pass - This pass computes the set of blocks in which each
267 /// variable is life and sets machine operand kill flags.
268 extern char &LiveVariablesID;
270 /// PHIElimination - This pass eliminates machine instruction PHI nodes
271 /// by inserting copy instructions. This destroys SSA information, but is the
272 /// desired input for some register allocators. This pass is "required" by
273 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
274 extern char &PHIEliminationID;
276 /// StrongPHIElimination - This pass eliminates machine instruction PHI
277 /// nodes by inserting copy instructions. This destroys SSA information, but
278 /// is the desired input for some register allocators. This pass is
279 /// "required" by these register allocator like this:
280 /// AU.addRequiredID(PHIEliminationID);
281 /// This pass is still in development
282 extern char &StrongPHIEliminationID;
284 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
285 extern char &LiveStacksID;
287 /// TwoAddressInstruction - This pass reduces two-address instructions to
288 /// use two operands. This destroys SSA information but it is desired by
289 /// register allocators.
290 extern char &TwoAddressInstructionPassID;
292 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
293 extern char &ProcessImplicitDefsID;
295 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
296 extern char &RegisterCoalescerID;
298 /// MachineScheduler - This pass schedules machine instructions.
299 extern char &MachineSchedulerID;
301 /// SpillPlacement analysis. Suggest optimal placement of spill code between
303 extern char &SpillPlacementID;
305 /// UnreachableMachineBlockElimination - This pass removes unreachable
306 /// machine basic blocks.
307 extern char &UnreachableMachineBlockElimID;
309 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
310 extern char &DeadMachineInstructionElimID;
312 /// FastRegisterAllocation Pass - This pass register allocates as fast as
313 /// possible. It is best suited for debug code where live ranges are short.
315 FunctionPass *createFastRegisterAllocator();
317 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
318 /// register allocator using the basic regalloc framework.
320 FunctionPass *createBasicRegisterAllocator();
322 /// Greedy register allocation pass - This pass implements a global register
323 /// allocator for optimized builds.
325 FunctionPass *createGreedyRegisterAllocator();
327 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
328 /// Quadratic Prograaming (PBQP) based register allocator.
330 FunctionPass *createDefaultPBQPRegisterAllocator();
332 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
333 /// and eliminates abstract frame references.
334 extern char &PrologEpilogCodeInserterID;
336 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
337 /// register allocation.
338 extern char &ExpandPostRAPseudosID;
340 /// createPostRAScheduler - This pass performs post register allocation
342 extern char &PostRASchedulerID;
344 /// BranchFolding - This pass performs machine code CFG based
345 /// optimizations to delete branches to branches, eliminate branches to
346 /// successor blocks (creating fall throughs), and eliminating branches over
348 extern char &BranchFolderPassID;
350 /// TailDuplicate - Duplicate blocks with unconditional branches
351 /// into tails of their predecessors.
352 extern char &TailDuplicateID;
354 /// IfConverter - This pass performs machine code if conversion.
355 extern char &IfConverterID;
357 /// MachineBlockPlacement - This pass places basic blocks based on branch
359 extern char &MachineBlockPlacementID;
361 /// MachineBlockPlacementStats - This pass collects statistics about the
362 /// basic block placement using branch probabilities and block frequency
364 extern char &MachineBlockPlacementStatsID;
366 /// Code Placement - This pass optimize code placement and aligns loop
367 /// headers to target specific alignment boundary.
368 extern char &CodePlacementOptID;
370 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
371 /// highly portable strategies.
373 FunctionPass *createGCLoweringPass();
375 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
376 /// in machine code. Must be added very late during code generation, just
377 /// prior to output, and importantly after all CFG transformations (such as
379 extern char &GCMachineCodeAnalysisID;
381 /// Deleter Pass - Releases GC metadata.
383 FunctionPass *createGCInfoDeleter();
385 /// Creates a pass to print GC metadata.
387 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
389 /// MachineCSE - This pass performs global CSE on machine instructions.
390 extern char &MachineCSEID;
392 /// MachineLICM - This pass performs LICM on machine instructions.
393 extern char &MachineLICMID;
395 /// MachineSinking - This pass performs sinking on machine instructions.
396 extern char &MachineSinkingID;
398 /// MachineCopyPropagation - This pass performs copy propagation on
399 /// machine instructions.
400 extern char &MachineCopyPropagationID;
402 /// PeepholeOptimizer - This pass performs peephole optimizations -
403 /// like extension and comparison eliminations.
404 extern char &PeepholeOptimizerID;
406 /// OptimizePHIs - This pass optimizes machine instruction PHIs
407 /// to take advantage of opportunities created during DAG legalization.
408 extern char &OptimizePHIsID;
410 /// StackSlotColoring - This pass performs stack slot coloring.
411 extern char &StackSlotColoringID;
413 /// createStackProtectorPass - This pass adds stack protectors to functions.
415 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
417 /// createMachineVerifierPass - This pass verifies cenerated machine code
418 /// instructions for correctness.
420 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
422 /// createDwarfEHPass - This pass mulches exception handling code into a form
423 /// adapted to code generation. Required if using dwarf exception handling.
424 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
426 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
427 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
429 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
431 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
432 /// slots relative to one another and allocates base registers to access them
433 /// when it is estimated by the target to be out of range of normal frame
434 /// pointer or stack pointer index addressing.
435 extern char &LocalStackSlotAllocationID;
437 /// ExpandISelPseudos - This pass expands pseudo-instructions.
438 extern char &ExpandISelPseudosID;
440 /// createExecutionDependencyFixPass - This pass fixes execution time
441 /// problems with dependent instructions, such as switching execution
442 /// domains to match.
444 /// The pass will examine instructions using and defining registers in RC.
446 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
448 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
449 extern char &UnpackMachineBundlesID;
451 /// FinalizeMachineBundles - This pass finalize machine instruction
452 /// bundles (created earlier, e.g. during pre-RA scheduling).
453 extern char &FinalizeMachineBundlesID;
455 } // End llvm namespace