1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
60 PassConfigImpl *Impl; // Internal data structures
61 bool Initialized; // Flagged after all passes are configured.
63 // Target Pass Options
64 // Targets provide a default setting, user flags override.
68 /// Default setting for -enable-tail-merge on this target.
72 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
76 virtual ~TargetPassConfig();
80 /// Get the right type of TargetMachine for this target.
81 template<typename TMC> TMC &getTM() const {
82 return *static_cast<TMC*>(TM);
85 const TargetLowering *getTargetLowering() const {
86 return TM->getTargetLowering();
90 void setInitialized() { Initialized = true; }
92 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
94 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
96 bool getEnableTailMerge() const { return EnableTailMerge; }
97 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
99 /// Allow the target to override a specific pass without overriding the pass
100 /// pipeline. When passes are added to the standard pipeline at the
101 /// point where StadardID is expected, add TargetID in its place.
102 void substitutePass(char &StandardID, char &TargetID);
104 /// Allow the target to disable a specific standard pass.
105 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
107 /// Return the pass ssubtituted for StandardID by the target.
108 /// If no substitution exists, return StandardID.
109 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
111 /// Return true if the optimized regalloc pipeline is enabled.
112 bool getOptimizeRegAlloc() const;
114 /// Add common target configurable passes that perform LLVM IR to IR
115 /// transforms following machine independent optimization.
116 virtual void addIRPasses();
118 /// Add common passes that perform LLVM IR to IR transforms in preparation for
119 /// instruction selection.
120 virtual void addISelPrepare();
122 /// addInstSelector - This method should install an instruction selector pass,
123 /// which converts from LLVM code to machine instructions.
124 virtual bool addInstSelector() {
128 /// Add the complete, standard set of LLVM CodeGen passes.
129 /// Fully developed targets will not generally override this.
130 virtual void addMachinePasses();
133 // Helper to verify the analysis is really immutable.
134 void setOpt(bool &Opt, bool Val);
136 /// Methods with trivial inline returns are convenient points in the common
137 /// codegen pass pipeline where targets may insert passes. Methods with
138 /// out-of-line standard implementations are major CodeGen stages called by
139 /// addMachinePasses. Some targets may override major stages when inserting
140 /// passes is insufficient, but maintaining overriden stages is more work.
143 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
144 /// passes (which are run just before instruction selector).
145 virtual bool addPreISel() {
149 /// addMachineSSAOptimization - Add standard passes that optimize machine
150 /// instructions in SSA form.
151 virtual void addMachineSSAOptimization();
153 /// addPreRegAlloc - This method may be implemented by targets that want to
154 /// run passes immediately before register allocation. This should return
155 /// true if -print-machineinstrs should print after these passes.
156 virtual bool addPreRegAlloc() {
160 /// createTargetRegisterAllocator - Create the register allocator pass for
161 /// this target at the current optimization level.
162 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
164 /// addFastRegAlloc - Add the minimum set of target-independent passes that
165 /// are required for fast register allocation.
166 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
168 /// addOptimizedRegAlloc - Add passes related to register allocation.
169 /// LLVMTargetMachine provides standard regalloc passes for most targets.
170 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
172 /// addFinalizeRegAlloc - This method may be implemented by targets that want
173 /// to run passes within the regalloc pipeline, immediately after the register
174 /// allocation pass itself. These passes run as soon as virtual regisiters
175 /// have been rewritten to physical registers but before and other postRA
176 /// optimization happens. Targets that have marked instructions for bundling
177 /// must have finalized those bundles by the time these passes have run,
178 /// because subsequent passes are not guaranteed to be bundle-aware.
179 virtual bool addFinalizeRegAlloc() {
183 /// addPostRegAlloc - This method may be implemented by targets that want to
184 /// run passes after register allocation pass pipeline but before
185 /// prolog-epilog insertion. This should return true if -print-machineinstrs
186 /// should print after these passes.
187 virtual bool addPostRegAlloc() {
191 /// Add passes that optimize machine instructions after register allocation.
192 virtual void addMachineLateOptimization();
194 /// addPreSched2 - This method may be implemented by targets that want to
195 /// run passes after prolog-epilog insertion and before the second instruction
196 /// scheduling pass. This should return true if -print-machineinstrs should
197 /// print after these passes.
198 virtual bool addPreSched2() {
202 /// Add standard basic block placement passes.
203 virtual void addBlockPlacement();
205 /// addPreEmitPass - This pass may be implemented by targets that want to run
206 /// passes immediately before machine code is emitted. This should return
207 /// true if -print-machineinstrs should print out the code after the passes.
208 virtual bool addPreEmitPass() {
212 /// Utilities for targets to add passes to the pass manager.
215 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
216 /// Return the pass that was added, or NoPassID.
217 AnalysisID addPass(char &ID);
219 /// addMachinePasses helper to create the target-selected or overriden
221 FunctionPass *createRegAllocPass(bool Optimized);
223 /// printNoVerify - Add a pass to dump the machine function, if debugging is
226 void printNoVerify(const char *Banner) const;
228 /// printAndVerify - Add a pass to dump then verify the machine function, if
229 /// those steps are enabled.
231 void printAndVerify(const char *Banner) const;
235 /// List of target independent CodeGen pass IDs.
237 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
238 /// work well with unreachable basic blocks (what live ranges make sense for a
239 /// block that cannot be reached?). As such, a code generator should either
240 /// not instruction select unreachable blocks, or run this pass as its
241 /// last LLVM modifying pass to clean up blocks that are not reachable from
243 FunctionPass *createUnreachableBlockEliminationPass();
245 /// MachineFunctionPrinter pass - This pass prints out the machine function to
246 /// the given stream as a debugging tool.
247 MachineFunctionPass *
248 createMachineFunctionPrinterPass(raw_ostream &OS,
249 const std::string &Banner ="");
251 /// MachineLoopInfo - This pass is a loop analysis pass.
252 extern char &MachineLoopInfoID;
254 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
255 extern char &MachineLoopRangesID;
257 /// MachineDominators - This pass is a machine dominators analysis pass.
258 extern char &MachineDominatorsID;
260 /// EdgeBundles analysis - Bundle machine CFG edges.
261 extern char &EdgeBundlesID;
263 /// LiveVariables pass - This pass computes the set of blocks in which each
264 /// variable is life and sets machine operand kill flags.
265 extern char &LiveVariablesID;
267 /// PHIElimination - This pass eliminates machine instruction PHI nodes
268 /// by inserting copy instructions. This destroys SSA information, but is the
269 /// desired input for some register allocators. This pass is "required" by
270 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
271 extern char &PHIEliminationID;
273 /// StrongPHIElimination - This pass eliminates machine instruction PHI
274 /// nodes by inserting copy instructions. This destroys SSA information, but
275 /// is the desired input for some register allocators. This pass is
276 /// "required" by these register allocator like this:
277 /// AU.addRequiredID(PHIEliminationID);
278 /// This pass is still in development
279 extern char &StrongPHIEliminationID;
281 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
282 extern char &LiveStacksID;
284 /// TwoAddressInstruction - This pass reduces two-address instructions to
285 /// use two operands. This destroys SSA information but it is desired by
286 /// register allocators.
287 extern char &TwoAddressInstructionPassID;
289 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
290 extern char &ProcessImplicitDefsID;
292 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
293 extern char &RegisterCoalescerID;
295 /// MachineScheduler - This pass schedules machine instructions.
296 extern char &MachineSchedulerID;
298 /// SpillPlacement analysis. Suggest optimal placement of spill code between
300 extern char &SpillPlacementID;
302 /// UnreachableMachineBlockElimination - This pass removes unreachable
303 /// machine basic blocks.
304 extern char &UnreachableMachineBlockElimID;
306 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
307 extern char &DeadMachineInstructionElimID;
309 /// FastRegisterAllocation Pass - This pass register allocates as fast as
310 /// possible. It is best suited for debug code where live ranges are short.
312 FunctionPass *createFastRegisterAllocator();
314 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
315 /// register allocator using the basic regalloc framework.
317 FunctionPass *createBasicRegisterAllocator();
319 /// Greedy register allocation pass - This pass implements a global register
320 /// allocator for optimized builds.
322 FunctionPass *createGreedyRegisterAllocator();
324 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
325 /// Quadratic Prograaming (PBQP) based register allocator.
327 FunctionPass *createDefaultPBQPRegisterAllocator();
329 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
330 /// and eliminates abstract frame references.
331 extern char &PrologEpilogCodeInserterID;
333 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
334 /// register allocation.
335 extern char &ExpandPostRAPseudosID;
337 /// createPostRAScheduler - This pass performs post register allocation
339 extern char &PostRASchedulerID;
341 /// BranchFolding - This pass performs machine code CFG based
342 /// optimizations to delete branches to branches, eliminate branches to
343 /// successor blocks (creating fall throughs), and eliminating branches over
345 extern char &BranchFolderPassID;
347 /// TailDuplicate - Duplicate blocks with unconditional branches
348 /// into tails of their predecessors.
349 extern char &TailDuplicateID;
351 /// IfConverter - This pass performs machine code if conversion.
352 extern char &IfConverterID;
354 /// MachineBlockPlacement - This pass places basic blocks based on branch
356 extern char &MachineBlockPlacementID;
358 /// MachineBlockPlacementStats - This pass collects statistics about the
359 /// basic block placement using branch probabilities and block frequency
361 extern char &MachineBlockPlacementStatsID;
363 /// Code Placement - This pass optimize code placement and aligns loop
364 /// headers to target specific alignment boundary.
365 extern char &CodePlacementOptID;
367 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
368 /// highly portable strategies.
370 FunctionPass *createGCLoweringPass();
372 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
373 /// in machine code. Must be added very late during code generation, just
374 /// prior to output, and importantly after all CFG transformations (such as
376 extern char &GCMachineCodeAnalysisID;
378 /// Deleter Pass - Releases GC metadata.
380 FunctionPass *createGCInfoDeleter();
382 /// Creates a pass to print GC metadata.
384 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
386 /// MachineCSE - This pass performs global CSE on machine instructions.
387 extern char &MachineCSEID;
389 /// MachineLICM - This pass performs LICM on machine instructions.
390 extern char &MachineLICMID;
392 /// MachineSinking - This pass performs sinking on machine instructions.
393 extern char &MachineSinkingID;
395 /// MachineCopyPropagation - This pass performs copy propagation on
396 /// machine instructions.
397 extern char &MachineCopyPropagationID;
399 /// PeepholeOptimizer - This pass performs peephole optimizations -
400 /// like extension and comparison eliminations.
401 extern char &PeepholeOptimizerID;
403 /// OptimizePHIs - This pass optimizes machine instruction PHIs
404 /// to take advantage of opportunities created during DAG legalization.
405 extern char &OptimizePHIsID;
407 /// StackSlotColoring - This pass performs stack slot coloring.
408 extern char &StackSlotColoringID;
410 /// createStackProtectorPass - This pass adds stack protectors to functions.
412 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
414 /// createMachineVerifierPass - This pass verifies cenerated machine code
415 /// instructions for correctness.
417 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
419 /// createDwarfEHPass - This pass mulches exception handling code into a form
420 /// adapted to code generation. Required if using dwarf exception handling.
421 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
423 /// createSjLjEHPass - This pass adapts exception handling code to use
424 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
426 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
428 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
429 /// slots relative to one another and allocates base registers to access them
430 /// when it is estimated by the target to be out of range of normal frame
431 /// pointer or stack pointer index addressing.
432 extern char &LocalStackSlotAllocationID;
434 /// ExpandISelPseudos - This pass expands pseudo-instructions.
435 extern char &ExpandISelPseudosID;
437 /// createExecutionDependencyFixPass - This pass fixes execution time
438 /// problems with dependent instructions, such as switching execution
439 /// domains to match.
441 /// The pass will examine instructions using and defining registers in RC.
443 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
445 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
446 extern char &UnpackMachineBundlesID;
448 /// FinalizeMachineBundles - This pass finalize machine instruction
449 /// bundles (created earlier, e.g. during pre-RA scheduling).
450 extern char &FinalizeMachineBundlesID;
452 } // End llvm namespace