1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
27 class PassManagerBase;
29 class TargetRegisterClass;
35 extern char &NoPassID; // Allow targets to choose not to run a pass.
39 /// Target-Independent Code Generator Pass Configuration Options.
41 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
42 /// to the internals of other CodeGen passes.
43 class TargetPassConfig : public ImmutablePass {
45 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
46 /// are unregistered pass IDs. They are only useful for use with
47 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
50 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
51 /// during codegen, on SSA form.
52 static char EarlyTailDuplicateID;
54 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
55 /// optimization after regalloc.
56 static char PostRAMachineLICMID;
61 PassConfigImpl *Impl; // Internal data structures
62 bool Initialized; // Flagged after all passes are configured.
64 // Target Pass Options
65 // Targets provide a default setting, user flags override.
69 /// Default setting for -enable-tail-merge on this target.
73 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
77 virtual ~TargetPassConfig();
81 /// Get the right type of TargetMachine for this target.
82 template<typename TMC> TMC &getTM() const {
83 return *static_cast<TMC*>(TM);
86 const TargetLowering *getTargetLowering() const {
87 return TM->getTargetLowering();
91 void setInitialized() { Initialized = true; }
93 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
95 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
97 bool getEnableTailMerge() const { return EnableTailMerge; }
98 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
100 /// Allow the target to override a specific pass without overriding the pass
101 /// pipeline. When passes are added to the standard pipeline at the
102 /// point where StadardID is expected, add TargetID in its place.
103 void substitutePass(char &StandardID, char &TargetID);
105 /// Insert InsertedPassID pass after TargetPassID pass.
106 void insertPass(const char &TargetPassID, const char &InsertedPassID);
108 /// Allow the target to enable a specific standard pass by default.
109 void enablePass(char &ID) { substitutePass(ID, ID); }
111 /// Allow the target to disable a specific standard pass by default.
112 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
114 /// Return the pass ssubtituted for StandardID by the target.
115 /// If no substitution exists, return StandardID.
116 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
118 /// Return true if the optimized regalloc pipeline is enabled.
119 bool getOptimizeRegAlloc() const;
121 /// Add common target configurable passes that perform LLVM IR to IR
122 /// transforms following machine independent optimization.
123 virtual void addIRPasses();
125 /// Add common passes that perform LLVM IR to IR transforms in preparation for
126 /// instruction selection.
127 virtual void addISelPrepare();
129 /// addInstSelector - This method should install an instruction selector pass,
130 /// which converts from LLVM code to machine instructions.
131 virtual bool addInstSelector() {
135 /// Add the complete, standard set of LLVM CodeGen passes.
136 /// Fully developed targets will not generally override this.
137 virtual void addMachinePasses();
140 // Helper to verify the analysis is really immutable.
141 void setOpt(bool &Opt, bool Val);
143 /// Methods with trivial inline returns are convenient points in the common
144 /// codegen pass pipeline where targets may insert passes. Methods with
145 /// out-of-line standard implementations are major CodeGen stages called by
146 /// addMachinePasses. Some targets may override major stages when inserting
147 /// passes is insufficient, but maintaining overriden stages is more work.
150 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
151 /// passes (which are run just before instruction selector).
152 virtual bool addPreISel() {
156 /// addMachineSSAOptimization - Add standard passes that optimize machine
157 /// instructions in SSA form.
158 virtual void addMachineSSAOptimization();
160 /// addPreRegAlloc - This method may be implemented by targets that want to
161 /// run passes immediately before register allocation. This should return
162 /// true if -print-machineinstrs should print after these passes.
163 virtual bool addPreRegAlloc() {
167 /// createTargetRegisterAllocator - Create the register allocator pass for
168 /// this target at the current optimization level.
169 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
171 /// addFastRegAlloc - Add the minimum set of target-independent passes that
172 /// are required for fast register allocation.
173 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
175 /// addOptimizedRegAlloc - Add passes related to register allocation.
176 /// LLVMTargetMachine provides standard regalloc passes for most targets.
177 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
179 /// addPreRewrite - Add passes to the optimized register allocation pipeline
180 /// after register allocation is complete, but before virtual registers are
181 /// rewritten to physical registers.
183 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
184 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
185 /// When these passes run, VirtRegMap contains legal physreg assignments for
186 /// all virtual registers.
187 virtual bool addPreRewrite() {
191 /// addFinalizeRegAlloc - This method may be implemented by targets that want
192 /// to run passes within the regalloc pipeline, immediately after the register
193 /// allocation pass itself. These passes run as soon as virtual regisiters
194 /// have been rewritten to physical registers but before and other postRA
195 /// optimization happens. Targets that have marked instructions for bundling
196 /// must have finalized those bundles by the time these passes have run,
197 /// because subsequent passes are not guaranteed to be bundle-aware.
198 virtual bool addFinalizeRegAlloc() {
202 /// addPostRegAlloc - This method may be implemented by targets that want to
203 /// run passes after register allocation pass pipeline but before
204 /// prolog-epilog insertion. This should return true if -print-machineinstrs
205 /// should print after these passes.
206 virtual bool addPostRegAlloc() {
210 /// Add passes that optimize machine instructions after register allocation.
211 virtual void addMachineLateOptimization();
213 /// addPreSched2 - This method may be implemented by targets that want to
214 /// run passes after prolog-epilog insertion and before the second instruction
215 /// scheduling pass. This should return true if -print-machineinstrs should
216 /// print after these passes.
217 virtual bool addPreSched2() {
221 /// Add standard basic block placement passes.
222 virtual void addBlockPlacement();
224 /// addPreEmitPass - This pass may be implemented by targets that want to run
225 /// passes immediately before machine code is emitted. This should return
226 /// true if -print-machineinstrs should print out the code after the passes.
227 virtual bool addPreEmitPass() {
231 /// Utilities for targets to add passes to the pass manager.
234 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
235 /// Return the pass that was added, or NoPassID.
236 AnalysisID addPass(char &ID);
238 /// addMachinePasses helper to create the target-selected or overriden
240 FunctionPass *createRegAllocPass(bool Optimized);
242 /// printAndVerify - Add a pass to dump then verify the machine function, if
243 /// those steps are enabled.
245 void printAndVerify(const char *Banner) const;
249 /// List of target independent CodeGen pass IDs.
251 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
252 /// work well with unreachable basic blocks (what live ranges make sense for a
253 /// block that cannot be reached?). As such, a code generator should either
254 /// not instruction select unreachable blocks, or run this pass as its
255 /// last LLVM modifying pass to clean up blocks that are not reachable from
257 FunctionPass *createUnreachableBlockEliminationPass();
259 /// MachineFunctionPrinter pass - This pass prints out the machine function to
260 /// the given stream as a debugging tool.
261 MachineFunctionPass *
262 createMachineFunctionPrinterPass(raw_ostream &OS,
263 const std::string &Banner ="");
265 /// MachineLoopInfo - This pass is a loop analysis pass.
266 extern char &MachineLoopInfoID;
268 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
269 extern char &MachineLoopRangesID;
271 /// MachineDominators - This pass is a machine dominators analysis pass.
272 extern char &MachineDominatorsID;
274 /// EdgeBundles analysis - Bundle machine CFG edges.
275 extern char &EdgeBundlesID;
277 /// LiveVariables pass - This pass computes the set of blocks in which each
278 /// variable is life and sets machine operand kill flags.
279 extern char &LiveVariablesID;
281 /// PHIElimination - This pass eliminates machine instruction PHI nodes
282 /// by inserting copy instructions. This destroys SSA information, but is the
283 /// desired input for some register allocators. This pass is "required" by
284 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
285 extern char &PHIEliminationID;
287 /// StrongPHIElimination - This pass eliminates machine instruction PHI
288 /// nodes by inserting copy instructions. This destroys SSA information, but
289 /// is the desired input for some register allocators. This pass is
290 /// "required" by these register allocator like this:
291 /// AU.addRequiredID(PHIEliminationID);
292 /// This pass is still in development
293 extern char &StrongPHIEliminationID;
295 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
296 extern char &LiveStacksID;
298 /// TwoAddressInstruction - This pass reduces two-address instructions to
299 /// use two operands. This destroys SSA information but it is desired by
300 /// register allocators.
301 extern char &TwoAddressInstructionPassID;
303 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
304 extern char &ProcessImplicitDefsID;
306 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
307 extern char &RegisterCoalescerID;
309 /// MachineScheduler - This pass schedules machine instructions.
310 extern char &MachineSchedulerID;
312 /// SpillPlacement analysis. Suggest optimal placement of spill code between
314 extern char &SpillPlacementID;
316 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
317 /// assigned in VirtRegMap.
318 extern char &VirtRegRewriterID;
320 /// UnreachableMachineBlockElimination - This pass removes unreachable
321 /// machine basic blocks.
322 extern char &UnreachableMachineBlockElimID;
324 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
325 extern char &DeadMachineInstructionElimID;
327 /// FastRegisterAllocation Pass - This pass register allocates as fast as
328 /// possible. It is best suited for debug code where live ranges are short.
330 FunctionPass *createFastRegisterAllocator();
332 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
333 /// register allocator using the basic regalloc framework.
335 FunctionPass *createBasicRegisterAllocator();
337 /// Greedy register allocation pass - This pass implements a global register
338 /// allocator for optimized builds.
340 FunctionPass *createGreedyRegisterAllocator();
342 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
343 /// Quadratic Prograaming (PBQP) based register allocator.
345 FunctionPass *createDefaultPBQPRegisterAllocator();
347 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
348 /// and eliminates abstract frame references.
349 extern char &PrologEpilogCodeInserterID;
351 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
352 /// register allocation.
353 extern char &ExpandPostRAPseudosID;
355 /// createPostRAScheduler - This pass performs post register allocation
357 extern char &PostRASchedulerID;
359 /// BranchFolding - This pass performs machine code CFG based
360 /// optimizations to delete branches to branches, eliminate branches to
361 /// successor blocks (creating fall throughs), and eliminating branches over
363 extern char &BranchFolderPassID;
365 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
366 extern char &MachineFunctionPrinterPassID;
368 /// TailDuplicate - Duplicate blocks with unconditional branches
369 /// into tails of their predecessors.
370 extern char &TailDuplicateID;
372 /// IfConverter - This pass performs machine code if conversion.
373 extern char &IfConverterID;
375 /// MachineBlockPlacement - This pass places basic blocks based on branch
377 extern char &MachineBlockPlacementID;
379 /// MachineBlockPlacementStats - This pass collects statistics about the
380 /// basic block placement using branch probabilities and block frequency
382 extern char &MachineBlockPlacementStatsID;
384 /// Code Placement - This pass optimize code placement and aligns loop
385 /// headers to target specific alignment boundary.
386 extern char &CodePlacementOptID;
388 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
389 /// highly portable strategies.
391 FunctionPass *createGCLoweringPass();
393 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
394 /// in machine code. Must be added very late during code generation, just
395 /// prior to output, and importantly after all CFG transformations (such as
397 extern char &GCMachineCodeAnalysisID;
399 /// Deleter Pass - Releases GC metadata.
401 FunctionPass *createGCInfoDeleter();
403 /// Creates a pass to print GC metadata.
405 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
407 /// MachineCSE - This pass performs global CSE on machine instructions.
408 extern char &MachineCSEID;
410 /// MachineLICM - This pass performs LICM on machine instructions.
411 extern char &MachineLICMID;
413 /// MachineSinking - This pass performs sinking on machine instructions.
414 extern char &MachineSinkingID;
416 /// MachineCopyPropagation - This pass performs copy propagation on
417 /// machine instructions.
418 extern char &MachineCopyPropagationID;
420 /// PeepholeOptimizer - This pass performs peephole optimizations -
421 /// like extension and comparison eliminations.
422 extern char &PeepholeOptimizerID;
424 /// OptimizePHIs - This pass optimizes machine instruction PHIs
425 /// to take advantage of opportunities created during DAG legalization.
426 extern char &OptimizePHIsID;
428 /// StackSlotColoring - This pass performs stack slot coloring.
429 extern char &StackSlotColoringID;
431 /// createStackProtectorPass - This pass adds stack protectors to functions.
433 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
435 /// createMachineVerifierPass - This pass verifies cenerated machine code
436 /// instructions for correctness.
438 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
440 /// createDwarfEHPass - This pass mulches exception handling code into a form
441 /// adapted to code generation. Required if using dwarf exception handling.
442 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
444 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
445 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
447 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
449 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
450 /// slots relative to one another and allocates base registers to access them
451 /// when it is estimated by the target to be out of range of normal frame
452 /// pointer or stack pointer index addressing.
453 extern char &LocalStackSlotAllocationID;
455 /// ExpandISelPseudos - This pass expands pseudo-instructions.
456 extern char &ExpandISelPseudosID;
458 /// createExecutionDependencyFixPass - This pass fixes execution time
459 /// problems with dependent instructions, such as switching execution
460 /// domains to match.
462 /// The pass will examine instructions using and defining registers in RC.
464 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
466 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
467 extern char &UnpackMachineBundlesID;
469 /// FinalizeMachineBundles - This pass finalize machine instruction
470 /// bundles (created earlier, e.g. during pre-RA scheduling).
471 extern char &FinalizeMachineBundlesID;
473 } // End llvm namespace