1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
36 /// Target-Independent Code Generator Pass Configuration Options.
38 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
39 /// to the internals of other CodeGen passes.
40 class TargetPassConfig : public ImmutablePass {
44 bool Initialized; // Flagged after all passes are configured.
46 // Target Pass Options
47 // Targets provide a default setting, user flags override.
51 /// Default setting for -enable-tail-merge on this target.
55 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
59 virtual ~TargetPassConfig();
63 /// Get the right type of TargetMachine for this target.
64 template<typename TMC> TMC &getTM() const {
65 return *static_cast<TMC*>(TM);
68 const TargetLowering *getTargetLowering() const {
69 return TM->getTargetLowering();
72 void setInitialized() { Initialized = true; }
74 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
76 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
78 bool getEnableTailMerge() const { return EnableTailMerge; }
79 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
81 bool getOptimizeRegAlloc() const;
83 /// Add common target configurable passes that perform LLVM IR to IR
84 /// transforms following machine independent optimization.
85 virtual void addIRPasses();
87 /// Add common passes that perform LLVM IR to IR transforms in preparation for
88 /// instruction selection.
89 virtual void addISelPrepare();
91 /// addInstSelector - This method should install an instruction selector pass,
92 /// which converts from LLVM code to machine instructions.
93 virtual bool addInstSelector() {
97 /// Add the complete, standard set of LLVM CodeGen passes.
98 /// Fully developed targets will not generally override this.
99 virtual void addMachinePasses();
102 // Helper to verify the analysis is really immutable.
103 void setOpt(bool &Opt, bool Val);
105 /// Methods with trivial inline returns are convenient points in the common
106 /// codegen pass pipeline where targets may insert passes. Methods with
107 /// out-of-line standard implementations are major CodeGen stages called by
108 /// addMachinePasses. Some targets may override major stages when inserting
109 /// passes is insufficient, but maintaining overriden stages is more work.
112 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
113 /// passes (which are run just before instruction selector).
114 virtual bool addPreISel() {
118 /// addMachineSSAOptimization - Add standard passes that optimize machine
119 /// instructions in SSA form.
120 virtual void addMachineSSAOptimization();
122 /// addPreRegAlloc - This method may be implemented by targets that want to
123 /// run passes immediately before register allocation. This should return
124 /// true if -print-machineinstrs should print after these passes.
125 virtual bool addPreRegAlloc() {
129 /// createTargetRegisterAllocator - Create the register allocator pass for
130 /// this target at the current optimization level.
131 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
133 /// addFastRegAlloc - Add the minimum set of target-independent passes that
134 /// are required for fast register allocation.
135 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
137 /// addOptimizedRegAlloc - Add passes related to register allocation.
138 /// LLVMTargetMachine provides standard regalloc passes for most targets.
139 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
141 /// getSchedPass - This method may be implemented by target that want to
142 /// completely override the MachineScheduler pass with a new pass, rather than
143 /// inheriting from ScheduleDAGInstrs.
144 virtual char &getSchedPass() { return NoPassID; }
146 /// addFinalizeRegAlloc - This method may be implemented by targets that want
147 /// to run passes within the regalloc pipeline, immediately after the register
148 /// allocation pass itself. These passes run as soon as virtual regisiters
149 /// have been rewritten to physical registers but before and other postRA
150 /// optimization happens. Targets that have marked instructions for bundling
151 /// must have finalized those bundles by the time these passes have run,
152 /// because subsequent passes are not guaranteed to be bundle-aware.
153 virtual bool addFinalizeRegAlloc() {
157 /// addPostRegAlloc - This method may be implemented by targets that want to
158 /// run passes after register allocation pass pipeline but before
159 /// prolog-epilog insertion. This should return true if -print-machineinstrs
160 /// should print after these passes.
161 virtual bool addPostRegAlloc() {
165 /// Add passes that optimize machine instructions after register allocation.
166 virtual void addMachineLateOptimization();
168 /// addPreSched2 - This method may be implemented by targets that want to
169 /// run passes after prolog-epilog insertion and before the second instruction
170 /// scheduling pass. This should return true if -print-machineinstrs should
171 /// print after these passes.
172 virtual bool addPreSched2() {
176 /// Add standard basic block placement passes.
177 virtual void addBlockPlacement();
179 /// addPreEmitPass - This pass may be implemented by targets that want to run
180 /// passes immediately before machine code is emitted. This should return
181 /// true if -print-machineinstrs should print out the code after the passes.
182 virtual bool addPreEmitPass() {
186 /// Utilities for targets to add passes to the pass manager.
189 /// Add a target-independent CodeGen pass at this point in the pipeline.
190 void addPass(char &ID);
192 /// addMachinePasses helper to create the target-selected or overriden
194 FunctionPass *createRegAllocPass(bool Optimized);
196 /// printNoVerify - Add a pass to dump the machine function, if debugging is
199 void printNoVerify(const char *Banner) const;
201 /// printAndVerify - Add a pass to dump then verify the machine function, if
202 /// those steps are enabled.
204 void printAndVerify(const char *Banner) const;
208 /// List of target independent CodeGen pass IDs.
210 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
211 /// work well with unreachable basic blocks (what live ranges make sense for a
212 /// block that cannot be reached?). As such, a code generator should either
213 /// not instruction select unreachable blocks, or run this pass as its
214 /// last LLVM modifying pass to clean up blocks that are not reachable from
216 FunctionPass *createUnreachableBlockEliminationPass();
218 /// MachineFunctionPrinter pass - This pass prints out the machine function to
219 /// the given stream as a debugging tool.
220 MachineFunctionPass *
221 createMachineFunctionPrinterPass(raw_ostream &OS,
222 const std::string &Banner ="");
224 /// MachineLoopInfo - This pass is a loop analysis pass.
225 extern char &MachineLoopInfoID;
227 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
228 extern char &MachineLoopRangesID;
230 /// MachineDominators - This pass is a machine dominators analysis pass.
231 extern char &MachineDominatorsID;
233 /// EdgeBundles analysis - Bundle machine CFG edges.
234 extern char &EdgeBundlesID;
236 /// LiveVariables pass - This pass computes the set of blocks in which each
237 /// variable is life and sets machine operand kill flags.
238 extern char &LiveVariablesID;
240 /// PHIElimination - This pass eliminates machine instruction PHI nodes
241 /// by inserting copy instructions. This destroys SSA information, but is the
242 /// desired input for some register allocators. This pass is "required" by
243 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
244 extern char &PHIEliminationID;
246 /// StrongPHIElimination - This pass eliminates machine instruction PHI
247 /// nodes by inserting copy instructions. This destroys SSA information, but
248 /// is the desired input for some register allocators. This pass is
249 /// "required" by these register allocator like this:
250 /// AU.addRequiredID(PHIEliminationID);
251 /// This pass is still in development
252 extern char &StrongPHIEliminationID;
254 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
255 extern char &LiveStacksID;
257 /// TwoAddressInstruction - This pass reduces two-address instructions to
258 /// use two operands. This destroys SSA information but it is desired by
259 /// register allocators.
260 extern char &TwoAddressInstructionPassID;
262 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
263 extern char &ProcessImplicitDefsID;
265 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
266 extern char &RegisterCoalescerID;
268 /// MachineScheduler - This pass schedules machine instructions.
269 extern char &MachineSchedulerID;
271 /// SpillPlacement analysis. Suggest optimal placement of spill code between
273 extern char &SpillPlacementID;
275 /// UnreachableMachineBlockElimination - This pass removes unreachable
276 /// machine basic blocks.
277 extern char &UnreachableMachineBlockElimID;
279 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
280 extern char &DeadMachineInstructionElimID;
282 /// FastRegisterAllocation Pass - This pass register allocates as fast as
283 /// possible. It is best suited for debug code where live ranges are short.
285 FunctionPass *createFastRegisterAllocator();
287 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
288 /// register allocator using the basic regalloc framework.
290 FunctionPass *createBasicRegisterAllocator();
292 /// Greedy register allocation pass - This pass implements a global register
293 /// allocator for optimized builds.
295 FunctionPass *createGreedyRegisterAllocator();
297 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
298 /// Quadratic Prograaming (PBQP) based register allocator.
300 FunctionPass *createDefaultPBQPRegisterAllocator();
302 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
303 /// and eliminates abstract frame references.
304 extern char &PrologEpilogCodeInserterID;
306 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
307 /// register allocation.
308 extern char &ExpandPostRAPseudosID;
310 /// createPostRAScheduler - This pass performs post register allocation
312 extern char &PostRASchedulerID;
314 /// BranchFolding - This pass performs machine code CFG based
315 /// optimizations to delete branches to branches, eliminate branches to
316 /// successor blocks (creating fall throughs), and eliminating branches over
318 extern char &BranchFolderPassID;
320 /// TailDuplicate - Duplicate blocks with unconditional branches
321 /// into tails of their predecessors.
322 extern char &TailDuplicateID;
324 /// IfConverter - This pass performs machine code if conversion.
325 extern char &IfConverterID;
327 /// MachineBlockPlacement - This pass places basic blocks based on branch
329 extern char &MachineBlockPlacementID;
331 /// MachineBlockPlacementStats - This pass collects statistics about the
332 /// basic block placement using branch probabilities and block frequency
334 extern char &MachineBlockPlacementStatsID;
336 /// Code Placement - This pass optimize code placement and aligns loop
337 /// headers to target specific alignment boundary.
338 extern char &CodePlacementOptID;
340 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
341 /// highly portable strategies.
343 FunctionPass *createGCLoweringPass();
345 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
346 /// in machine code. Must be added very late during code generation, just
347 /// prior to output, and importantly after all CFG transformations (such as
349 extern char &GCMachineCodeAnalysisID;
351 /// Deleter Pass - Releases GC metadata.
353 FunctionPass *createGCInfoDeleter();
355 /// Creates a pass to print GC metadata.
357 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
359 /// MachineCSE - This pass performs global CSE on machine instructions.
360 extern char &MachineCSEID;
362 /// MachineLICM - This pass performs LICM on machine instructions.
363 extern char &MachineLICMID;
365 /// MachineSinking - This pass performs sinking on machine instructions.
366 extern char &MachineSinkingID;
368 /// MachineCopyPropagation - This pass performs copy propagation on
369 /// machine instructions.
370 extern char &MachineCopyPropagationID;
372 /// PeepholeOptimizer - This pass performs peephole optimizations -
373 /// like extension and comparison eliminations.
374 extern char &PeepholeOptimizerID;
376 /// OptimizePHIs - This pass optimizes machine instruction PHIs
377 /// to take advantage of opportunities created during DAG legalization.
378 extern char &OptimizePHIsID;
380 /// StackSlotColoring - This pass performs stack slot coloring.
381 extern char &StackSlotColoringID;
383 /// createStackProtectorPass - This pass adds stack protectors to functions.
385 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
387 /// createMachineVerifierPass - This pass verifies cenerated machine code
388 /// instructions for correctness.
390 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
392 /// createDwarfEHPass - This pass mulches exception handling code into a form
393 /// adapted to code generation. Required if using dwarf exception handling.
394 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
396 /// createSjLjEHPass - This pass adapts exception handling code to use
397 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
399 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
401 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
402 /// slots relative to one another and allocates base registers to access them
403 /// when it is estimated by the target to be out of range of normal frame
404 /// pointer or stack pointer index addressing.
405 extern char &LocalStackSlotAllocationID;
407 /// ExpandISelPseudos - This pass expands pseudo-instructions.
408 extern char &ExpandISelPseudosID;
410 /// createExecutionDependencyFixPass - This pass fixes execution time
411 /// problems with dependent instructions, such as switching execution
412 /// domains to match.
414 /// The pass will examine instructions using and defining registers in RC.
416 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
418 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
419 extern char &UnpackMachineBundlesID;
421 /// FinalizeMachineBundles - This pass finalize machine instruction
422 /// bundles (created earlier, e.g. during pre-RA scheduling).
423 extern char &FinalizeMachineBundlesID;
425 } // End llvm namespace