1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
36 /// Target-Independent Code Generator Pass Configuration Options.
38 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
39 /// to the internals of other CodeGen passes.
40 class TargetPassConfig : public ImmutablePass {
44 bool Initialized; // Flagged after all passes are configured.
46 // Target Pass Options
47 // Targets provide a default setting, user flags override.
51 /// Default setting for -enable-tail-merge on this target.
55 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
59 virtual ~TargetPassConfig();
63 /// Get the right type of TargetMachine for this target.
64 template<typename TMC> TMC &getTM() const {
65 return *static_cast<TMC*>(TM);
68 const TargetLowering *getTargetLowering() const {
69 return TM->getTargetLowering();
72 void setInitialized() { Initialized = true; }
74 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
76 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
78 bool getEnableTailMerge() const { return EnableTailMerge; }
79 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
81 /// Return true if the optimized regalloc pipeline is enabled.
82 bool getOptimizeRegAlloc() const;
84 /// Add common target configurable passes that perform LLVM IR to IR
85 /// transforms following machine independent optimization.
86 virtual void addIRPasses();
88 /// Add common passes that perform LLVM IR to IR transforms in preparation for
89 /// instruction selection.
90 virtual void addISelPrepare();
92 /// addInstSelector - This method should install an instruction selector pass,
93 /// which converts from LLVM code to machine instructions.
94 virtual bool addInstSelector() {
98 /// Add the complete, standard set of LLVM CodeGen passes.
99 /// Fully developed targets will not generally override this.
100 virtual void addMachinePasses();
103 // Helper to verify the analysis is really immutable.
104 void setOpt(bool &Opt, bool Val);
106 /// Methods with trivial inline returns are convenient points in the common
107 /// codegen pass pipeline where targets may insert passes. Methods with
108 /// out-of-line standard implementations are major CodeGen stages called by
109 /// addMachinePasses. Some targets may override major stages when inserting
110 /// passes is insufficient, but maintaining overriden stages is more work.
113 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
114 /// passes (which are run just before instruction selector).
115 virtual bool addPreISel() {
119 /// addMachineSSAOptimization - Add standard passes that optimize machine
120 /// instructions in SSA form.
121 virtual void addMachineSSAOptimization();
123 /// addPreRegAlloc - This method may be implemented by targets that want to
124 /// run passes immediately before register allocation. This should return
125 /// true if -print-machineinstrs should print after these passes.
126 virtual bool addPreRegAlloc() {
130 /// createTargetRegisterAllocator - Create the register allocator pass for
131 /// this target at the current optimization level.
132 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
134 /// addFastRegAlloc - Add the minimum set of target-independent passes that
135 /// are required for fast register allocation.
136 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
138 /// addOptimizedRegAlloc - Add passes related to register allocation.
139 /// LLVMTargetMachine provides standard regalloc passes for most targets.
140 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
142 /// getSchedPass - This method may be implemented by target that want to
143 /// completely override the MachineScheduler pass with a new pass, rather than
144 /// inheriting from ScheduleDAGInstrs.
145 virtual char &getSchedPass() { return NoPassID; }
147 /// addFinalizeRegAlloc - This method may be implemented by targets that want
148 /// to run passes within the regalloc pipeline, immediately after the register
149 /// allocation pass itself. These passes run as soon as virtual regisiters
150 /// have been rewritten to physical registers but before and other postRA
151 /// optimization happens. Targets that have marked instructions for bundling
152 /// must have finalized those bundles by the time these passes have run,
153 /// because subsequent passes are not guaranteed to be bundle-aware.
154 virtual bool addFinalizeRegAlloc() {
158 /// addPostRegAlloc - This method may be implemented by targets that want to
159 /// run passes after register allocation pass pipeline but before
160 /// prolog-epilog insertion. This should return true if -print-machineinstrs
161 /// should print after these passes.
162 virtual bool addPostRegAlloc() {
166 /// Add passes that optimize machine instructions after register allocation.
167 virtual void addMachineLateOptimization();
169 /// addPreSched2 - This method may be implemented by targets that want to
170 /// run passes after prolog-epilog insertion and before the second instruction
171 /// scheduling pass. This should return true if -print-machineinstrs should
172 /// print after these passes.
173 virtual bool addPreSched2() {
177 /// Add standard basic block placement passes.
178 virtual void addBlockPlacement();
180 /// addPreEmitPass - This pass may be implemented by targets that want to run
181 /// passes immediately before machine code is emitted. This should return
182 /// true if -print-machineinstrs should print out the code after the passes.
183 virtual bool addPreEmitPass() {
187 /// Utilities for targets to add passes to the pass manager.
190 /// Add a target-independent CodeGen pass at this point in the pipeline.
191 void addPass(char &ID);
193 /// addMachinePasses helper to create the target-selected or overriden
195 FunctionPass *createRegAllocPass(bool Optimized);
197 /// printNoVerify - Add a pass to dump the machine function, if debugging is
200 void printNoVerify(const char *Banner) const;
202 /// printAndVerify - Add a pass to dump then verify the machine function, if
203 /// those steps are enabled.
205 void printAndVerify(const char *Banner) const;
209 /// List of target independent CodeGen pass IDs.
211 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
212 /// work well with unreachable basic blocks (what live ranges make sense for a
213 /// block that cannot be reached?). As such, a code generator should either
214 /// not instruction select unreachable blocks, or run this pass as its
215 /// last LLVM modifying pass to clean up blocks that are not reachable from
217 FunctionPass *createUnreachableBlockEliminationPass();
219 /// MachineFunctionPrinter pass - This pass prints out the machine function to
220 /// the given stream as a debugging tool.
221 MachineFunctionPass *
222 createMachineFunctionPrinterPass(raw_ostream &OS,
223 const std::string &Banner ="");
225 /// MachineLoopInfo - This pass is a loop analysis pass.
226 extern char &MachineLoopInfoID;
228 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
229 extern char &MachineLoopRangesID;
231 /// MachineDominators - This pass is a machine dominators analysis pass.
232 extern char &MachineDominatorsID;
234 /// EdgeBundles analysis - Bundle machine CFG edges.
235 extern char &EdgeBundlesID;
237 /// LiveVariables pass - This pass computes the set of blocks in which each
238 /// variable is life and sets machine operand kill flags.
239 extern char &LiveVariablesID;
241 /// PHIElimination - This pass eliminates machine instruction PHI nodes
242 /// by inserting copy instructions. This destroys SSA information, but is the
243 /// desired input for some register allocators. This pass is "required" by
244 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
245 extern char &PHIEliminationID;
247 /// StrongPHIElimination - This pass eliminates machine instruction PHI
248 /// nodes by inserting copy instructions. This destroys SSA information, but
249 /// is the desired input for some register allocators. This pass is
250 /// "required" by these register allocator like this:
251 /// AU.addRequiredID(PHIEliminationID);
252 /// This pass is still in development
253 extern char &StrongPHIEliminationID;
255 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
256 extern char &LiveStacksID;
258 /// TwoAddressInstruction - This pass reduces two-address instructions to
259 /// use two operands. This destroys SSA information but it is desired by
260 /// register allocators.
261 extern char &TwoAddressInstructionPassID;
263 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
264 extern char &ProcessImplicitDefsID;
266 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
267 extern char &RegisterCoalescerID;
269 /// MachineScheduler - This pass schedules machine instructions.
270 extern char &MachineSchedulerID;
272 /// SpillPlacement analysis. Suggest optimal placement of spill code between
274 extern char &SpillPlacementID;
276 /// UnreachableMachineBlockElimination - This pass removes unreachable
277 /// machine basic blocks.
278 extern char &UnreachableMachineBlockElimID;
280 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
281 extern char &DeadMachineInstructionElimID;
283 /// FastRegisterAllocation Pass - This pass register allocates as fast as
284 /// possible. It is best suited for debug code where live ranges are short.
286 FunctionPass *createFastRegisterAllocator();
288 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
289 /// register allocator using the basic regalloc framework.
291 FunctionPass *createBasicRegisterAllocator();
293 /// Greedy register allocation pass - This pass implements a global register
294 /// allocator for optimized builds.
296 FunctionPass *createGreedyRegisterAllocator();
298 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
299 /// Quadratic Prograaming (PBQP) based register allocator.
301 FunctionPass *createDefaultPBQPRegisterAllocator();
303 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
304 /// and eliminates abstract frame references.
305 extern char &PrologEpilogCodeInserterID;
307 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
308 /// register allocation.
309 extern char &ExpandPostRAPseudosID;
311 /// createPostRAScheduler - This pass performs post register allocation
313 extern char &PostRASchedulerID;
315 /// BranchFolding - This pass performs machine code CFG based
316 /// optimizations to delete branches to branches, eliminate branches to
317 /// successor blocks (creating fall throughs), and eliminating branches over
319 extern char &BranchFolderPassID;
321 /// TailDuplicate - Duplicate blocks with unconditional branches
322 /// into tails of their predecessors.
323 extern char &TailDuplicateID;
325 /// IfConverter - This pass performs machine code if conversion.
326 extern char &IfConverterID;
328 /// MachineBlockPlacement - This pass places basic blocks based on branch
330 extern char &MachineBlockPlacementID;
332 /// MachineBlockPlacementStats - This pass collects statistics about the
333 /// basic block placement using branch probabilities and block frequency
335 extern char &MachineBlockPlacementStatsID;
337 /// Code Placement - This pass optimize code placement and aligns loop
338 /// headers to target specific alignment boundary.
339 extern char &CodePlacementOptID;
341 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
342 /// highly portable strategies.
344 FunctionPass *createGCLoweringPass();
346 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
347 /// in machine code. Must be added very late during code generation, just
348 /// prior to output, and importantly after all CFG transformations (such as
350 extern char &GCMachineCodeAnalysisID;
352 /// Deleter Pass - Releases GC metadata.
354 FunctionPass *createGCInfoDeleter();
356 /// Creates a pass to print GC metadata.
358 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
360 /// MachineCSE - This pass performs global CSE on machine instructions.
361 extern char &MachineCSEID;
363 /// MachineLICM - This pass performs LICM on machine instructions.
364 extern char &MachineLICMID;
366 /// MachineSinking - This pass performs sinking on machine instructions.
367 extern char &MachineSinkingID;
369 /// MachineCopyPropagation - This pass performs copy propagation on
370 /// machine instructions.
371 extern char &MachineCopyPropagationID;
373 /// PeepholeOptimizer - This pass performs peephole optimizations -
374 /// like extension and comparison eliminations.
375 extern char &PeepholeOptimizerID;
377 /// OptimizePHIs - This pass optimizes machine instruction PHIs
378 /// to take advantage of opportunities created during DAG legalization.
379 extern char &OptimizePHIsID;
381 /// StackSlotColoring - This pass performs stack slot coloring.
382 extern char &StackSlotColoringID;
384 /// createStackProtectorPass - This pass adds stack protectors to functions.
386 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
388 /// createMachineVerifierPass - This pass verifies cenerated machine code
389 /// instructions for correctness.
391 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
393 /// createDwarfEHPass - This pass mulches exception handling code into a form
394 /// adapted to code generation. Required if using dwarf exception handling.
395 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
397 /// createSjLjEHPass - This pass adapts exception handling code to use
398 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
400 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
402 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
403 /// slots relative to one another and allocates base registers to access them
404 /// when it is estimated by the target to be out of range of normal frame
405 /// pointer or stack pointer index addressing.
406 extern char &LocalStackSlotAllocationID;
408 /// ExpandISelPseudos - This pass expands pseudo-instructions.
409 extern char &ExpandISelPseudosID;
411 /// createExecutionDependencyFixPass - This pass fixes execution time
412 /// problems with dependent instructions, such as switching execution
413 /// domains to match.
415 /// The pass will examine instructions using and defining registers in RC.
417 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
419 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
420 extern char &UnpackMachineBundlesID;
422 /// FinalizeMachineBundles - This pass finalize machine instruction
423 /// bundles (created earlier, e.g. during pre-RA scheduling).
424 extern char &FinalizeMachineBundlesID;
426 } // End llvm namespace