1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
46 PassConfigImpl *Impl; // Internal data structures
47 bool Initialized; // Flagged after all passes are configured.
49 // Target Pass Options
50 // Targets provide a default setting, user flags override.
54 /// Default setting for -enable-tail-merge on this target.
58 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
62 virtual ~TargetPassConfig();
66 /// Get the right type of TargetMachine for this target.
67 template<typename TMC> TMC &getTM() const {
68 return *static_cast<TMC*>(TM);
71 const TargetLowering *getTargetLowering() const {
72 return TM->getTargetLowering();
76 void setInitialized() { Initialized = true; }
78 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
80 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
82 bool getEnableTailMerge() const { return EnableTailMerge; }
83 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
85 /// Allow the target to override a specific pass without overriding the pass
86 /// pipeline. When passes are added to the standard pipeline at the
87 /// point where StadardID is expected, add TargetID in its place.
88 void substitutePass(char &StandardID, char &TargetID);
90 /// Allow the target to disable a specific standard pass.
91 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
93 /// Return the pass ssubtituted for StandardID by the target.
94 /// If no substitution exists, return StandardID.
95 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
97 /// Return true if the optimized regalloc pipeline is enabled.
98 bool getOptimizeRegAlloc() const;
100 /// Add common target configurable passes that perform LLVM IR to IR
101 /// transforms following machine independent optimization.
102 virtual void addIRPasses();
104 /// Add common passes that perform LLVM IR to IR transforms in preparation for
105 /// instruction selection.
106 virtual void addISelPrepare();
108 /// addInstSelector - This method should install an instruction selector pass,
109 /// which converts from LLVM code to machine instructions.
110 virtual bool addInstSelector() {
114 /// Add the complete, standard set of LLVM CodeGen passes.
115 /// Fully developed targets will not generally override this.
116 virtual void addMachinePasses();
119 // Helper to verify the analysis is really immutable.
120 void setOpt(bool &Opt, bool Val);
122 /// Methods with trivial inline returns are convenient points in the common
123 /// codegen pass pipeline where targets may insert passes. Methods with
124 /// out-of-line standard implementations are major CodeGen stages called by
125 /// addMachinePasses. Some targets may override major stages when inserting
126 /// passes is insufficient, but maintaining overriden stages is more work.
129 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
130 /// passes (which are run just before instruction selector).
131 virtual bool addPreISel() {
135 /// addMachineSSAOptimization - Add standard passes that optimize machine
136 /// instructions in SSA form.
137 virtual void addMachineSSAOptimization();
139 /// addPreRegAlloc - This method may be implemented by targets that want to
140 /// run passes immediately before register allocation. This should return
141 /// true if -print-machineinstrs should print after these passes.
142 virtual bool addPreRegAlloc() {
146 /// createTargetRegisterAllocator - Create the register allocator pass for
147 /// this target at the current optimization level.
148 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
150 /// addFastRegAlloc - Add the minimum set of target-independent passes that
151 /// are required for fast register allocation.
152 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
154 /// addOptimizedRegAlloc - Add passes related to register allocation.
155 /// LLVMTargetMachine provides standard regalloc passes for most targets.
156 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
158 /// getSchedPass - This method may be implemented by target that want to
159 /// completely override the MachineScheduler pass with a new pass, rather than
160 /// inheriting from ScheduleDAGInstrs.
161 virtual char &getSchedPass() { return NoPassID; }
163 /// addFinalizeRegAlloc - This method may be implemented by targets that want
164 /// to run passes within the regalloc pipeline, immediately after the register
165 /// allocation pass itself. These passes run as soon as virtual regisiters
166 /// have been rewritten to physical registers but before and other postRA
167 /// optimization happens. Targets that have marked instructions for bundling
168 /// must have finalized those bundles by the time these passes have run,
169 /// because subsequent passes are not guaranteed to be bundle-aware.
170 virtual bool addFinalizeRegAlloc() {
174 /// addPostRegAlloc - This method may be implemented by targets that want to
175 /// run passes after register allocation pass pipeline but before
176 /// prolog-epilog insertion. This should return true if -print-machineinstrs
177 /// should print after these passes.
178 virtual bool addPostRegAlloc() {
182 /// Add passes that optimize machine instructions after register allocation.
183 virtual void addMachineLateOptimization();
185 /// addPreSched2 - This method may be implemented by targets that want to
186 /// run passes after prolog-epilog insertion and before the second instruction
187 /// scheduling pass. This should return true if -print-machineinstrs should
188 /// print after these passes.
189 virtual bool addPreSched2() {
193 /// Add standard basic block placement passes.
194 virtual void addBlockPlacement();
196 /// addPreEmitPass - This pass may be implemented by targets that want to run
197 /// passes immediately before machine code is emitted. This should return
198 /// true if -print-machineinstrs should print out the code after the passes.
199 virtual bool addPreEmitPass() {
203 /// Utilities for targets to add passes to the pass manager.
206 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
207 /// Return the pass that was added, or NoPassID.
208 AnalysisID addPass(char &ID);
210 /// addMachinePasses helper to create the target-selected or overriden
212 FunctionPass *createRegAllocPass(bool Optimized);
214 /// printNoVerify - Add a pass to dump the machine function, if debugging is
217 void printNoVerify(const char *Banner) const;
219 /// printAndVerify - Add a pass to dump then verify the machine function, if
220 /// those steps are enabled.
222 void printAndVerify(const char *Banner) const;
226 /// List of target independent CodeGen pass IDs.
228 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
229 /// work well with unreachable basic blocks (what live ranges make sense for a
230 /// block that cannot be reached?). As such, a code generator should either
231 /// not instruction select unreachable blocks, or run this pass as its
232 /// last LLVM modifying pass to clean up blocks that are not reachable from
234 FunctionPass *createUnreachableBlockEliminationPass();
236 /// MachineFunctionPrinter pass - This pass prints out the machine function to
237 /// the given stream as a debugging tool.
238 MachineFunctionPass *
239 createMachineFunctionPrinterPass(raw_ostream &OS,
240 const std::string &Banner ="");
242 /// MachineLoopInfo - This pass is a loop analysis pass.
243 extern char &MachineLoopInfoID;
245 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
246 extern char &MachineLoopRangesID;
248 /// MachineDominators - This pass is a machine dominators analysis pass.
249 extern char &MachineDominatorsID;
251 /// EdgeBundles analysis - Bundle machine CFG edges.
252 extern char &EdgeBundlesID;
254 /// LiveVariables pass - This pass computes the set of blocks in which each
255 /// variable is life and sets machine operand kill flags.
256 extern char &LiveVariablesID;
258 /// PHIElimination - This pass eliminates machine instruction PHI nodes
259 /// by inserting copy instructions. This destroys SSA information, but is the
260 /// desired input for some register allocators. This pass is "required" by
261 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
262 extern char &PHIEliminationID;
264 /// StrongPHIElimination - This pass eliminates machine instruction PHI
265 /// nodes by inserting copy instructions. This destroys SSA information, but
266 /// is the desired input for some register allocators. This pass is
267 /// "required" by these register allocator like this:
268 /// AU.addRequiredID(PHIEliminationID);
269 /// This pass is still in development
270 extern char &StrongPHIEliminationID;
272 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
273 extern char &LiveStacksID;
275 /// TwoAddressInstruction - This pass reduces two-address instructions to
276 /// use two operands. This destroys SSA information but it is desired by
277 /// register allocators.
278 extern char &TwoAddressInstructionPassID;
280 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
281 extern char &ProcessImplicitDefsID;
283 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
284 extern char &RegisterCoalescerID;
286 /// MachineScheduler - This pass schedules machine instructions.
287 extern char &MachineSchedulerID;
289 /// SpillPlacement analysis. Suggest optimal placement of spill code between
291 extern char &SpillPlacementID;
293 /// UnreachableMachineBlockElimination - This pass removes unreachable
294 /// machine basic blocks.
295 extern char &UnreachableMachineBlockElimID;
297 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
298 extern char &DeadMachineInstructionElimID;
300 /// FastRegisterAllocation Pass - This pass register allocates as fast as
301 /// possible. It is best suited for debug code where live ranges are short.
303 FunctionPass *createFastRegisterAllocator();
305 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
306 /// register allocator using the basic regalloc framework.
308 FunctionPass *createBasicRegisterAllocator();
310 /// Greedy register allocation pass - This pass implements a global register
311 /// allocator for optimized builds.
313 FunctionPass *createGreedyRegisterAllocator();
315 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
316 /// Quadratic Prograaming (PBQP) based register allocator.
318 FunctionPass *createDefaultPBQPRegisterAllocator();
320 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
321 /// and eliminates abstract frame references.
322 extern char &PrologEpilogCodeInserterID;
324 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
325 /// register allocation.
326 extern char &ExpandPostRAPseudosID;
328 /// createPostRAScheduler - This pass performs post register allocation
330 extern char &PostRASchedulerID;
332 /// BranchFolding - This pass performs machine code CFG based
333 /// optimizations to delete branches to branches, eliminate branches to
334 /// successor blocks (creating fall throughs), and eliminating branches over
336 extern char &BranchFolderPassID;
338 /// TailDuplicate - Duplicate blocks with unconditional branches
339 /// into tails of their predecessors.
340 extern char &TailDuplicateID;
342 /// IfConverter - This pass performs machine code if conversion.
343 extern char &IfConverterID;
345 /// MachineBlockPlacement - This pass places basic blocks based on branch
347 extern char &MachineBlockPlacementID;
349 /// MachineBlockPlacementStats - This pass collects statistics about the
350 /// basic block placement using branch probabilities and block frequency
352 extern char &MachineBlockPlacementStatsID;
354 /// Code Placement - This pass optimize code placement and aligns loop
355 /// headers to target specific alignment boundary.
356 extern char &CodePlacementOptID;
358 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
359 /// highly portable strategies.
361 FunctionPass *createGCLoweringPass();
363 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
364 /// in machine code. Must be added very late during code generation, just
365 /// prior to output, and importantly after all CFG transformations (such as
367 extern char &GCMachineCodeAnalysisID;
369 /// Deleter Pass - Releases GC metadata.
371 FunctionPass *createGCInfoDeleter();
373 /// Creates a pass to print GC metadata.
375 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
377 /// MachineCSE - This pass performs global CSE on machine instructions.
378 extern char &MachineCSEID;
380 /// MachineLICM - This pass performs LICM on machine instructions.
381 extern char &MachineLICMID;
383 /// MachineSinking - This pass performs sinking on machine instructions.
384 extern char &MachineSinkingID;
386 /// MachineCopyPropagation - This pass performs copy propagation on
387 /// machine instructions.
388 extern char &MachineCopyPropagationID;
390 /// PeepholeOptimizer - This pass performs peephole optimizations -
391 /// like extension and comparison eliminations.
392 extern char &PeepholeOptimizerID;
394 /// OptimizePHIs - This pass optimizes machine instruction PHIs
395 /// to take advantage of opportunities created during DAG legalization.
396 extern char &OptimizePHIsID;
398 /// StackSlotColoring - This pass performs stack slot coloring.
399 extern char &StackSlotColoringID;
401 /// createStackProtectorPass - This pass adds stack protectors to functions.
403 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
405 /// createMachineVerifierPass - This pass verifies cenerated machine code
406 /// instructions for correctness.
408 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
410 /// createDwarfEHPass - This pass mulches exception handling code into a form
411 /// adapted to code generation. Required if using dwarf exception handling.
412 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
414 /// createSjLjEHPass - This pass adapts exception handling code to use
415 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
417 FunctionPass *createSjLjEHPass(const TargetLowering *tli);
419 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
420 /// slots relative to one another and allocates base registers to access them
421 /// when it is estimated by the target to be out of range of normal frame
422 /// pointer or stack pointer index addressing.
423 extern char &LocalStackSlotAllocationID;
425 /// ExpandISelPseudos - This pass expands pseudo-instructions.
426 extern char &ExpandISelPseudosID;
428 /// createExecutionDependencyFixPass - This pass fixes execution time
429 /// problems with dependent instructions, such as switching execution
430 /// domains to match.
432 /// The pass will examine instructions using and defining registers in RC.
434 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
436 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
437 extern char &UnpackMachineBundlesID;
439 /// FinalizeMachineBundles - This pass finalize machine instruction
440 /// bundles (created earlier, e.g. during pre-RA scheduling).
441 extern char &FinalizeMachineBundlesID;
443 } // End llvm namespace