1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
27 class PassManagerBase;
29 class TargetRegisterClass;
35 extern char &NoPassID; // Allow targets to choose not to run a pass.
39 /// Target-Independent Code Generator Pass Configuration Options.
41 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
42 /// to the internals of other CodeGen passes.
43 class TargetPassConfig : public ImmutablePass {
45 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
46 /// are unregistered pass IDs. They are only useful for use with
47 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
50 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
51 /// during codegen, on SSA form.
52 static char EarlyTailDuplicateID;
54 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
55 /// optimization after regalloc.
56 static char PostRAMachineLICMID;
63 PassConfigImpl *Impl; // Internal data structures
64 bool Initialized; // Flagged after all passes are configured.
66 // Target Pass Options
67 // Targets provide a default setting, user flags override.
71 /// Default setting for -enable-tail-merge on this target.
75 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
79 virtual ~TargetPassConfig();
83 /// Get the right type of TargetMachine for this target.
84 template<typename TMC> TMC &getTM() const {
85 return *static_cast<TMC*>(TM);
88 const TargetLowering *getTargetLowering() const {
89 return TM->getTargetLowering();
93 void setInitialized() { Initialized = true; }
95 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
97 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
99 bool getEnableTailMerge() const { return EnableTailMerge; }
100 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
102 /// Allow the target to override a specific pass without overriding the pass
103 /// pipeline. When passes are added to the standard pipeline at the
104 /// point where StadardID is expected, add TargetID in its place.
105 void substitutePass(char &StandardID, char &TargetID);
107 /// Insert InsertedPassID pass after TargetPassID pass.
108 void insertPass(const char &TargetPassID, const char &InsertedPassID);
110 /// Allow the target to enable a specific standard pass by default.
111 void enablePass(char &ID) { substitutePass(ID, ID); }
113 /// Allow the target to disable a specific standard pass by default.
114 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
116 /// Return the pass ssubtituted for StandardID by the target.
117 /// If no substitution exists, return StandardID.
118 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
120 /// Return true if the optimized regalloc pipeline is enabled.
121 bool getOptimizeRegAlloc() const;
123 /// Add common target configurable passes that perform LLVM IR to IR
124 /// transforms following machine independent optimization.
125 virtual void addIRPasses();
127 /// Add passes to lower exception handling for the code generator.
128 void addPassesToHandleExceptions();
130 /// Add common passes that perform LLVM IR to IR transforms in preparation for
131 /// instruction selection.
132 virtual void addISelPrepare();
134 /// addInstSelector - This method should install an instruction selector pass,
135 /// which converts from LLVM code to machine instructions.
136 virtual bool addInstSelector() {
140 /// Add the complete, standard set of LLVM CodeGen passes.
141 /// Fully developed targets will not generally override this.
142 virtual void addMachinePasses();
145 // Helper to verify the analysis is really immutable.
146 void setOpt(bool &Opt, bool Val);
148 /// Methods with trivial inline returns are convenient points in the common
149 /// codegen pass pipeline where targets may insert passes. Methods with
150 /// out-of-line standard implementations are major CodeGen stages called by
151 /// addMachinePasses. Some targets may override major stages when inserting
152 /// passes is insufficient, but maintaining overriden stages is more work.
155 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
156 /// passes (which are run just before instruction selector).
157 virtual bool addPreISel() {
161 /// addMachineSSAOptimization - Add standard passes that optimize machine
162 /// instructions in SSA form.
163 virtual void addMachineSSAOptimization();
165 /// addPreRegAlloc - This method may be implemented by targets that want to
166 /// run passes immediately before register allocation. This should return
167 /// true if -print-machineinstrs should print after these passes.
168 virtual bool addPreRegAlloc() {
172 /// createTargetRegisterAllocator - Create the register allocator pass for
173 /// this target at the current optimization level.
174 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
176 /// addFastRegAlloc - Add the minimum set of target-independent passes that
177 /// are required for fast register allocation.
178 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
180 /// addOptimizedRegAlloc - Add passes related to register allocation.
181 /// LLVMTargetMachine provides standard regalloc passes for most targets.
182 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
184 /// addPreRewrite - Add passes to the optimized register allocation pipeline
185 /// after register allocation is complete, but before virtual registers are
186 /// rewritten to physical registers.
188 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
189 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
190 /// When these passes run, VirtRegMap contains legal physreg assignments for
191 /// all virtual registers.
192 virtual bool addPreRewrite() {
196 /// addFinalizeRegAlloc - This method may be implemented by targets that want
197 /// to run passes within the regalloc pipeline, immediately after the register
198 /// allocation pass itself. These passes run as soon as virtual regisiters
199 /// have been rewritten to physical registers but before and other postRA
200 /// optimization happens. Targets that have marked instructions for bundling
201 /// must have finalized those bundles by the time these passes have run,
202 /// because subsequent passes are not guaranteed to be bundle-aware.
203 virtual bool addFinalizeRegAlloc() {
207 /// addPostRegAlloc - This method may be implemented by targets that want to
208 /// run passes after register allocation pass pipeline but before
209 /// prolog-epilog insertion. This should return true if -print-machineinstrs
210 /// should print after these passes.
211 virtual bool addPostRegAlloc() {
215 /// Add passes that optimize machine instructions after register allocation.
216 virtual void addMachineLateOptimization();
218 /// addPreSched2 - This method may be implemented by targets that want to
219 /// run passes after prolog-epilog insertion and before the second instruction
220 /// scheduling pass. This should return true if -print-machineinstrs should
221 /// print after these passes.
222 virtual bool addPreSched2() {
226 /// Add standard basic block placement passes.
227 virtual void addBlockPlacement();
229 /// addPreEmitPass - This pass may be implemented by targets that want to run
230 /// passes immediately before machine code is emitted. This should return
231 /// true if -print-machineinstrs should print out the code after the passes.
232 virtual bool addPreEmitPass() {
236 /// Utilities for targets to add passes to the pass manager.
239 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
240 /// Return the pass that was added, or NoPassID.
241 AnalysisID addPass(char &ID);
243 /// Add a pass to the PassManager.
244 void addPass(Pass *P);
246 /// addMachinePasses helper to create the target-selected or overriden
248 FunctionPass *createRegAllocPass(bool Optimized);
250 /// printAndVerify - Add a pass to dump then verify the machine function, if
251 /// those steps are enabled.
253 void printAndVerify(const char *Banner);
257 /// List of target independent CodeGen pass IDs.
259 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
260 /// work well with unreachable basic blocks (what live ranges make sense for a
261 /// block that cannot be reached?). As such, a code generator should either
262 /// not instruction select unreachable blocks, or run this pass as its
263 /// last LLVM modifying pass to clean up blocks that are not reachable from
265 FunctionPass *createUnreachableBlockEliminationPass();
267 /// MachineFunctionPrinter pass - This pass prints out the machine function to
268 /// the given stream as a debugging tool.
269 MachineFunctionPass *
270 createMachineFunctionPrinterPass(raw_ostream &OS,
271 const std::string &Banner ="");
273 /// MachineLoopInfo - This pass is a loop analysis pass.
274 extern char &MachineLoopInfoID;
276 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
277 extern char &MachineLoopRangesID;
279 /// MachineDominators - This pass is a machine dominators analysis pass.
280 extern char &MachineDominatorsID;
282 /// EdgeBundles analysis - Bundle machine CFG edges.
283 extern char &EdgeBundlesID;
285 /// LiveVariables pass - This pass computes the set of blocks in which each
286 /// variable is life and sets machine operand kill flags.
287 extern char &LiveVariablesID;
289 /// PHIElimination - This pass eliminates machine instruction PHI nodes
290 /// by inserting copy instructions. This destroys SSA information, but is the
291 /// desired input for some register allocators. This pass is "required" by
292 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
293 extern char &PHIEliminationID;
295 /// StrongPHIElimination - This pass eliminates machine instruction PHI
296 /// nodes by inserting copy instructions. This destroys SSA information, but
297 /// is the desired input for some register allocators. This pass is
298 /// "required" by these register allocator like this:
299 /// AU.addRequiredID(PHIEliminationID);
300 /// This pass is still in development
301 extern char &StrongPHIEliminationID;
303 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
304 extern char &LiveStacksID;
306 /// TwoAddressInstruction - This pass reduces two-address instructions to
307 /// use two operands. This destroys SSA information but it is desired by
308 /// register allocators.
309 extern char &TwoAddressInstructionPassID;
311 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
312 extern char &ProcessImplicitDefsID;
314 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
315 extern char &RegisterCoalescerID;
317 /// MachineScheduler - This pass schedules machine instructions.
318 extern char &MachineSchedulerID;
320 /// SpillPlacement analysis. Suggest optimal placement of spill code between
322 extern char &SpillPlacementID;
324 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
325 /// assigned in VirtRegMap.
326 extern char &VirtRegRewriterID;
328 /// UnreachableMachineBlockElimination - This pass removes unreachable
329 /// machine basic blocks.
330 extern char &UnreachableMachineBlockElimID;
332 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
333 extern char &DeadMachineInstructionElimID;
335 /// FastRegisterAllocation Pass - This pass register allocates as fast as
336 /// possible. It is best suited for debug code where live ranges are short.
338 FunctionPass *createFastRegisterAllocator();
340 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
341 /// register allocator using the basic regalloc framework.
343 FunctionPass *createBasicRegisterAllocator();
345 /// Greedy register allocation pass - This pass implements a global register
346 /// allocator for optimized builds.
348 FunctionPass *createGreedyRegisterAllocator();
350 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
351 /// Quadratic Prograaming (PBQP) based register allocator.
353 FunctionPass *createDefaultPBQPRegisterAllocator();
355 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
356 /// and eliminates abstract frame references.
357 extern char &PrologEpilogCodeInserterID;
359 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
360 /// register allocation.
361 extern char &ExpandPostRAPseudosID;
363 /// createPostRAScheduler - This pass performs post register allocation
365 extern char &PostRASchedulerID;
367 /// BranchFolding - This pass performs machine code CFG based
368 /// optimizations to delete branches to branches, eliminate branches to
369 /// successor blocks (creating fall throughs), and eliminating branches over
371 extern char &BranchFolderPassID;
373 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
374 extern char &MachineFunctionPrinterPassID;
376 /// TailDuplicate - Duplicate blocks with unconditional branches
377 /// into tails of their predecessors.
378 extern char &TailDuplicateID;
380 /// IfConverter - This pass performs machine code if conversion.
381 extern char &IfConverterID;
383 /// MachineBlockPlacement - This pass places basic blocks based on branch
385 extern char &MachineBlockPlacementID;
387 /// MachineBlockPlacementStats - This pass collects statistics about the
388 /// basic block placement using branch probabilities and block frequency
390 extern char &MachineBlockPlacementStatsID;
392 /// Code Placement - This pass optimize code placement and aligns loop
393 /// headers to target specific alignment boundary.
394 extern char &CodePlacementOptID;
396 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
397 /// highly portable strategies.
399 FunctionPass *createGCLoweringPass();
401 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
402 /// in machine code. Must be added very late during code generation, just
403 /// prior to output, and importantly after all CFG transformations (such as
405 extern char &GCMachineCodeAnalysisID;
407 /// Deleter Pass - Releases GC metadata.
409 FunctionPass *createGCInfoDeleter();
411 /// Creates a pass to print GC metadata.
413 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
415 /// MachineCSE - This pass performs global CSE on machine instructions.
416 extern char &MachineCSEID;
418 /// MachineLICM - This pass performs LICM on machine instructions.
419 extern char &MachineLICMID;
421 /// MachineSinking - This pass performs sinking on machine instructions.
422 extern char &MachineSinkingID;
424 /// MachineCopyPropagation - This pass performs copy propagation on
425 /// machine instructions.
426 extern char &MachineCopyPropagationID;
428 /// PeepholeOptimizer - This pass performs peephole optimizations -
429 /// like extension and comparison eliminations.
430 extern char &PeepholeOptimizerID;
432 /// OptimizePHIs - This pass optimizes machine instruction PHIs
433 /// to take advantage of opportunities created during DAG legalization.
434 extern char &OptimizePHIsID;
436 /// StackSlotColoring - This pass performs stack slot coloring.
437 extern char &StackSlotColoringID;
439 /// createStackProtectorPass - This pass adds stack protectors to functions.
441 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
443 /// createMachineVerifierPass - This pass verifies cenerated machine code
444 /// instructions for correctness.
446 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
448 /// createDwarfEHPass - This pass mulches exception handling code into a form
449 /// adapted to code generation. Required if using dwarf exception handling.
450 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
452 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
453 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
455 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
457 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
458 /// slots relative to one another and allocates base registers to access them
459 /// when it is estimated by the target to be out of range of normal frame
460 /// pointer or stack pointer index addressing.
461 extern char &LocalStackSlotAllocationID;
463 /// ExpandISelPseudos - This pass expands pseudo-instructions.
464 extern char &ExpandISelPseudosID;
466 /// createExecutionDependencyFixPass - This pass fixes execution time
467 /// problems with dependent instructions, such as switching execution
468 /// domains to match.
470 /// The pass will examine instructions using and defining registers in RC.
472 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
474 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
475 extern char &UnpackMachineBundlesID;
477 /// FinalizeMachineBundles - This pass finalize machine instruction
478 /// bundles (created earlier, e.g. during pre-RA scheduling).
479 extern char &FinalizeMachineBundlesID;
481 } // End llvm namespace