1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class TargetRegisterClass;
34 extern char &NoPassID; // Allow targets to choose not to run a pass.
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
60 PassConfigImpl *Impl; // Internal data structures
61 bool Initialized; // Flagged after all passes are configured.
63 // Target Pass Options
64 // Targets provide a default setting, user flags override.
68 /// Default setting for -enable-tail-merge on this target.
72 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
76 virtual ~TargetPassConfig();
80 /// Get the right type of TargetMachine for this target.
81 template<typename TMC> TMC &getTM() const {
82 return *static_cast<TMC*>(TM);
85 const TargetLowering *getTargetLowering() const {
86 return TM->getTargetLowering();
90 void setInitialized() { Initialized = true; }
92 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
94 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
96 bool getEnableTailMerge() const { return EnableTailMerge; }
97 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
99 /// Allow the target to override a specific pass without overriding the pass
100 /// pipeline. When passes are added to the standard pipeline at the
101 /// point where StadardID is expected, add TargetID in its place.
102 void substitutePass(char &StandardID, char &TargetID);
104 /// Insert InsertedPassID pass after TargetPassID pass.
105 void insertPass(const char &TargetPassID, const char &InsertedPassID);
107 /// Allow the target to enable a specific standard pass by default.
108 void enablePass(char &ID) { substitutePass(ID, ID); }
110 /// Allow the target to disable a specific standard pass by default.
111 void disablePass(char &ID) { substitutePass(ID, NoPassID); }
113 /// Return the pass ssubtituted for StandardID by the target.
114 /// If no substitution exists, return StandardID.
115 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
117 /// Return true if the optimized regalloc pipeline is enabled.
118 bool getOptimizeRegAlloc() const;
120 /// Add common target configurable passes that perform LLVM IR to IR
121 /// transforms following machine independent optimization.
122 virtual void addIRPasses();
124 /// Add common passes that perform LLVM IR to IR transforms in preparation for
125 /// instruction selection.
126 virtual void addISelPrepare();
128 /// addInstSelector - This method should install an instruction selector pass,
129 /// which converts from LLVM code to machine instructions.
130 virtual bool addInstSelector() {
134 /// Add the complete, standard set of LLVM CodeGen passes.
135 /// Fully developed targets will not generally override this.
136 virtual void addMachinePasses();
139 // Helper to verify the analysis is really immutable.
140 void setOpt(bool &Opt, bool Val);
142 /// Methods with trivial inline returns are convenient points in the common
143 /// codegen pass pipeline where targets may insert passes. Methods with
144 /// out-of-line standard implementations are major CodeGen stages called by
145 /// addMachinePasses. Some targets may override major stages when inserting
146 /// passes is insufficient, but maintaining overriden stages is more work.
149 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
150 /// passes (which are run just before instruction selector).
151 virtual bool addPreISel() {
155 /// addMachineSSAOptimization - Add standard passes that optimize machine
156 /// instructions in SSA form.
157 virtual void addMachineSSAOptimization();
159 /// addPreRegAlloc - This method may be implemented by targets that want to
160 /// run passes immediately before register allocation. This should return
161 /// true if -print-machineinstrs should print after these passes.
162 virtual bool addPreRegAlloc() {
166 /// createTargetRegisterAllocator - Create the register allocator pass for
167 /// this target at the current optimization level.
168 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
170 /// addFastRegAlloc - Add the minimum set of target-independent passes that
171 /// are required for fast register allocation.
172 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
174 /// addOptimizedRegAlloc - Add passes related to register allocation.
175 /// LLVMTargetMachine provides standard regalloc passes for most targets.
176 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
178 /// addFinalizeRegAlloc - This method may be implemented by targets that want
179 /// to run passes within the regalloc pipeline, immediately after the register
180 /// allocation pass itself. These passes run as soon as virtual regisiters
181 /// have been rewritten to physical registers but before and other postRA
182 /// optimization happens. Targets that have marked instructions for bundling
183 /// must have finalized those bundles by the time these passes have run,
184 /// because subsequent passes are not guaranteed to be bundle-aware.
185 virtual bool addFinalizeRegAlloc() {
189 /// addPostRegAlloc - This method may be implemented by targets that want to
190 /// run passes after register allocation pass pipeline but before
191 /// prolog-epilog insertion. This should return true if -print-machineinstrs
192 /// should print after these passes.
193 virtual bool addPostRegAlloc() {
197 /// Add passes that optimize machine instructions after register allocation.
198 virtual void addMachineLateOptimization();
200 /// addPreSched2 - This method may be implemented by targets that want to
201 /// run passes after prolog-epilog insertion and before the second instruction
202 /// scheduling pass. This should return true if -print-machineinstrs should
203 /// print after these passes.
204 virtual bool addPreSched2() {
208 /// Add standard basic block placement passes.
209 virtual void addBlockPlacement();
211 /// addPreEmitPass - This pass may be implemented by targets that want to run
212 /// passes immediately before machine code is emitted. This should return
213 /// true if -print-machineinstrs should print out the code after the passes.
214 virtual bool addPreEmitPass() {
218 /// Utilities for targets to add passes to the pass manager.
221 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
222 /// Return the pass that was added, or NoPassID.
223 AnalysisID addPass(char &ID);
225 /// addMachinePasses helper to create the target-selected or overriden
227 FunctionPass *createRegAllocPass(bool Optimized);
229 /// printAndVerify - Add a pass to dump then verify the machine function, if
230 /// those steps are enabled.
232 void printAndVerify(const char *Banner) const;
236 /// List of target independent CodeGen pass IDs.
238 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
239 /// work well with unreachable basic blocks (what live ranges make sense for a
240 /// block that cannot be reached?). As such, a code generator should either
241 /// not instruction select unreachable blocks, or run this pass as its
242 /// last LLVM modifying pass to clean up blocks that are not reachable from
244 FunctionPass *createUnreachableBlockEliminationPass();
246 /// MachineFunctionPrinter pass - This pass prints out the machine function to
247 /// the given stream as a debugging tool.
248 MachineFunctionPass *
249 createMachineFunctionPrinterPass(raw_ostream &OS,
250 const std::string &Banner ="");
252 /// MachineLoopInfo - This pass is a loop analysis pass.
253 extern char &MachineLoopInfoID;
255 /// MachineLoopRanges - This pass is an on-demand loop coverage analysis.
256 extern char &MachineLoopRangesID;
258 /// MachineDominators - This pass is a machine dominators analysis pass.
259 extern char &MachineDominatorsID;
261 /// EdgeBundles analysis - Bundle machine CFG edges.
262 extern char &EdgeBundlesID;
264 /// LiveVariables pass - This pass computes the set of blocks in which each
265 /// variable is life and sets machine operand kill flags.
266 extern char &LiveVariablesID;
268 /// PHIElimination - This pass eliminates machine instruction PHI nodes
269 /// by inserting copy instructions. This destroys SSA information, but is the
270 /// desired input for some register allocators. This pass is "required" by
271 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
272 extern char &PHIEliminationID;
274 /// StrongPHIElimination - This pass eliminates machine instruction PHI
275 /// nodes by inserting copy instructions. This destroys SSA information, but
276 /// is the desired input for some register allocators. This pass is
277 /// "required" by these register allocator like this:
278 /// AU.addRequiredID(PHIEliminationID);
279 /// This pass is still in development
280 extern char &StrongPHIEliminationID;
282 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
283 extern char &LiveStacksID;
285 /// TwoAddressInstruction - This pass reduces two-address instructions to
286 /// use two operands. This destroys SSA information but it is desired by
287 /// register allocators.
288 extern char &TwoAddressInstructionPassID;
290 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
291 extern char &ProcessImplicitDefsID;
293 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
294 extern char &RegisterCoalescerID;
296 /// MachineScheduler - This pass schedules machine instructions.
297 extern char &MachineSchedulerID;
299 /// SpillPlacement analysis. Suggest optimal placement of spill code between
301 extern char &SpillPlacementID;
303 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
304 /// assigned in VirtRegMap.
305 extern char &VirtRegRewriterID;
307 /// UnreachableMachineBlockElimination - This pass removes unreachable
308 /// machine basic blocks.
309 extern char &UnreachableMachineBlockElimID;
311 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
312 extern char &DeadMachineInstructionElimID;
314 /// FastRegisterAllocation Pass - This pass register allocates as fast as
315 /// possible. It is best suited for debug code where live ranges are short.
317 FunctionPass *createFastRegisterAllocator();
319 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
320 /// register allocator using the basic regalloc framework.
322 FunctionPass *createBasicRegisterAllocator();
324 /// Greedy register allocation pass - This pass implements a global register
325 /// allocator for optimized builds.
327 FunctionPass *createGreedyRegisterAllocator();
329 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
330 /// Quadratic Prograaming (PBQP) based register allocator.
332 FunctionPass *createDefaultPBQPRegisterAllocator();
334 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
335 /// and eliminates abstract frame references.
336 extern char &PrologEpilogCodeInserterID;
338 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
339 /// register allocation.
340 extern char &ExpandPostRAPseudosID;
342 /// createPostRAScheduler - This pass performs post register allocation
344 extern char &PostRASchedulerID;
346 /// BranchFolding - This pass performs machine code CFG based
347 /// optimizations to delete branches to branches, eliminate branches to
348 /// successor blocks (creating fall throughs), and eliminating branches over
350 extern char &BranchFolderPassID;
352 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
353 extern char &MachineFunctionPrinterPassID;
355 /// TailDuplicate - Duplicate blocks with unconditional branches
356 /// into tails of their predecessors.
357 extern char &TailDuplicateID;
359 /// IfConverter - This pass performs machine code if conversion.
360 extern char &IfConverterID;
362 /// MachineBlockPlacement - This pass places basic blocks based on branch
364 extern char &MachineBlockPlacementID;
366 /// MachineBlockPlacementStats - This pass collects statistics about the
367 /// basic block placement using branch probabilities and block frequency
369 extern char &MachineBlockPlacementStatsID;
371 /// Code Placement - This pass optimize code placement and aligns loop
372 /// headers to target specific alignment boundary.
373 extern char &CodePlacementOptID;
375 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
376 /// highly portable strategies.
378 FunctionPass *createGCLoweringPass();
380 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
381 /// in machine code. Must be added very late during code generation, just
382 /// prior to output, and importantly after all CFG transformations (such as
384 extern char &GCMachineCodeAnalysisID;
386 /// Deleter Pass - Releases GC metadata.
388 FunctionPass *createGCInfoDeleter();
390 /// Creates a pass to print GC metadata.
392 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
394 /// MachineCSE - This pass performs global CSE on machine instructions.
395 extern char &MachineCSEID;
397 /// MachineLICM - This pass performs LICM on machine instructions.
398 extern char &MachineLICMID;
400 /// MachineSinking - This pass performs sinking on machine instructions.
401 extern char &MachineSinkingID;
403 /// MachineCopyPropagation - This pass performs copy propagation on
404 /// machine instructions.
405 extern char &MachineCopyPropagationID;
407 /// PeepholeOptimizer - This pass performs peephole optimizations -
408 /// like extension and comparison eliminations.
409 extern char &PeepholeOptimizerID;
411 /// OptimizePHIs - This pass optimizes machine instruction PHIs
412 /// to take advantage of opportunities created during DAG legalization.
413 extern char &OptimizePHIsID;
415 /// StackSlotColoring - This pass performs stack slot coloring.
416 extern char &StackSlotColoringID;
418 /// createStackProtectorPass - This pass adds stack protectors to functions.
420 FunctionPass *createStackProtectorPass(const TargetLowering *tli);
422 /// createMachineVerifierPass - This pass verifies cenerated machine code
423 /// instructions for correctness.
425 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
427 /// createDwarfEHPass - This pass mulches exception handling code into a form
428 /// adapted to code generation. Required if using dwarf exception handling.
429 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
431 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
432 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
434 FunctionPass *createSjLjEHPreparePass(const TargetLowering *tli);
436 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
437 /// slots relative to one another and allocates base registers to access them
438 /// when it is estimated by the target to be out of range of normal frame
439 /// pointer or stack pointer index addressing.
440 extern char &LocalStackSlotAllocationID;
442 /// ExpandISelPseudos - This pass expands pseudo-instructions.
443 extern char &ExpandISelPseudosID;
445 /// createExecutionDependencyFixPass - This pass fixes execution time
446 /// problems with dependent instructions, such as switching execution
447 /// domains to match.
449 /// The pass will examine instructions using and defining registers in RC.
451 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
453 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
454 extern char &UnpackMachineBundlesID;
456 /// FinalizeMachineBundles - This pass finalize machine instruction
457 /// bundles (created earlier, e.g. during pre-RA scheduling).
458 extern char &FinalizeMachineBundlesID;
460 } // End llvm namespace