1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides a MachineSchedRegistry for registering alternative machine
11 // schedulers. A Target may provide an alternative scheduler implementation by
12 // implementing the following boilerplate:
14 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
15 // return new CustomMachineScheduler(C);
17 // static MachineSchedRegistry
18 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
19 // createCustomMachineSched);
21 // Inside <Target>PassConfig:
22 // enablePass(&MachineSchedulerID);
23 // MachineSchedRegistry::setDefault(createCustomMachineSched);
25 //===----------------------------------------------------------------------===//
27 #ifndef MACHINESCHEDULER_H
28 #define MACHINESCHEDULER_H
30 #include "llvm/CodeGen/MachinePassRegistry.h"
31 #include "llvm/CodeGen/RegisterPressure.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
33 #include "llvm/Target/TargetInstrInfo.h"
37 extern cl::opt<bool> ForceTopDown;
38 extern cl::opt<bool> ForceBottomUp;
42 class MachineDominatorTree;
43 class MachineLoopInfo;
44 class RegisterClassInfo;
45 class ScheduleDAGInstrs;
47 /// MachineSchedContext provides enough context from the MachineScheduler pass
48 /// for the target to instantiate a scheduler.
49 struct MachineSchedContext {
51 const MachineLoopInfo *MLI;
52 const MachineDominatorTree *MDT;
53 const TargetPassConfig *PassConfig;
57 RegisterClassInfo *RegClassInfo;
59 MachineSchedContext();
60 virtual ~MachineSchedContext();
63 /// MachineSchedRegistry provides a selection of available machine instruction
65 class MachineSchedRegistry : public MachinePassRegistryNode {
67 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
69 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
70 typedef ScheduleDAGCtor FunctionPassCtor;
72 static MachinePassRegistry Registry;
74 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
75 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
78 ~MachineSchedRegistry() { Registry.Remove(this); }
82 MachineSchedRegistry *getNext() const {
83 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
85 static MachineSchedRegistry *getList() {
86 return (MachineSchedRegistry *)Registry.getList();
88 static ScheduleDAGCtor getDefault() {
89 return (ScheduleDAGCtor)Registry.getDefault();
91 static void setDefault(ScheduleDAGCtor C) {
92 Registry.setDefault((MachinePassCtor)C);
94 static void setDefault(StringRef Name) {
95 Registry.setDefault(Name);
97 static void setListener(MachinePassRegistryListener *L) {
98 Registry.setListener(L);
104 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
106 class MachineSchedStrategy {
108 virtual ~MachineSchedStrategy() {}
110 /// Initialize the strategy after building the DAG for a new region.
111 virtual void initialize(ScheduleDAGMI *DAG) = 0;
113 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
114 /// schedule the node at the top of the unscheduled region. Otherwise it will
115 /// be scheduled at the bottom.
116 virtual SUnit *pickNode(bool &IsTopNode) = 0;
118 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
119 /// instruction and updated scheduled/remaining flags in the DAG nodes.
120 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
122 /// When all predecessor dependencies have been resolved, free this node for
123 /// top-down scheduling.
124 virtual void releaseTopNode(SUnit *SU) = 0;
125 /// When all successor dependencies have been resolved, free this node for
126 /// bottom-up scheduling.
127 virtual void releaseBottomNode(SUnit *SU) = 0;
130 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
131 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
132 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
134 /// This is a convenience class that may be used by implementations of
135 /// MachineSchedStrategy.
139 std::vector<SUnit*> Queue;
142 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
144 unsigned getID() const { return ID; }
146 StringRef getName() const { return Name; }
148 // SU is in this queue if it's NodeQueueID is a superset of this ID.
149 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
151 bool empty() const { return Queue.empty(); }
153 unsigned size() const { return Queue.size(); }
155 typedef std::vector<SUnit*>::iterator iterator;
157 iterator begin() { return Queue.begin(); }
159 iterator end() { return Queue.end(); }
161 iterator find(SUnit *SU) {
162 return std::find(Queue.begin(), Queue.end(), SU);
165 void push(SUnit *SU) {
167 SU->NodeQueueId |= ID;
170 void remove(iterator I) {
171 (*I)->NodeQueueId &= ~ID;
181 /// Mutate the DAG as a postpass after normal DAG building.
182 class ScheduleDAGMutation {
184 virtual ~ScheduleDAGMutation() {}
186 virtual void apply(ScheduleDAGMI *DAG) = 0;
189 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
190 /// machine instructions while updating LiveIntervals and tracking regpressure.
191 class ScheduleDAGMI : public ScheduleDAGInstrs {
194 RegisterClassInfo *RegClassInfo;
195 MachineSchedStrategy *SchedImpl;
197 /// Ordered list of DAG postprocessing steps.
198 std::vector<ScheduleDAGMutation*> Mutations;
200 MachineBasicBlock::iterator LiveRegionEnd;
202 /// Register pressure in this region computed by buildSchedGraph.
203 IntervalPressure RegPressure;
204 RegPressureTracker RPTracker;
206 /// List of pressure sets that exceed the target's pressure limit before
207 /// scheduling, listed in increasing set ID order. Each pressure set is paired
208 /// with its max pressure in the currently scheduled regions.
209 std::vector<PressureElement> RegionCriticalPSets;
211 /// The top of the unscheduled zone.
212 MachineBasicBlock::iterator CurrentTop;
213 IntervalPressure TopPressure;
214 RegPressureTracker TopRPTracker;
216 /// The bottom of the unscheduled zone.
217 MachineBasicBlock::iterator CurrentBottom;
218 IntervalPressure BotPressure;
219 RegPressureTracker BotRPTracker;
222 /// The number of instructions scheduled so far. Used to cut off the
223 /// scheduler at the point determined by misched-cutoff.
224 unsigned NumInstrsScheduled;
228 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
229 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
230 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
231 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
232 CurrentBottom(), BotRPTracker(BotPressure) {
234 NumInstrsScheduled = 0;
238 virtual ~ScheduleDAGMI() {
242 /// Add a postprocessing step to the DAG builder.
243 /// Mutations are applied in the order that they are added after normal DAG
244 /// building and before MachineSchedStrategy initialization.
245 void addMutation(ScheduleDAGMutation *Mutation) {
246 Mutations.push_back(Mutation);
249 MachineBasicBlock::iterator top() const { return CurrentTop; }
250 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
252 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
253 /// region. This covers all instructions in a block, while schedule() may only
255 void enterRegion(MachineBasicBlock *bb,
256 MachineBasicBlock::iterator begin,
257 MachineBasicBlock::iterator end,
261 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
262 /// reorderable instructions.
263 virtual void schedule();
265 /// Get current register pressure for the top scheduled instructions.
266 const IntervalPressure &getTopPressure() const { return TopPressure; }
267 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
269 /// Get current register pressure for the bottom scheduled instructions.
270 const IntervalPressure &getBotPressure() const { return BotPressure; }
271 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
273 /// Get register pressure for the entire scheduling region before scheduling.
274 const IntervalPressure &getRegPressure() const { return RegPressure; }
276 const std::vector<PressureElement> &getRegionCriticalPSets() const {
277 return RegionCriticalPSets;
281 // Top-Level entry points for the schedule() driver...
283 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
284 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
285 /// region, TopTracker and BottomTracker will be initialized to the top and
286 /// bottom of the DAG region without covereing any unscheduled instruction.
287 void buildDAGWithRegPressure();
289 /// Apply each ScheduleDAGMutation step in order. This allows different
290 /// instances of ScheduleDAGMI to perform custom DAG postprocessing.
291 void postprocessDAG();
293 /// Identify DAG roots and setup scheduler queues.
296 /// Move an instruction and update register pressure.
297 void scheduleMI(SUnit *SU, bool IsTopNode);
299 /// Update scheduler DAG and queues after scheduling an instruction.
300 void updateQueues(SUnit *SU, bool IsTopNode);
302 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
303 void placeDebugValues();
307 void initRegPressure();
309 void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
311 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
312 bool checkSchedLimit();
316 void releaseSucc(SUnit *SU, SDep *SuccEdge);
317 void releaseSuccessors(SUnit *SU);
318 void releasePred(SUnit *SU, SDep *PredEdge);
319 void releasePredecessors(SUnit *SU);