1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/DenseMapInfo.h"
28 #include "llvm/Support/DebugLoc.h"
33 template <typename T> class SmallVectorImpl;
35 class TargetInstrInfo;
36 class TargetRegisterClass;
37 class TargetRegisterInfo;
38 class MachineFunction;
39 class MachineMemOperand;
41 //===----------------------------------------------------------------------===//
42 /// MachineInstr - Representation of each machine instruction.
44 class MachineInstr : public ilist_node<MachineInstr> {
46 typedef MachineMemOperand **mmo_iterator;
48 /// Flags to specify different kinds of comments to output in
49 /// assembly code. These flags carry semantic information not
50 /// otherwise easily derivable from the IR text.
58 FrameSetup = 1 << 0, // Instruction is used as a part of
59 // function frame setup code.
60 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
61 // the first MI in a bundle)
64 const MCInstrDesc *MCID; // Instruction descriptor.
66 uint8_t Flags; // Various bits of additional
67 // information about machine
70 uint8_t AsmPrinterFlags; // Various bits of information used by
71 // the AsmPrinter to emit helpful
72 // comments. This is *not* semantic
73 // information. Do not use this for
74 // anything other than to convey comment
75 // information to AsmPrinter.
77 uint16_t NumMemRefs; // information on memory references
80 std::vector<MachineOperand> Operands; // the operands
81 MachineBasicBlock *Parent; // Pointer to the owning basic block.
82 DebugLoc debugLoc; // Source line information.
84 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
85 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
87 // Intrusive list support
88 friend struct ilist_traits<MachineInstr>;
89 friend struct ilist_traits<MachineBasicBlock>;
90 void setParent(MachineBasicBlock *P) { Parent = P; }
92 /// MachineInstr ctor - This constructor creates a copy of the given
93 /// MachineInstr in the given MachineFunction.
94 MachineInstr(MachineFunction &, const MachineInstr &);
96 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
97 /// MCID NULL and no operands.
100 // The next two constructors have DebugLoc and non-DebugLoc versions;
101 // over time, the non-DebugLoc versions should be phased out and eventually
104 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
105 /// implicit operands. It reserves space for the number of operands specified
106 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
107 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
109 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
110 /// the MachineInstr is created and added to the end of the specified basic
111 /// block. The version with a DebugLoc should be preferred.
112 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
114 /// MachineInstr ctor - This constructor create a MachineInstr and add the
115 /// implicit operands. It reserves space for number of operands specified by
116 /// MCInstrDesc. An explicit DebugLoc is supplied.
117 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
120 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
121 /// the MachineInstr is created and added to the end of the specified basic
123 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
124 const MCInstrDesc &MCID);
128 // MachineInstrs are pool-allocated and owned by MachineFunction.
129 friend class MachineFunction;
132 const MachineBasicBlock* getParent() const { return Parent; }
133 MachineBasicBlock* getParent() { return Parent; }
135 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
137 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
139 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
141 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
143 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
145 bool getAsmPrinterFlag(CommentFlag Flag) const {
146 return AsmPrinterFlags & Flag;
149 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
151 void setAsmPrinterFlag(CommentFlag Flag) {
152 AsmPrinterFlags |= (uint8_t)Flag;
155 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
157 void clearAsmPrinterFlag(CommentFlag Flag) {
158 AsmPrinterFlags &= ~Flag;
161 /// getFlags - Return the MI flags bitvector.
162 uint8_t getFlags() const {
166 /// getFlag - Return whether an MI flag is set.
167 bool getFlag(MIFlag Flag) const {
171 /// setFlag - Set a MI flag.
172 void setFlag(MIFlag Flag) {
173 Flags |= (uint8_t)Flag;
176 void setFlags(unsigned flags) {
180 /// clearFlag - Clear a MI flag.
181 void clearFlag(MIFlag Flag) {
182 Flags &= ~((uint8_t)Flag);
185 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
188 /// A bundle looks like this before it's finalized:
200 /// In this case, the first MI starts a bundle but is not inside a bundle, the
201 /// next 2 MIs are considered "inside" the bundle.
203 /// After a bundle is finalized, it looks like this:
219 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
220 /// a bundle, but the next three MIs are.
221 bool isInsideBundle() const {
222 return getFlag(InsideBundle);
225 /// setIsInsideBundle - Set InsideBundle bit.
227 void setIsInsideBundle(bool Val = true) {
229 setFlag(InsideBundle);
231 clearFlag(InsideBundle);
234 /// isBundled - Return true if this instruction part of a bundle. This is true
235 /// if either itself or its following instruction is marked "InsideBundle".
236 bool isBundled() const;
238 /// getDebugLoc - Returns the debug location id of this MachineInstr.
240 DebugLoc getDebugLoc() const { return debugLoc; }
242 /// emitError - Emit an error referring to the source location of this
243 /// instruction. This should only be used for inline assembly that is somehow
244 /// impossible to compile. Other errors should have been handled much
247 /// If this method returns, the caller should try to recover from the error.
249 void emitError(StringRef Msg) const;
251 /// getDesc - Returns the target instruction descriptor of this
253 const MCInstrDesc &getDesc() const { return *MCID; }
255 /// getOpcode - Returns the opcode of this MachineInstr.
257 int getOpcode() const { return MCID->Opcode; }
259 /// Access to explicit operands of the instruction.
261 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
263 const MachineOperand& getOperand(unsigned i) const {
264 assert(i < getNumOperands() && "getOperand() out of range!");
267 MachineOperand& getOperand(unsigned i) {
268 assert(i < getNumOperands() && "getOperand() out of range!");
272 /// getNumExplicitOperands - Returns the number of non-implicit operands.
274 unsigned getNumExplicitOperands() const;
276 /// iterator/begin/end - Iterate over all operands of a machine instruction.
277 typedef std::vector<MachineOperand>::iterator mop_iterator;
278 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
280 mop_iterator operands_begin() { return Operands.begin(); }
281 mop_iterator operands_end() { return Operands.end(); }
283 const_mop_iterator operands_begin() const { return Operands.begin(); }
284 const_mop_iterator operands_end() const { return Operands.end(); }
286 /// Access to memory operands of the instruction
287 mmo_iterator memoperands_begin() const { return MemRefs; }
288 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
289 bool memoperands_empty() const { return NumMemRefs == 0; }
291 /// hasOneMemOperand - Return true if this instruction has exactly one
292 /// MachineMemOperand.
293 bool hasOneMemOperand() const {
294 return NumMemRefs == 1;
297 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
298 /// queries but they are bundle aware.
301 IgnoreBundle, // Ignore bundles
302 AnyInBundle, // Return true if any instruction in bundle has property
303 AllInBundle // Return true if all instructions in bundle have property
306 /// hasProperty - Return true if the instruction (or in the case of a bundle,
307 /// the instructions inside the bundle) has the specified property.
308 /// The first argument is the property being queried.
309 /// The second argument indicates whether the query should look inside
310 /// instruction bundles.
311 bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
313 /// isVariadic - Return true if this instruction can have a variable number of
314 /// operands. In this case, the variable operands will be after the normal
315 /// operands but before the implicit definitions and uses (if any are
317 bool isVariadic(QueryType Type = IgnoreBundle) const {
318 return hasProperty(MCID::Variadic, Type);
321 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
322 /// ARM instructions which can set condition code if 's' bit is set.
323 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
324 return hasProperty(MCID::HasOptionalDef, Type);
327 /// isPseudo - Return true if this is a pseudo instruction that doesn't
328 /// correspond to a real machine instruction.
330 bool isPseudo(QueryType Type = IgnoreBundle) const {
331 return hasProperty(MCID::Pseudo, Type);
334 bool isReturn(QueryType Type = AnyInBundle) const {
335 return hasProperty(MCID::Return, Type);
338 bool isCall(QueryType Type = AnyInBundle) const {
339 return hasProperty(MCID::Call, Type);
342 /// isBarrier - Returns true if the specified instruction stops control flow
343 /// from executing the instruction immediately following it. Examples include
344 /// unconditional branches and return instructions.
345 bool isBarrier(QueryType Type = AnyInBundle) const {
346 return hasProperty(MCID::Barrier, Type);
349 /// isTerminator - Returns true if this instruction part of the terminator for
350 /// a basic block. Typically this is things like return and branch
353 /// Various passes use this to insert code into the bottom of a basic block,
354 /// but before control flow occurs.
355 bool isTerminator(QueryType Type = AnyInBundle) const {
356 return hasProperty(MCID::Terminator, Type);
359 /// isBranch - Returns true if this is a conditional, unconditional, or
360 /// indirect branch. Predicates below can be used to discriminate between
361 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
362 /// get more information.
363 bool isBranch(QueryType Type = AnyInBundle) const {
364 return hasProperty(MCID::Branch, Type);
367 /// isIndirectBranch - Return true if this is an indirect branch, such as a
368 /// branch through a register.
369 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
370 return hasProperty(MCID::IndirectBranch, Type);
373 /// isConditionalBranch - Return true if this is a branch which may fall
374 /// through to the next instruction or may transfer control flow to some other
375 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
376 /// information about this branch.
377 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
378 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
381 /// isUnconditionalBranch - Return true if this is a branch which always
382 /// transfers control flow to some other block. The
383 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
384 /// about this branch.
385 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
386 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
389 // isPredicable - Return true if this instruction has a predicate operand that
390 // controls execution. It may be set to 'always', or may be set to other
391 /// values. There are various methods in TargetInstrInfo that can be used to
392 /// control and modify the predicate in this instruction.
393 bool isPredicable(QueryType Type = AllInBundle) const {
394 // If it's a bundle than all bundled instructions must be predicable for this
396 return hasProperty(MCID::Predicable, Type);
399 /// isCompare - Return true if this instruction is a comparison.
400 bool isCompare(QueryType Type = IgnoreBundle) const {
401 return hasProperty(MCID::Compare, Type);
404 /// isMoveImmediate - Return true if this instruction is a move immediate
405 /// (including conditional moves) instruction.
406 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
407 return hasProperty(MCID::MoveImm, Type);
410 /// isBitcast - Return true if this instruction is a bitcast instruction.
412 bool isBitcast(QueryType Type = IgnoreBundle) const {
413 return hasProperty(MCID::Bitcast, Type);
416 /// isNotDuplicable - Return true if this instruction cannot be safely
417 /// duplicated. For example, if the instruction has a unique labels attached
418 /// to it, duplicating it would cause multiple definition errors.
419 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
420 return hasProperty(MCID::NotDuplicable, Type);
423 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
424 /// which must be filled by the code generator.
425 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
426 return hasProperty(MCID::DelaySlot, Type);
429 /// canFoldAsLoad - Return true for instructions that can be folded as
430 /// memory operands in other instructions. The most common use for this
431 /// is instructions that are simple loads from memory that don't modify
432 /// the loaded value in any way, but it can also be used for instructions
433 /// that can be expressed as constant-pool loads, such as V_SETALLONES
434 /// on x86, to allow them to be folded when it is beneficial.
435 /// This should only be set on instructions that return a value in their
436 /// only virtual register definition.
437 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
438 return hasProperty(MCID::FoldableAsLoad, Type);
441 //===--------------------------------------------------------------------===//
442 // Side Effect Analysis
443 //===--------------------------------------------------------------------===//
445 /// mayLoad - Return true if this instruction could possibly read memory.
446 /// Instructions with this flag set are not necessarily simple load
447 /// instructions, they may load a value and modify it, for example.
448 bool mayLoad(QueryType Type = AnyInBundle) const {
449 return hasProperty(MCID::MayLoad, Type);
453 /// mayStore - Return true if this instruction could possibly modify memory.
454 /// Instructions with this flag set are not necessarily simple store
455 /// instructions, they may store a modified value based on their operands, or
456 /// may not actually modify anything, for example.
457 bool mayStore(QueryType Type = AnyInBundle) const {
458 return hasProperty(MCID::MayStore, Type);
461 //===--------------------------------------------------------------------===//
462 // Flags that indicate whether an instruction can be modified by a method.
463 //===--------------------------------------------------------------------===//
465 /// isCommutable - Return true if this may be a 2- or 3-address
466 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
467 /// result if Y and Z are exchanged. If this flag is set, then the
468 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
471 /// Note that this flag may be set on instructions that are only commutable
472 /// sometimes. In these cases, the call to commuteInstruction will fail.
473 /// Also note that some instructions require non-trivial modification to
475 bool isCommutable(QueryType Type = IgnoreBundle) const {
476 return hasProperty(MCID::Commutable, Type);
479 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
480 /// which can be changed into a 3-address instruction if needed. Doing this
481 /// transformation can be profitable in the register allocator, because it
482 /// means that the instruction can use a 2-address form if possible, but
483 /// degrade into a less efficient form if the source and dest register cannot
484 /// be assigned to the same register. For example, this allows the x86
485 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
486 /// is the same speed as the shift but has bigger code size.
488 /// If this returns true, then the target must implement the
489 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
490 /// is allowed to fail if the transformation isn't valid for this specific
491 /// instruction (e.g. shl reg, 4 on x86).
493 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
494 return hasProperty(MCID::ConvertibleTo3Addr, Type);
497 /// usesCustomInsertionHook - Return true if this instruction requires
498 /// custom insertion support when the DAG scheduler is inserting it into a
499 /// machine basic block. If this is true for the instruction, it basically
500 /// means that it is a pseudo instruction used at SelectionDAG time that is
501 /// expanded out into magic code by the target when MachineInstrs are formed.
503 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
504 /// is used to insert this into the MachineBasicBlock.
505 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
506 return hasProperty(MCID::UsesCustomInserter, Type);
509 /// hasPostISelHook - Return true if this instruction requires *adjustment*
510 /// after instruction selection by calling a target hook. For example, this
511 /// can be used to fill in ARM 's' optional operand depending on whether
512 /// the conditional flag register is used.
513 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
514 return hasProperty(MCID::HasPostISelHook, Type);
517 /// isRematerializable - Returns true if this instruction is a candidate for
518 /// remat. This flag is deprecated, please don't use it anymore. If this
519 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
520 /// verify the instruction is really rematable.
521 bool isRematerializable(QueryType Type = AllInBundle) const {
522 // It's only possible to re-mat a bundle if all bundled instructions are
523 // re-materializable.
524 return hasProperty(MCID::Rematerializable, Type);
527 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
528 /// less) than a move instruction. This is useful during certain types of
529 /// optimizations (e.g., remat during two-address conversion or machine licm)
530 /// where we would like to remat or hoist the instruction, but not if it costs
531 /// more than moving the instruction into the appropriate register. Note, we
532 /// are not marking copies from and to the same register class with this flag.
533 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
534 // Only returns true for a bundle if all bundled instructions are cheap.
535 // FIXME: This probably requires a target hook.
536 return hasProperty(MCID::CheapAsAMove, Type);
539 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
540 /// have special register allocation requirements that are not captured by the
541 /// operand register classes. e.g. ARM::STRD's two source registers must be an
542 /// even / odd pair, ARM::STM registers have to be in ascending order.
543 /// Post-register allocation passes should not attempt to change allocations
544 /// for sources of instructions with this flag.
545 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
546 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
549 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
550 /// have special register allocation requirements that are not captured by the
551 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
552 /// even / odd pair, ARM::LDM registers have to be in ascending order.
553 /// Post-register allocation passes should not attempt to change allocations
554 /// for definitions of instructions with this flag.
555 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
556 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
561 CheckDefs, // Check all operands for equality
562 CheckKillDead, // Check all operands including kill / dead markers
563 IgnoreDefs, // Ignore all definitions
564 IgnoreVRegDefs // Ignore virtual register definitions
567 /// isIdenticalTo - Return true if this instruction is identical to (same
568 /// opcode and same operands as) the specified instruction.
569 bool isIdenticalTo(const MachineInstr *Other,
570 MICheckType Check = CheckDefs) const;
572 /// removeFromParent - This method unlinks 'this' from the containing basic
573 /// block, and returns it, but does not delete it.
574 MachineInstr *removeFromParent();
576 /// eraseFromParent - This method unlinks 'this' from the containing basic
577 /// block and deletes it.
578 void eraseFromParent();
580 /// isLabel - Returns true if the MachineInstr represents a label.
582 bool isLabel() const {
583 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
584 getOpcode() == TargetOpcode::EH_LABEL ||
585 getOpcode() == TargetOpcode::GC_LABEL;
588 bool isPrologLabel() const {
589 return getOpcode() == TargetOpcode::PROLOG_LABEL;
591 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
592 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
593 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
595 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
596 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
597 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
598 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
599 bool isStackAligningInlineAsm() const;
600 bool isInsertSubreg() const {
601 return getOpcode() == TargetOpcode::INSERT_SUBREG;
603 bool isSubregToReg() const {
604 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
606 bool isRegSequence() const {
607 return getOpcode() == TargetOpcode::REG_SEQUENCE;
609 bool isBundle() const {
610 return getOpcode() == TargetOpcode::BUNDLE;
612 bool isCopy() const {
613 return getOpcode() == TargetOpcode::COPY;
615 bool isFullCopy() const {
616 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
619 /// isCopyLike - Return true if the instruction behaves like a copy.
620 /// This does not include native copy instructions.
621 bool isCopyLike() const {
622 return isCopy() || isSubregToReg();
625 /// isIdentityCopy - Return true is the instruction is an identity copy.
626 bool isIdentityCopy() const {
627 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
628 getOperand(0).getSubReg() == getOperand(1).getSubReg();
631 /// getBundleSize - Return the number of instructions inside the MI bundle.
632 unsigned getBundleSize() const;
634 /// readsRegister - Return true if the MachineInstr reads the specified
635 /// register. If TargetRegisterInfo is passed, then it also checks if there
636 /// is a read of a super-register.
637 /// This does not count partial redefines of virtual registers as reads:
639 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
640 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
643 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
644 /// virtual register. Take into account that a partial define is a
645 /// read-modify-write operation.
646 bool readsVirtualRegister(unsigned Reg) const {
647 return readsWritesVirtualRegister(Reg).first;
650 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
651 /// indicating if this instruction reads or writes Reg. This also considers
653 /// If Ops is not null, all operand indices for Reg are added.
654 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
655 SmallVectorImpl<unsigned> *Ops = 0) const;
657 /// killsRegister - Return true if the MachineInstr kills the specified
658 /// register. If TargetRegisterInfo is passed, then it also checks if there is
659 /// a kill of a super-register.
660 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
661 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
664 /// definesRegister - Return true if the MachineInstr fully defines the
665 /// specified register. If TargetRegisterInfo is passed, then it also checks
666 /// if there is a def of a super-register.
667 /// NOTE: It's ignoring subreg indices on virtual registers.
668 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
669 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
672 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
673 /// or partially define) the specified register.
674 /// NOTE: It's ignoring subreg indices on virtual registers.
675 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
676 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
679 /// registerDefIsDead - Returns true if the register is dead in this machine
680 /// instruction. If TargetRegisterInfo is passed, then it also checks
681 /// if there is a dead def of a super-register.
682 bool registerDefIsDead(unsigned Reg,
683 const TargetRegisterInfo *TRI = NULL) const {
684 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
687 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
688 /// the specific register or -1 if it is not found. It further tightens
689 /// the search criteria to a use that kills the register if isKill is true.
690 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
691 const TargetRegisterInfo *TRI = NULL) const;
693 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
694 /// a pointer to the MachineOperand rather than an index.
695 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
696 const TargetRegisterInfo *TRI = NULL) {
697 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
698 return (Idx == -1) ? NULL : &getOperand(Idx);
701 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
702 /// the specified register or -1 if it is not found. If isDead is true, defs
703 /// that are not dead are skipped. If Overlap is true, then it also looks for
704 /// defs that merely overlap the specified register. If TargetRegisterInfo is
705 /// non-null, then it also checks if there is a def of a super-register.
706 /// This may also return a register mask operand when Overlap is true.
707 int findRegisterDefOperandIdx(unsigned Reg,
708 bool isDead = false, bool Overlap = false,
709 const TargetRegisterInfo *TRI = NULL) const;
711 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
712 /// a pointer to the MachineOperand rather than an index.
713 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
714 const TargetRegisterInfo *TRI = NULL) {
715 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
716 return (Idx == -1) ? NULL : &getOperand(Idx);
719 /// findFirstPredOperandIdx() - Find the index of the first operand in the
720 /// operand list that is used to represent the predicate. It returns -1 if
722 int findFirstPredOperandIdx() const;
724 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
725 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
726 /// getOperand(OpIdx) does not belong to an inline asm operand group.
728 /// If GroupNo is not NULL, it will receive the number of the operand group
729 /// containing OpIdx.
731 /// The flag operand is an immediate that can be decoded with methods like
732 /// InlineAsm::hasRegClassConstraint().
734 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
736 /// getRegClassConstraint - Compute the static register class constraint for
737 /// operand OpIdx. For normal instructions, this is derived from the
738 /// MCInstrDesc. For inline assembly it is derived from the flag words.
740 /// Returns NULL if the static register classs constraint cannot be
743 const TargetRegisterClass*
744 getRegClassConstraint(unsigned OpIdx,
745 const TargetInstrInfo *TII,
746 const TargetRegisterInfo *TRI) const;
748 /// isRegTiedToUseOperand - Given the index of a register def operand,
749 /// check if the register def is tied to a source operand, due to either
750 /// two-address elimination or inline assembly constraints. Returns the
751 /// first tied use operand index by reference if UseOpIdx is not null.
752 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
754 /// isRegTiedToDefOperand - Return true if the use operand of the specified
755 /// index is tied to an def operand. It also returns the def operand index by
756 /// reference if DefOpIdx is not null.
757 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
759 /// clearKillInfo - Clears kill flags on all operands.
761 void clearKillInfo();
763 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
765 void copyKillDeadInfo(const MachineInstr *MI);
767 /// copyPredicates - Copies predicate operand(s) from MI.
768 void copyPredicates(const MachineInstr *MI);
770 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
771 /// properly composing subreg indices where necessary.
772 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
773 const TargetRegisterInfo &RegInfo);
775 /// addRegisterKilled - We have determined MI kills a register. Look for the
776 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
777 /// add a implicit operand if it's not found. Returns true if the operand
778 /// exists / is added.
779 bool addRegisterKilled(unsigned IncomingReg,
780 const TargetRegisterInfo *RegInfo,
781 bool AddIfNotFound = false);
783 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
784 /// provided, this includes super-register kills.
785 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
787 /// addRegisterDead - We have determined MI defined a register without a use.
788 /// Look for the operand that defines it and mark it as IsDead. If
789 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
790 /// true if the operand exists / is added.
791 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
792 bool AddIfNotFound = false);
794 /// addRegisterDefined - We have determined MI defines a register. Make sure
795 /// there is an operand defining Reg.
796 void addRegisterDefined(unsigned IncomingReg,
797 const TargetRegisterInfo *RegInfo = 0);
799 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
800 /// dead except those in the UsedRegs list.
802 /// On instructions with register mask operands, also add implicit-def
803 /// operands for all registers in UsedRegs.
804 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
805 const TargetRegisterInfo &TRI);
807 /// isSafeToMove - Return true if it is safe to move this instruction. If
808 /// SawStore is set to true, it means that there is a store (or call) between
809 /// the instruction's location and its intended destination.
810 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
811 bool &SawStore) const;
813 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
814 /// instruction which defined the specified register instead of copying it.
815 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
816 unsigned DstReg) const;
818 /// hasVolatileMemoryRef - Return true if this instruction may have a
819 /// volatile memory reference, or if the information describing the
820 /// memory reference is not available. Return false if it is known to
821 /// have no volatile memory references.
822 bool hasVolatileMemoryRef() const;
824 /// isInvariantLoad - Return true if this instruction is loading from a
825 /// location whose value is invariant across the function. For example,
826 /// loading a value from the constant pool or from the argument area of
827 /// a function if it does not change. This should only return true of *all*
828 /// loads the instruction does are invariant (if it does multiple loads).
829 bool isInvariantLoad(AliasAnalysis *AA) const;
831 /// isConstantValuePHI - If the specified instruction is a PHI that always
832 /// merges together the same virtual register, return the register, otherwise
834 unsigned isConstantValuePHI() const;
836 /// hasUnmodeledSideEffects - Return true if this instruction has side
837 /// effects that are not modeled by mayLoad / mayStore, etc.
838 /// For all instructions, the property is encoded in MCInstrDesc::Flags
839 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
840 /// INLINEASM instruction, in which case the side effect property is encoded
841 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
843 bool hasUnmodeledSideEffects() const;
845 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
847 bool allDefsAreDead() const;
849 /// copyImplicitOps - Copy implicit register operands from specified
850 /// instruction to this instruction.
851 void copyImplicitOps(const MachineInstr *MI);
856 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
859 //===--------------------------------------------------------------------===//
860 // Accessors used to build up machine instructions.
862 /// addOperand - Add the specified operand to the instruction. If it is an
863 /// implicit operand, it is added to the end of the operand list. If it is
864 /// an explicit operand it is added at the end of the explicit operand list
865 /// (before the first implicit operand).
866 void addOperand(const MachineOperand &Op);
868 /// setDesc - Replace the instruction descriptor (thus opcode) of
869 /// the current instruction with a new one.
871 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
873 /// setDebugLoc - Replace current source information with new such.
874 /// Avoid using this, the constructor argument is preferable.
876 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
878 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
879 /// fewer operand than it started with.
881 void RemoveOperand(unsigned i);
883 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
884 /// This function should be used only occasionally. The setMemRefs function
885 /// is the primary method for setting up a MachineInstr's MemRefs list.
886 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
888 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
889 /// list. This does not transfer ownership.
890 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
891 MemRefs = NewMemRefs;
892 NumMemRefs = NewMemRefsEnd - NewMemRefs;
896 /// getRegInfo - If this instruction is embedded into a MachineFunction,
897 /// return the MachineRegisterInfo object for the current function, otherwise
899 MachineRegisterInfo *getRegInfo();
901 /// addImplicitDefUseOperands - Add all implicit def and use operands to
902 /// this instruction.
903 void addImplicitDefUseOperands();
905 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
906 /// this instruction from their respective use lists. This requires that the
907 /// operands already be on their use lists.
908 void RemoveRegOperandsFromUseLists();
910 /// AddRegOperandsToUseLists - Add all of the register operands in
911 /// this instruction from their respective use lists. This requires that the
912 /// operands not be on their use lists yet.
913 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
916 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
917 /// MachineInstr* by *value* of the instruction rather than by pointer value.
918 /// The hashing and equality testing functions ignore definitions so this is
919 /// useful for CSE, etc.
920 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
921 static inline MachineInstr *getEmptyKey() {
925 static inline MachineInstr *getTombstoneKey() {
926 return reinterpret_cast<MachineInstr*>(-1);
929 static unsigned getHashValue(const MachineInstr* const &MI);
931 static bool isEqual(const MachineInstr* const &LHS,
932 const MachineInstr* const &RHS) {
933 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
934 LHS == getEmptyKey() || LHS == getTombstoneKey())
936 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
940 //===----------------------------------------------------------------------===//
943 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
948 } // End llvm namespace