1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/DenseMapInfo.h"
28 #include "llvm/Support/DebugLoc.h"
33 template <typename T> class SmallVectorImpl;
35 class TargetInstrInfo;
36 class TargetRegisterClass;
37 class TargetRegisterInfo;
38 class MachineFunction;
39 class MachineMemOperand;
41 //===----------------------------------------------------------------------===//
42 /// MachineInstr - Representation of each machine instruction.
44 class MachineInstr : public ilist_node<MachineInstr> {
46 typedef MachineMemOperand **mmo_iterator;
48 /// Flags to specify different kinds of comments to output in
49 /// assembly code. These flags carry semantic information not
50 /// otherwise easily derivable from the IR text.
58 FrameSetup = 1 << 0, // Instruction is used as a part of
59 // function frame setup code.
60 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
61 // the first MI in a bundle)
64 const MCInstrDesc *MCID; // Instruction descriptor.
66 uint8_t Flags; // Various bits of additional
67 // information about machine
70 uint8_t AsmPrinterFlags; // Various bits of information used by
71 // the AsmPrinter to emit helpful
72 // comments. This is *not* semantic
73 // information. Do not use this for
74 // anything other than to convey comment
75 // information to AsmPrinter.
77 std::vector<MachineOperand> Operands; // the operands
78 mmo_iterator MemRefs; // information on memory references
79 mmo_iterator MemRefsEnd;
80 MachineBasicBlock *Parent; // Pointer to the owning basic block.
81 DebugLoc debugLoc; // Source line information.
83 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
84 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
86 // Intrusive list support
87 friend struct ilist_traits<MachineInstr>;
88 friend struct ilist_traits<MachineBasicBlock>;
89 void setParent(MachineBasicBlock *P) { Parent = P; }
91 /// MachineInstr ctor - This constructor creates a copy of the given
92 /// MachineInstr in the given MachineFunction.
93 MachineInstr(MachineFunction &, const MachineInstr &);
95 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
96 /// MCID NULL and no operands.
99 // The next two constructors have DebugLoc and non-DebugLoc versions;
100 // over time, the non-DebugLoc versions should be phased out and eventually
103 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
104 /// implicit operands. It reserves space for the number of operands specified
105 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
106 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
108 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
109 /// the MachineInstr is created and added to the end of the specified basic
110 /// block. The version with a DebugLoc should be preferred.
111 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
113 /// MachineInstr ctor - This constructor create a MachineInstr and add the
114 /// implicit operands. It reserves space for number of operands specified by
115 /// MCInstrDesc. An explicit DebugLoc is supplied.
116 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
119 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
120 /// the MachineInstr is created and added to the end of the specified basic
122 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
123 const MCInstrDesc &MCID);
127 // MachineInstrs are pool-allocated and owned by MachineFunction.
128 friend class MachineFunction;
131 const MachineBasicBlock* getParent() const { return Parent; }
132 MachineBasicBlock* getParent() { return Parent; }
134 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
136 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
138 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
140 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
142 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
144 bool getAsmPrinterFlag(CommentFlag Flag) const {
145 return AsmPrinterFlags & Flag;
148 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
150 void setAsmPrinterFlag(CommentFlag Flag) {
151 AsmPrinterFlags |= (uint8_t)Flag;
154 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
156 void clearAsmPrinterFlag(CommentFlag Flag) {
157 AsmPrinterFlags &= ~Flag;
160 /// getFlags - Return the MI flags bitvector.
161 uint8_t getFlags() const {
165 /// getFlag - Return whether an MI flag is set.
166 bool getFlag(MIFlag Flag) const {
170 /// setFlag - Set a MI flag.
171 void setFlag(MIFlag Flag) {
172 Flags |= (uint8_t)Flag;
175 void setFlags(unsigned flags) {
179 /// clearFlag - Clear a MI flag.
180 void clearFlag(MIFlag Flag) {
181 Flags &= ~((uint8_t)Flag);
184 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
187 /// A bundle looks like this before it's finalized:
199 /// In this case, the first MI starts a bundle but is not inside a bundle, the
200 /// next 2 MIs are considered "inside" the bundle.
202 /// After a bundle is finalized, it looks like this:
218 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
219 /// a bundle, but the next three MIs are.
220 bool isInsideBundle() const {
221 return getFlag(InsideBundle);
224 /// setIsInsideBundle - Set InsideBundle bit.
226 void setIsInsideBundle(bool Val = true) {
228 setFlag(InsideBundle);
230 clearFlag(InsideBundle);
233 /// isBundled - Return true if this instruction part of a bundle. This is true
234 /// if either itself or its following instruction is marked "InsideBundle".
235 bool isBundled() const;
237 /// getDebugLoc - Returns the debug location id of this MachineInstr.
239 DebugLoc getDebugLoc() const { return debugLoc; }
241 /// emitError - Emit an error referring to the source location of this
242 /// instruction. This should only be used for inline assembly that is somehow
243 /// impossible to compile. Other errors should have been handled much
246 /// If this method returns, the caller should try to recover from the error.
248 void emitError(StringRef Msg) const;
250 /// getDesc - Returns the target instruction descriptor of this
252 const MCInstrDesc &getDesc() const { return *MCID; }
254 /// getOpcode - Returns the opcode of this MachineInstr.
256 int getOpcode() const { return MCID->Opcode; }
258 /// Access to explicit operands of the instruction.
260 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
262 const MachineOperand& getOperand(unsigned i) const {
263 assert(i < getNumOperands() && "getOperand() out of range!");
266 MachineOperand& getOperand(unsigned i) {
267 assert(i < getNumOperands() && "getOperand() out of range!");
271 /// getNumExplicitOperands - Returns the number of non-implicit operands.
273 unsigned getNumExplicitOperands() const;
275 /// iterator/begin/end - Iterate over all operands of a machine instruction.
276 typedef std::vector<MachineOperand>::iterator mop_iterator;
277 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
279 mop_iterator operands_begin() { return Operands.begin(); }
280 mop_iterator operands_end() { return Operands.end(); }
282 const_mop_iterator operands_begin() const { return Operands.begin(); }
283 const_mop_iterator operands_end() const { return Operands.end(); }
285 /// Access to memory operands of the instruction
286 mmo_iterator memoperands_begin() const { return MemRefs; }
287 mmo_iterator memoperands_end() const { return MemRefsEnd; }
288 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
290 /// hasOneMemOperand - Return true if this instruction has exactly one
291 /// MachineMemOperand.
292 bool hasOneMemOperand() const {
293 return MemRefsEnd - MemRefs == 1;
296 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
297 /// queries but they are bundle aware.
300 IgnoreBundle, // Ignore bundles
301 AnyInBundle, // Return true if any instruction in bundle has property
302 AllInBundle // Return true if all instructions in bundle have property
305 /// hasProperty - Return true if the instruction (or in the case of a bundle,
306 /// the instructions inside the bundle) has the specified property.
307 /// The first argument is the property being queried.
308 /// The second argument indicates whether the query should look inside
309 /// instruction bundles.
310 bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
312 /// isVariadic - Return true if this instruction can have a variable number of
313 /// operands. In this case, the variable operands will be after the normal
314 /// operands but before the implicit definitions and uses (if any are
316 bool isVariadic(QueryType Type = IgnoreBundle) const {
317 return hasProperty(MCID::Variadic, Type);
320 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
321 /// ARM instructions which can set condition code if 's' bit is set.
322 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
323 return hasProperty(MCID::HasOptionalDef, Type);
326 /// isPseudo - Return true if this is a pseudo instruction that doesn't
327 /// correspond to a real machine instruction.
329 bool isPseudo(QueryType Type = IgnoreBundle) const {
330 return hasProperty(MCID::Pseudo, Type);
333 bool isReturn(QueryType Type = AnyInBundle) const {
334 return hasProperty(MCID::Return, Type);
337 bool isCall(QueryType Type = AnyInBundle) const {
338 return hasProperty(MCID::Call, Type);
341 /// isBarrier - Returns true if the specified instruction stops control flow
342 /// from executing the instruction immediately following it. Examples include
343 /// unconditional branches and return instructions.
344 bool isBarrier(QueryType Type = AnyInBundle) const {
345 return hasProperty(MCID::Barrier, Type);
348 /// isTerminator - Returns true if this instruction part of the terminator for
349 /// a basic block. Typically this is things like return and branch
352 /// Various passes use this to insert code into the bottom of a basic block,
353 /// but before control flow occurs.
354 bool isTerminator(QueryType Type = AnyInBundle) const {
355 return hasProperty(MCID::Terminator, Type);
358 /// isBranch - Returns true if this is a conditional, unconditional, or
359 /// indirect branch. Predicates below can be used to discriminate between
360 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
361 /// get more information.
362 bool isBranch(QueryType Type = AnyInBundle) const {
363 return hasProperty(MCID::Branch, Type);
366 /// isIndirectBranch - Return true if this is an indirect branch, such as a
367 /// branch through a register.
368 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
369 return hasProperty(MCID::IndirectBranch, Type);
372 /// isConditionalBranch - Return true if this is a branch which may fall
373 /// through to the next instruction or may transfer control flow to some other
374 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
375 /// information about this branch.
376 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
377 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
380 /// isUnconditionalBranch - Return true if this is a branch which always
381 /// transfers control flow to some other block. The
382 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
383 /// about this branch.
384 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
385 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
388 // isPredicable - Return true if this instruction has a predicate operand that
389 // controls execution. It may be set to 'always', or may be set to other
390 /// values. There are various methods in TargetInstrInfo that can be used to
391 /// control and modify the predicate in this instruction.
392 bool isPredicable(QueryType Type = AllInBundle) const {
393 // If it's a bundle than all bundled instructions must be predicable for this
395 return hasProperty(MCID::Predicable, Type);
398 /// isCompare - Return true if this instruction is a comparison.
399 bool isCompare(QueryType Type = IgnoreBundle) const {
400 return hasProperty(MCID::Compare, Type);
403 /// isMoveImmediate - Return true if this instruction is a move immediate
404 /// (including conditional moves) instruction.
405 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
406 return hasProperty(MCID::MoveImm, Type);
409 /// isBitcast - Return true if this instruction is a bitcast instruction.
411 bool isBitcast(QueryType Type = IgnoreBundle) const {
412 return hasProperty(MCID::Bitcast, Type);
415 /// isNotDuplicable - Return true if this instruction cannot be safely
416 /// duplicated. For example, if the instruction has a unique labels attached
417 /// to it, duplicating it would cause multiple definition errors.
418 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
419 return hasProperty(MCID::NotDuplicable, Type);
422 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
423 /// which must be filled by the code generator.
424 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
425 return hasProperty(MCID::DelaySlot, Type);
428 /// canFoldAsLoad - Return true for instructions that can be folded as
429 /// memory operands in other instructions. The most common use for this
430 /// is instructions that are simple loads from memory that don't modify
431 /// the loaded value in any way, but it can also be used for instructions
432 /// that can be expressed as constant-pool loads, such as V_SETALLONES
433 /// on x86, to allow them to be folded when it is beneficial.
434 /// This should only be set on instructions that return a value in their
435 /// only virtual register definition.
436 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
437 return hasProperty(MCID::FoldableAsLoad, Type);
440 //===--------------------------------------------------------------------===//
441 // Side Effect Analysis
442 //===--------------------------------------------------------------------===//
444 /// mayLoad - Return true if this instruction could possibly read memory.
445 /// Instructions with this flag set are not necessarily simple load
446 /// instructions, they may load a value and modify it, for example.
447 bool mayLoad(QueryType Type = AnyInBundle) const {
448 return hasProperty(MCID::MayLoad, Type);
452 /// mayStore - Return true if this instruction could possibly modify memory.
453 /// Instructions with this flag set are not necessarily simple store
454 /// instructions, they may store a modified value based on their operands, or
455 /// may not actually modify anything, for example.
456 bool mayStore(QueryType Type = AnyInBundle) const {
457 return hasProperty(MCID::MayStore, Type);
460 //===--------------------------------------------------------------------===//
461 // Flags that indicate whether an instruction can be modified by a method.
462 //===--------------------------------------------------------------------===//
464 /// isCommutable - Return true if this may be a 2- or 3-address
465 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
466 /// result if Y and Z are exchanged. If this flag is set, then the
467 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
470 /// Note that this flag may be set on instructions that are only commutable
471 /// sometimes. In these cases, the call to commuteInstruction will fail.
472 /// Also note that some instructions require non-trivial modification to
474 bool isCommutable(QueryType Type = IgnoreBundle) const {
475 return hasProperty(MCID::Commutable, Type);
478 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
479 /// which can be changed into a 3-address instruction if needed. Doing this
480 /// transformation can be profitable in the register allocator, because it
481 /// means that the instruction can use a 2-address form if possible, but
482 /// degrade into a less efficient form if the source and dest register cannot
483 /// be assigned to the same register. For example, this allows the x86
484 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
485 /// is the same speed as the shift but has bigger code size.
487 /// If this returns true, then the target must implement the
488 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
489 /// is allowed to fail if the transformation isn't valid for this specific
490 /// instruction (e.g. shl reg, 4 on x86).
492 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
493 return hasProperty(MCID::ConvertibleTo3Addr, Type);
496 /// usesCustomInsertionHook - Return true if this instruction requires
497 /// custom insertion support when the DAG scheduler is inserting it into a
498 /// machine basic block. If this is true for the instruction, it basically
499 /// means that it is a pseudo instruction used at SelectionDAG time that is
500 /// expanded out into magic code by the target when MachineInstrs are formed.
502 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
503 /// is used to insert this into the MachineBasicBlock.
504 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
505 return hasProperty(MCID::UsesCustomInserter, Type);
508 /// hasPostISelHook - Return true if this instruction requires *adjustment*
509 /// after instruction selection by calling a target hook. For example, this
510 /// can be used to fill in ARM 's' optional operand depending on whether
511 /// the conditional flag register is used.
512 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
513 return hasProperty(MCID::HasPostISelHook, Type);
516 /// isRematerializable - Returns true if this instruction is a candidate for
517 /// remat. This flag is deprecated, please don't use it anymore. If this
518 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
519 /// verify the instruction is really rematable.
520 bool isRematerializable(QueryType Type = AllInBundle) const {
521 // It's only possible to re-mat a bundle if all bundled instructions are
522 // re-materializable.
523 return hasProperty(MCID::Rematerializable, Type);
526 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
527 /// less) than a move instruction. This is useful during certain types of
528 /// optimizations (e.g., remat during two-address conversion or machine licm)
529 /// where we would like to remat or hoist the instruction, but not if it costs
530 /// more than moving the instruction into the appropriate register. Note, we
531 /// are not marking copies from and to the same register class with this flag.
532 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
533 // Only returns true for a bundle if all bundled instructions are cheap.
534 // FIXME: This probably requires a target hook.
535 return hasProperty(MCID::CheapAsAMove, Type);
538 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
539 /// have special register allocation requirements that are not captured by the
540 /// operand register classes. e.g. ARM::STRD's two source registers must be an
541 /// even / odd pair, ARM::STM registers have to be in ascending order.
542 /// Post-register allocation passes should not attempt to change allocations
543 /// for sources of instructions with this flag.
544 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
545 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
548 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
549 /// have special register allocation requirements that are not captured by the
550 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
551 /// even / odd pair, ARM::LDM registers have to be in ascending order.
552 /// Post-register allocation passes should not attempt to change allocations
553 /// for definitions of instructions with this flag.
554 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
555 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
560 CheckDefs, // Check all operands for equality
561 CheckKillDead, // Check all operands including kill / dead markers
562 IgnoreDefs, // Ignore all definitions
563 IgnoreVRegDefs // Ignore virtual register definitions
566 /// isIdenticalTo - Return true if this instruction is identical to (same
567 /// opcode and same operands as) the specified instruction.
568 bool isIdenticalTo(const MachineInstr *Other,
569 MICheckType Check = CheckDefs) const;
571 /// removeFromParent - This method unlinks 'this' from the containing basic
572 /// block, and returns it, but does not delete it.
573 MachineInstr *removeFromParent();
575 /// eraseFromParent - This method unlinks 'this' from the containing basic
576 /// block and deletes it.
577 void eraseFromParent();
579 /// isLabel - Returns true if the MachineInstr represents a label.
581 bool isLabel() const {
582 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
583 getOpcode() == TargetOpcode::EH_LABEL ||
584 getOpcode() == TargetOpcode::GC_LABEL;
587 bool isPrologLabel() const {
588 return getOpcode() == TargetOpcode::PROLOG_LABEL;
590 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
591 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
592 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
594 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
595 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
596 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
597 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
598 bool isStackAligningInlineAsm() const;
599 bool isInsertSubreg() const {
600 return getOpcode() == TargetOpcode::INSERT_SUBREG;
602 bool isSubregToReg() const {
603 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
605 bool isRegSequence() const {
606 return getOpcode() == TargetOpcode::REG_SEQUENCE;
608 bool isBundle() const {
609 return getOpcode() == TargetOpcode::BUNDLE;
611 bool isCopy() const {
612 return getOpcode() == TargetOpcode::COPY;
614 bool isFullCopy() const {
615 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
618 /// isCopyLike - Return true if the instruction behaves like a copy.
619 /// This does not include native copy instructions.
620 bool isCopyLike() const {
621 return isCopy() || isSubregToReg();
624 /// isIdentityCopy - Return true is the instruction is an identity copy.
625 bool isIdentityCopy() const {
626 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
627 getOperand(0).getSubReg() == getOperand(1).getSubReg();
630 /// getBundleSize - Return the number of instructions inside the MI bundle.
631 unsigned getBundleSize() const;
633 /// readsRegister - Return true if the MachineInstr reads the specified
634 /// register. If TargetRegisterInfo is passed, then it also checks if there
635 /// is a read of a super-register.
636 /// This does not count partial redefines of virtual registers as reads:
638 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
639 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
642 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
643 /// virtual register. Take into account that a partial define is a
644 /// read-modify-write operation.
645 bool readsVirtualRegister(unsigned Reg) const {
646 return readsWritesVirtualRegister(Reg).first;
649 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
650 /// indicating if this instruction reads or writes Reg. This also considers
652 /// If Ops is not null, all operand indices for Reg are added.
653 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
654 SmallVectorImpl<unsigned> *Ops = 0) const;
656 /// killsRegister - Return true if the MachineInstr kills the specified
657 /// register. If TargetRegisterInfo is passed, then it also checks if there is
658 /// a kill of a super-register.
659 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
660 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
663 /// definesRegister - Return true if the MachineInstr fully defines the
664 /// specified register. If TargetRegisterInfo is passed, then it also checks
665 /// if there is a def of a super-register.
666 /// NOTE: It's ignoring subreg indices on virtual registers.
667 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
668 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
671 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
672 /// or partially define) the specified register.
673 /// NOTE: It's ignoring subreg indices on virtual registers.
674 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
675 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
678 /// registerDefIsDead - Returns true if the register is dead in this machine
679 /// instruction. If TargetRegisterInfo is passed, then it also checks
680 /// if there is a dead def of a super-register.
681 bool registerDefIsDead(unsigned Reg,
682 const TargetRegisterInfo *TRI = NULL) const {
683 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
686 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
687 /// the specific register or -1 if it is not found. It further tightens
688 /// the search criteria to a use that kills the register if isKill is true.
689 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
690 const TargetRegisterInfo *TRI = NULL) const;
692 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
693 /// a pointer to the MachineOperand rather than an index.
694 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
695 const TargetRegisterInfo *TRI = NULL) {
696 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
697 return (Idx == -1) ? NULL : &getOperand(Idx);
700 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
701 /// the specified register or -1 if it is not found. If isDead is true, defs
702 /// that are not dead are skipped. If Overlap is true, then it also looks for
703 /// defs that merely overlap the specified register. If TargetRegisterInfo is
704 /// non-null, then it also checks if there is a def of a super-register.
705 /// This may also return a register mask operand when Overlap is true.
706 int findRegisterDefOperandIdx(unsigned Reg,
707 bool isDead = false, bool Overlap = false,
708 const TargetRegisterInfo *TRI = NULL) const;
710 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
711 /// a pointer to the MachineOperand rather than an index.
712 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
713 const TargetRegisterInfo *TRI = NULL) {
714 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
715 return (Idx == -1) ? NULL : &getOperand(Idx);
718 /// findFirstPredOperandIdx() - Find the index of the first operand in the
719 /// operand list that is used to represent the predicate. It returns -1 if
721 int findFirstPredOperandIdx() const;
723 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
724 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
725 /// getOperand(OpIdx) does not belong to an inline asm operand group.
727 /// If GroupNo is not NULL, it will receive the number of the operand group
728 /// containing OpIdx.
730 /// The flag operand is an immediate that can be decoded with methods like
731 /// InlineAsm::hasRegClassConstraint().
733 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
735 /// getRegClassConstraint - Compute the static register class constraint for
736 /// operand OpIdx. For normal instructions, this is derived from the
737 /// MCInstrDesc. For inline assembly it is derived from the flag words.
739 /// Returns NULL if the static register classs constraint cannot be
742 const TargetRegisterClass*
743 getRegClassConstraint(unsigned OpIdx,
744 const TargetInstrInfo *TII,
745 const TargetRegisterInfo *TRI) const;
747 /// isRegTiedToUseOperand - Given the index of a register def operand,
748 /// check if the register def is tied to a source operand, due to either
749 /// two-address elimination or inline assembly constraints. Returns the
750 /// first tied use operand index by reference if UseOpIdx is not null.
751 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
753 /// isRegTiedToDefOperand - Return true if the use operand of the specified
754 /// index is tied to an def operand. It also returns the def operand index by
755 /// reference if DefOpIdx is not null.
756 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
758 /// clearKillInfo - Clears kill flags on all operands.
760 void clearKillInfo();
762 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
764 void copyKillDeadInfo(const MachineInstr *MI);
766 /// copyPredicates - Copies predicate operand(s) from MI.
767 void copyPredicates(const MachineInstr *MI);
769 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
770 /// properly composing subreg indices where necessary.
771 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
772 const TargetRegisterInfo &RegInfo);
774 /// addRegisterKilled - We have determined MI kills a register. Look for the
775 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
776 /// add a implicit operand if it's not found. Returns true if the operand
777 /// exists / is added.
778 bool addRegisterKilled(unsigned IncomingReg,
779 const TargetRegisterInfo *RegInfo,
780 bool AddIfNotFound = false);
782 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
783 /// provided, this includes super-register kills.
784 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
786 /// addRegisterDead - We have determined MI defined a register without a use.
787 /// Look for the operand that defines it and mark it as IsDead. If
788 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
789 /// true if the operand exists / is added.
790 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
791 bool AddIfNotFound = false);
793 /// addRegisterDefined - We have determined MI defines a register. Make sure
794 /// there is an operand defining Reg.
795 void addRegisterDefined(unsigned IncomingReg,
796 const TargetRegisterInfo *RegInfo = 0);
798 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
799 /// dead except those in the UsedRegs list.
801 /// On instructions with register mask operands, also add implicit-def
802 /// operands for all registers in UsedRegs.
803 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
804 const TargetRegisterInfo &TRI);
806 /// isSafeToMove - Return true if it is safe to move this instruction. If
807 /// SawStore is set to true, it means that there is a store (or call) between
808 /// the instruction's location and its intended destination.
809 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
810 bool &SawStore) const;
812 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
813 /// instruction which defined the specified register instead of copying it.
814 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
815 unsigned DstReg) const;
817 /// hasVolatileMemoryRef - Return true if this instruction may have a
818 /// volatile memory reference, or if the information describing the
819 /// memory reference is not available. Return false if it is known to
820 /// have no volatile memory references.
821 bool hasVolatileMemoryRef() const;
823 /// isInvariantLoad - Return true if this instruction is loading from a
824 /// location whose value is invariant across the function. For example,
825 /// loading a value from the constant pool or from the argument area of
826 /// a function if it does not change. This should only return true of *all*
827 /// loads the instruction does are invariant (if it does multiple loads).
828 bool isInvariantLoad(AliasAnalysis *AA) const;
830 /// isConstantValuePHI - If the specified instruction is a PHI that always
831 /// merges together the same virtual register, return the register, otherwise
833 unsigned isConstantValuePHI() const;
835 /// hasUnmodeledSideEffects - Return true if this instruction has side
836 /// effects that are not modeled by mayLoad / mayStore, etc.
837 /// For all instructions, the property is encoded in MCInstrDesc::Flags
838 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
839 /// INLINEASM instruction, in which case the side effect property is encoded
840 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
842 bool hasUnmodeledSideEffects() const;
844 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
846 bool allDefsAreDead() const;
848 /// copyImplicitOps - Copy implicit register operands from specified
849 /// instruction to this instruction.
850 void copyImplicitOps(const MachineInstr *MI);
855 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
858 //===--------------------------------------------------------------------===//
859 // Accessors used to build up machine instructions.
861 /// addOperand - Add the specified operand to the instruction. If it is an
862 /// implicit operand, it is added to the end of the operand list. If it is
863 /// an explicit operand it is added at the end of the explicit operand list
864 /// (before the first implicit operand).
865 void addOperand(const MachineOperand &Op);
867 /// setDesc - Replace the instruction descriptor (thus opcode) of
868 /// the current instruction with a new one.
870 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
872 /// setDebugLoc - Replace current source information with new such.
873 /// Avoid using this, the constructor argument is preferable.
875 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
877 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
878 /// fewer operand than it started with.
880 void RemoveOperand(unsigned i);
882 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
883 /// This function should be used only occasionally. The setMemRefs function
884 /// is the primary method for setting up a MachineInstr's MemRefs list.
885 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
887 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
888 /// list. This does not transfer ownership.
889 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
890 MemRefs = NewMemRefs;
891 MemRefsEnd = NewMemRefsEnd;
895 /// getRegInfo - If this instruction is embedded into a MachineFunction,
896 /// return the MachineRegisterInfo object for the current function, otherwise
898 MachineRegisterInfo *getRegInfo();
900 /// addImplicitDefUseOperands - Add all implicit def and use operands to
901 /// this instruction.
902 void addImplicitDefUseOperands();
904 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
905 /// this instruction from their respective use lists. This requires that the
906 /// operands already be on their use lists.
907 void RemoveRegOperandsFromUseLists();
909 /// AddRegOperandsToUseLists - Add all of the register operands in
910 /// this instruction from their respective use lists. This requires that the
911 /// operands not be on their use lists yet.
912 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
915 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
916 /// MachineInstr* by *value* of the instruction rather than by pointer value.
917 /// The hashing and equality testing functions ignore definitions so this is
918 /// useful for CSE, etc.
919 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
920 static inline MachineInstr *getEmptyKey() {
924 static inline MachineInstr *getTombstoneKey() {
925 return reinterpret_cast<MachineInstr*>(-1);
928 static unsigned getHashValue(const MachineInstr* const &MI);
930 static bool isEqual(const MachineInstr* const &LHS,
931 const MachineInstr* const &RHS) {
932 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
933 LHS == getEmptyKey() || LHS == getTombstoneKey())
935 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
939 //===----------------------------------------------------------------------===//
942 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
947 } // End llvm namespace