1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/DenseMapInfo.h"
28 #include "llvm/InlineAsm.h"
29 #include "llvm/Support/DebugLoc.h"
34 template <typename T> class SmallVectorImpl;
36 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
39 class MachineFunction;
40 class MachineMemOperand;
42 //===----------------------------------------------------------------------===//
43 /// MachineInstr - Representation of each machine instruction.
45 class MachineInstr : public ilist_node<MachineInstr> {
47 typedef MachineMemOperand **mmo_iterator;
49 /// Flags to specify different kinds of comments to output in
50 /// assembly code. These flags carry semantic information not
51 /// otherwise easily derivable from the IR text.
59 FrameSetup = 1 << 0, // Instruction is used as a part of
60 // function frame setup code.
61 InsideBundle = 1 << 1, // Instruction is inside a bundle (not
62 // the first MI in a bundle)
63 MayLoad = 1 << 2, // Instruction could possibly read memory.
64 MayStore = 1 << 3 // Instruction could possibly modify memory.
67 const MCInstrDesc *MCID; // Instruction descriptor.
69 uint8_t Flags; // Various bits of additional
70 // information about machine
73 uint8_t AsmPrinterFlags; // Various bits of information used by
74 // the AsmPrinter to emit helpful
75 // comments. This is *not* semantic
76 // information. Do not use this for
77 // anything other than to convey comment
78 // information to AsmPrinter.
80 uint16_t NumMemRefs; // information on memory references
83 std::vector<MachineOperand> Operands; // the operands
84 MachineBasicBlock *Parent; // Pointer to the owning basic block.
85 DebugLoc debugLoc; // Source line information.
87 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
88 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
90 // Intrusive list support
91 friend struct ilist_traits<MachineInstr>;
92 friend struct ilist_traits<MachineBasicBlock>;
93 void setParent(MachineBasicBlock *P) { Parent = P; }
95 /// MachineInstr ctor - This constructor creates a copy of the given
96 /// MachineInstr in the given MachineFunction.
97 MachineInstr(MachineFunction &, const MachineInstr &);
99 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
100 /// MCID NULL and no operands.
103 /// MachineInstr ctor - This constructor create a MachineInstr and add the
104 /// implicit operands. It reserves space for number of operands specified by
105 /// MCInstrDesc. An explicit DebugLoc is supplied.
106 MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = false);
108 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
109 /// the MachineInstr is created and added to the end of the specified basic
111 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
112 const MCInstrDesc &MCID);
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
164 void setFlags(unsigned flags) {
168 /// clearFlag - Clear a MI flag.
169 void clearFlag(MIFlag Flag) {
170 Flags &= ~((uint8_t)Flag);
173 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
176 /// A bundle looks like this before it's finalized:
188 /// In this case, the first MI starts a bundle but is not inside a bundle, the
189 /// next 2 MIs are considered "inside" the bundle.
191 /// After a bundle is finalized, it looks like this:
207 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
208 /// a bundle, but the next three MIs are.
209 bool isInsideBundle() const {
210 return getFlag(InsideBundle);
213 /// setIsInsideBundle - Set InsideBundle bit.
215 void setIsInsideBundle(bool Val = true) {
217 setFlag(InsideBundle);
219 clearFlag(InsideBundle);
222 /// isBundled - Return true if this instruction part of a bundle. This is true
223 /// if either itself or its following instruction is marked "InsideBundle".
224 bool isBundled() const;
226 /// getDebugLoc - Returns the debug location id of this MachineInstr.
228 DebugLoc getDebugLoc() const { return debugLoc; }
230 /// emitError - Emit an error referring to the source location of this
231 /// instruction. This should only be used for inline assembly that is somehow
232 /// impossible to compile. Other errors should have been handled much
235 /// If this method returns, the caller should try to recover from the error.
237 void emitError(StringRef Msg) const;
239 /// getDesc - Returns the target instruction descriptor of this
241 const MCInstrDesc &getDesc() const { return *MCID; }
243 /// getOpcode - Returns the opcode of this MachineInstr.
245 int getOpcode() const { return MCID->Opcode; }
247 /// Access to explicit operands of the instruction.
249 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
251 const MachineOperand& getOperand(unsigned i) const {
252 assert(i < getNumOperands() && "getOperand() out of range!");
255 MachineOperand& getOperand(unsigned i) {
256 assert(i < getNumOperands() && "getOperand() out of range!");
260 /// getNumExplicitOperands - Returns the number of non-implicit operands.
262 unsigned getNumExplicitOperands() const;
264 /// iterator/begin/end - Iterate over all operands of a machine instruction.
265 typedef std::vector<MachineOperand>::iterator mop_iterator;
266 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
268 mop_iterator operands_begin() { return Operands.begin(); }
269 mop_iterator operands_end() { return Operands.end(); }
271 const_mop_iterator operands_begin() const { return Operands.begin(); }
272 const_mop_iterator operands_end() const { return Operands.end(); }
274 /// Access to memory operands of the instruction
275 mmo_iterator memoperands_begin() const { return MemRefs; }
276 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
277 bool memoperands_empty() const { return NumMemRefs == 0; }
279 /// hasOneMemOperand - Return true if this instruction has exactly one
280 /// MachineMemOperand.
281 bool hasOneMemOperand() const {
282 return NumMemRefs == 1;
285 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
286 /// queries but they are bundle aware.
289 IgnoreBundle, // Ignore bundles
290 AnyInBundle, // Return true if any instruction in bundle has property
291 AllInBundle // Return true if all instructions in bundle have property
294 /// hasProperty - Return true if the instruction (or in the case of a bundle,
295 /// the instructions inside the bundle) has the specified property.
296 /// The first argument is the property being queried.
297 /// The second argument indicates whether the query should look inside
298 /// instruction bundles.
299 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
300 // Inline the fast path.
301 if (Type == IgnoreBundle || !isBundle())
302 return getDesc().getFlags() & (1 << MCFlag);
304 // If we have a bundle, take the slow path.
305 return hasPropertyInBundle(1 << MCFlag, Type);
308 /// isVariadic - Return true if this instruction can have a variable number of
309 /// operands. In this case, the variable operands will be after the normal
310 /// operands but before the implicit definitions and uses (if any are
312 bool isVariadic(QueryType Type = IgnoreBundle) const {
313 return hasProperty(MCID::Variadic, Type);
316 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
317 /// ARM instructions which can set condition code if 's' bit is set.
318 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
319 return hasProperty(MCID::HasOptionalDef, Type);
322 /// isPseudo - Return true if this is a pseudo instruction that doesn't
323 /// correspond to a real machine instruction.
325 bool isPseudo(QueryType Type = IgnoreBundle) const {
326 return hasProperty(MCID::Pseudo, Type);
329 bool isReturn(QueryType Type = AnyInBundle) const {
330 return hasProperty(MCID::Return, Type);
333 bool isCall(QueryType Type = AnyInBundle) const {
334 return hasProperty(MCID::Call, Type);
337 /// isBarrier - Returns true if the specified instruction stops control flow
338 /// from executing the instruction immediately following it. Examples include
339 /// unconditional branches and return instructions.
340 bool isBarrier(QueryType Type = AnyInBundle) const {
341 return hasProperty(MCID::Barrier, Type);
344 /// isTerminator - Returns true if this instruction part of the terminator for
345 /// a basic block. Typically this is things like return and branch
348 /// Various passes use this to insert code into the bottom of a basic block,
349 /// but before control flow occurs.
350 bool isTerminator(QueryType Type = AnyInBundle) const {
351 return hasProperty(MCID::Terminator, Type);
354 /// isBranch - Returns true if this is a conditional, unconditional, or
355 /// indirect branch. Predicates below can be used to discriminate between
356 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
357 /// get more information.
358 bool isBranch(QueryType Type = AnyInBundle) const {
359 return hasProperty(MCID::Branch, Type);
362 /// isIndirectBranch - Return true if this is an indirect branch, such as a
363 /// branch through a register.
364 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
365 return hasProperty(MCID::IndirectBranch, Type);
368 /// isConditionalBranch - Return true if this is a branch which may fall
369 /// through to the next instruction or may transfer control flow to some other
370 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
371 /// information about this branch.
372 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
373 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
376 /// isUnconditionalBranch - Return true if this is a branch which always
377 /// transfers control flow to some other block. The
378 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
379 /// about this branch.
380 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
381 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
384 // isPredicable - Return true if this instruction has a predicate operand that
385 // controls execution. It may be set to 'always', or may be set to other
386 /// values. There are various methods in TargetInstrInfo that can be used to
387 /// control and modify the predicate in this instruction.
388 bool isPredicable(QueryType Type = AllInBundle) const {
389 // If it's a bundle than all bundled instructions must be predicable for this
391 return hasProperty(MCID::Predicable, Type);
394 /// isCompare - Return true if this instruction is a comparison.
395 bool isCompare(QueryType Type = IgnoreBundle) const {
396 return hasProperty(MCID::Compare, Type);
399 /// isMoveImmediate - Return true if this instruction is a move immediate
400 /// (including conditional moves) instruction.
401 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
402 return hasProperty(MCID::MoveImm, Type);
405 /// isBitcast - Return true if this instruction is a bitcast instruction.
407 bool isBitcast(QueryType Type = IgnoreBundle) const {
408 return hasProperty(MCID::Bitcast, Type);
411 /// isSelect - Return true if this instruction is a select instruction.
413 bool isSelect(QueryType Type = IgnoreBundle) const {
414 return hasProperty(MCID::Select, Type);
417 /// isNotDuplicable - Return true if this instruction cannot be safely
418 /// duplicated. For example, if the instruction has a unique labels attached
419 /// to it, duplicating it would cause multiple definition errors.
420 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
421 return hasProperty(MCID::NotDuplicable, Type);
424 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
425 /// which must be filled by the code generator.
426 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
427 return hasProperty(MCID::DelaySlot, Type);
430 /// canFoldAsLoad - Return true for instructions that can be folded as
431 /// memory operands in other instructions. The most common use for this
432 /// is instructions that are simple loads from memory that don't modify
433 /// the loaded value in any way, but it can also be used for instructions
434 /// that can be expressed as constant-pool loads, such as V_SETALLONES
435 /// on x86, to allow them to be folded when it is beneficial.
436 /// This should only be set on instructions that return a value in their
437 /// only virtual register definition.
438 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
439 return hasProperty(MCID::FoldableAsLoad, Type);
442 //===--------------------------------------------------------------------===//
443 // Side Effect Analysis
444 //===--------------------------------------------------------------------===//
446 /// mayLoad - Return true if this instruction could possibly read memory.
447 /// Instructions with this flag set are not necessarily simple load
448 /// instructions, they may load a value and modify it, for example.
449 bool mayLoad(QueryType Type = AnyInBundle) const {
450 return hasProperty(MCID::MayLoad, Type) || (Flags & MayLoad);
454 /// mayStore - Return true if this instruction could possibly modify memory.
455 /// Instructions with this flag set are not necessarily simple store
456 /// instructions, they may store a modified value based on their operands, or
457 /// may not actually modify anything, for example.
458 bool mayStore(QueryType Type = AnyInBundle) const {
459 return hasProperty(MCID::MayStore, Type) || (Flags & MayStore);
462 //===--------------------------------------------------------------------===//
463 // Flags that indicate whether an instruction can be modified by a method.
464 //===--------------------------------------------------------------------===//
466 /// isCommutable - Return true if this may be a 2- or 3-address
467 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
468 /// result if Y and Z are exchanged. If this flag is set, then the
469 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
472 /// Note that this flag may be set on instructions that are only commutable
473 /// sometimes. In these cases, the call to commuteInstruction will fail.
474 /// Also note that some instructions require non-trivial modification to
476 bool isCommutable(QueryType Type = IgnoreBundle) const {
477 return hasProperty(MCID::Commutable, Type);
480 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
481 /// which can be changed into a 3-address instruction if needed. Doing this
482 /// transformation can be profitable in the register allocator, because it
483 /// means that the instruction can use a 2-address form if possible, but
484 /// degrade into a less efficient form if the source and dest register cannot
485 /// be assigned to the same register. For example, this allows the x86
486 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
487 /// is the same speed as the shift but has bigger code size.
489 /// If this returns true, then the target must implement the
490 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
491 /// is allowed to fail if the transformation isn't valid for this specific
492 /// instruction (e.g. shl reg, 4 on x86).
494 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
495 return hasProperty(MCID::ConvertibleTo3Addr, Type);
498 /// usesCustomInsertionHook - Return true if this instruction requires
499 /// custom insertion support when the DAG scheduler is inserting it into a
500 /// machine basic block. If this is true for the instruction, it basically
501 /// means that it is a pseudo instruction used at SelectionDAG time that is
502 /// expanded out into magic code by the target when MachineInstrs are formed.
504 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
505 /// is used to insert this into the MachineBasicBlock.
506 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
507 return hasProperty(MCID::UsesCustomInserter, Type);
510 /// hasPostISelHook - Return true if this instruction requires *adjustment*
511 /// after instruction selection by calling a target hook. For example, this
512 /// can be used to fill in ARM 's' optional operand depending on whether
513 /// the conditional flag register is used.
514 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
515 return hasProperty(MCID::HasPostISelHook, Type);
518 /// isRematerializable - Returns true if this instruction is a candidate for
519 /// remat. This flag is deprecated, please don't use it anymore. If this
520 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
521 /// verify the instruction is really rematable.
522 bool isRematerializable(QueryType Type = AllInBundle) const {
523 // It's only possible to re-mat a bundle if all bundled instructions are
524 // re-materializable.
525 return hasProperty(MCID::Rematerializable, Type);
528 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
529 /// less) than a move instruction. This is useful during certain types of
530 /// optimizations (e.g., remat during two-address conversion or machine licm)
531 /// where we would like to remat or hoist the instruction, but not if it costs
532 /// more than moving the instruction into the appropriate register. Note, we
533 /// are not marking copies from and to the same register class with this flag.
534 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
535 // Only returns true for a bundle if all bundled instructions are cheap.
536 // FIXME: This probably requires a target hook.
537 return hasProperty(MCID::CheapAsAMove, Type);
540 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
541 /// have special register allocation requirements that are not captured by the
542 /// operand register classes. e.g. ARM::STRD's two source registers must be an
543 /// even / odd pair, ARM::STM registers have to be in ascending order.
544 /// Post-register allocation passes should not attempt to change allocations
545 /// for sources of instructions with this flag.
546 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
547 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
550 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
551 /// have special register allocation requirements that are not captured by the
552 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
553 /// even / odd pair, ARM::LDM registers have to be in ascending order.
554 /// Post-register allocation passes should not attempt to change allocations
555 /// for definitions of instructions with this flag.
556 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
557 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
562 CheckDefs, // Check all operands for equality
563 CheckKillDead, // Check all operands including kill / dead markers
564 IgnoreDefs, // Ignore all definitions
565 IgnoreVRegDefs // Ignore virtual register definitions
568 /// isIdenticalTo - Return true if this instruction is identical to (same
569 /// opcode and same operands as) the specified instruction.
570 bool isIdenticalTo(const MachineInstr *Other,
571 MICheckType Check = CheckDefs) const;
573 /// removeFromParent - This method unlinks 'this' from the containing basic
574 /// block, and returns it, but does not delete it.
575 MachineInstr *removeFromParent();
577 /// eraseFromParent - This method unlinks 'this' from the containing basic
578 /// block and deletes it.
579 void eraseFromParent();
581 /// isLabel - Returns true if the MachineInstr represents a label.
583 bool isLabel() const {
584 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
585 getOpcode() == TargetOpcode::EH_LABEL ||
586 getOpcode() == TargetOpcode::GC_LABEL;
589 bool isPrologLabel() const {
590 return getOpcode() == TargetOpcode::PROLOG_LABEL;
592 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
593 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
594 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
596 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
597 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
598 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
599 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
600 bool isStackAligningInlineAsm() const;
601 InlineAsm::AsmDialect getInlineAsmDialect() const;
602 bool isInsertSubreg() const {
603 return getOpcode() == TargetOpcode::INSERT_SUBREG;
605 bool isSubregToReg() const {
606 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
608 bool isRegSequence() const {
609 return getOpcode() == TargetOpcode::REG_SEQUENCE;
611 bool isBundle() const {
612 return getOpcode() == TargetOpcode::BUNDLE;
614 bool isCopy() const {
615 return getOpcode() == TargetOpcode::COPY;
617 bool isFullCopy() const {
618 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
621 /// isCopyLike - Return true if the instruction behaves like a copy.
622 /// This does not include native copy instructions.
623 bool isCopyLike() const {
624 return isCopy() || isSubregToReg();
627 /// isIdentityCopy - Return true is the instruction is an identity copy.
628 bool isIdentityCopy() const {
629 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
630 getOperand(0).getSubReg() == getOperand(1).getSubReg();
633 /// isTransient - Return true if this is a transient instruction that is
634 /// either very likely to be eliminated during register allocation (such as
635 /// copy-like instructions), or if this instruction doesn't have an
636 /// execution-time cost.
637 bool isTransient() const {
638 switch(getOpcode()) {
639 default: return false;
640 // Copy-like instructions are usually eliminated during register allocation.
641 case TargetOpcode::PHI:
642 case TargetOpcode::COPY:
643 case TargetOpcode::INSERT_SUBREG:
644 case TargetOpcode::SUBREG_TO_REG:
645 case TargetOpcode::REG_SEQUENCE:
646 // Pseudo-instructions that don't produce any real output.
647 case TargetOpcode::IMPLICIT_DEF:
648 case TargetOpcode::KILL:
649 case TargetOpcode::PROLOG_LABEL:
650 case TargetOpcode::EH_LABEL:
651 case TargetOpcode::GC_LABEL:
652 case TargetOpcode::DBG_VALUE:
657 /// getBundleSize - Return the number of instructions inside the MI bundle.
658 unsigned getBundleSize() const;
660 /// readsRegister - Return true if the MachineInstr reads the specified
661 /// register. If TargetRegisterInfo is passed, then it also checks if there
662 /// is a read of a super-register.
663 /// This does not count partial redefines of virtual registers as reads:
665 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
666 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
669 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
670 /// virtual register. Take into account that a partial define is a
671 /// read-modify-write operation.
672 bool readsVirtualRegister(unsigned Reg) const {
673 return readsWritesVirtualRegister(Reg).first;
676 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
677 /// indicating if this instruction reads or writes Reg. This also considers
679 /// If Ops is not null, all operand indices for Reg are added.
680 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
681 SmallVectorImpl<unsigned> *Ops = 0) const;
683 /// killsRegister - Return true if the MachineInstr kills the specified
684 /// register. If TargetRegisterInfo is passed, then it also checks if there is
685 /// a kill of a super-register.
686 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
687 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
690 /// definesRegister - Return true if the MachineInstr fully defines the
691 /// specified register. If TargetRegisterInfo is passed, then it also checks
692 /// if there is a def of a super-register.
693 /// NOTE: It's ignoring subreg indices on virtual registers.
694 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
695 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
698 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
699 /// or partially define) the specified register.
700 /// NOTE: It's ignoring subreg indices on virtual registers.
701 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
702 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
705 /// registerDefIsDead - Returns true if the register is dead in this machine
706 /// instruction. If TargetRegisterInfo is passed, then it also checks
707 /// if there is a dead def of a super-register.
708 bool registerDefIsDead(unsigned Reg,
709 const TargetRegisterInfo *TRI = NULL) const {
710 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
713 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
714 /// the specific register or -1 if it is not found. It further tightens
715 /// the search criteria to a use that kills the register if isKill is true.
716 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
717 const TargetRegisterInfo *TRI = NULL) const;
719 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
720 /// a pointer to the MachineOperand rather than an index.
721 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
722 const TargetRegisterInfo *TRI = NULL) {
723 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
724 return (Idx == -1) ? NULL : &getOperand(Idx);
727 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
728 /// the specified register or -1 if it is not found. If isDead is true, defs
729 /// that are not dead are skipped. If Overlap is true, then it also looks for
730 /// defs that merely overlap the specified register. If TargetRegisterInfo is
731 /// non-null, then it also checks if there is a def of a super-register.
732 /// This may also return a register mask operand when Overlap is true.
733 int findRegisterDefOperandIdx(unsigned Reg,
734 bool isDead = false, bool Overlap = false,
735 const TargetRegisterInfo *TRI = NULL) const;
737 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
738 /// a pointer to the MachineOperand rather than an index.
739 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
740 const TargetRegisterInfo *TRI = NULL) {
741 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
742 return (Idx == -1) ? NULL : &getOperand(Idx);
745 /// findFirstPredOperandIdx() - Find the index of the first operand in the
746 /// operand list that is used to represent the predicate. It returns -1 if
748 int findFirstPredOperandIdx() const;
750 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
751 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
752 /// getOperand(OpIdx) does not belong to an inline asm operand group.
754 /// If GroupNo is not NULL, it will receive the number of the operand group
755 /// containing OpIdx.
757 /// The flag operand is an immediate that can be decoded with methods like
758 /// InlineAsm::hasRegClassConstraint().
760 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
762 /// getRegClassConstraint - Compute the static register class constraint for
763 /// operand OpIdx. For normal instructions, this is derived from the
764 /// MCInstrDesc. For inline assembly it is derived from the flag words.
766 /// Returns NULL if the static register classs constraint cannot be
769 const TargetRegisterClass*
770 getRegClassConstraint(unsigned OpIdx,
771 const TargetInstrInfo *TII,
772 const TargetRegisterInfo *TRI) const;
774 /// tieOperands - Add a tie between the register operands at DefIdx and
775 /// UseIdx. The tie will cause the register allocator to ensure that the two
776 /// operands are assigned the same physical register.
778 /// Tied operands are managed automatically for explicit operands in the
779 /// MCInstrDesc. This method is for exceptional cases like inline asm.
780 void tieOperands(unsigned DefIdx, unsigned UseIdx);
782 /// findTiedOperandIdx - Given the index of a tied register operand, find the
783 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
784 /// index of the tied operand which must exist.
785 unsigned findTiedOperandIdx(unsigned OpIdx) const;
787 /// isRegTiedToUseOperand - Given the index of a register def operand,
788 /// check if the register def is tied to a source operand, due to either
789 /// two-address elimination or inline assembly constraints. Returns the
790 /// first tied use operand index by reference if UseOpIdx is not null.
791 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
792 const MachineOperand &MO = getOperand(DefOpIdx);
793 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
796 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
800 /// isRegTiedToDefOperand - Return true if the use operand of the specified
801 /// index is tied to an def operand. It also returns the def operand index by
802 /// reference if DefOpIdx is not null.
803 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
804 const MachineOperand &MO = getOperand(UseOpIdx);
805 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
808 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
812 /// clearKillInfo - Clears kill flags on all operands.
814 void clearKillInfo();
816 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
818 void copyKillDeadInfo(const MachineInstr *MI);
820 /// copyPredicates - Copies predicate operand(s) from MI.
821 void copyPredicates(const MachineInstr *MI);
823 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
824 /// properly composing subreg indices where necessary.
825 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
826 const TargetRegisterInfo &RegInfo);
828 /// addRegisterKilled - We have determined MI kills a register. Look for the
829 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
830 /// add a implicit operand if it's not found. Returns true if the operand
831 /// exists / is added.
832 bool addRegisterKilled(unsigned IncomingReg,
833 const TargetRegisterInfo *RegInfo,
834 bool AddIfNotFound = false);
836 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
837 /// provided, this includes super-register kills.
838 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
840 /// addRegisterDead - We have determined MI defined a register without a use.
841 /// Look for the operand that defines it and mark it as IsDead. If
842 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
843 /// true if the operand exists / is added.
844 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
845 bool AddIfNotFound = false);
847 /// addRegisterDefined - We have determined MI defines a register. Make sure
848 /// there is an operand defining Reg.
849 void addRegisterDefined(unsigned IncomingReg,
850 const TargetRegisterInfo *RegInfo = 0);
852 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
853 /// dead except those in the UsedRegs list.
855 /// On instructions with register mask operands, also add implicit-def
856 /// operands for all registers in UsedRegs.
857 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
858 const TargetRegisterInfo &TRI);
860 /// isSafeToMove - Return true if it is safe to move this instruction. If
861 /// SawStore is set to true, it means that there is a store (or call) between
862 /// the instruction's location and its intended destination.
863 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
864 bool &SawStore) const;
866 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
867 /// instruction which defined the specified register instead of copying it.
868 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
869 unsigned DstReg) const;
871 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
872 /// or volatile memory reference, or if the information describing the memory
873 /// reference is not available. Return false if it is known to have no
874 /// ordered or volatile memory references.
875 bool hasOrderedMemoryRef() const;
877 /// isInvariantLoad - Return true if this instruction is loading from a
878 /// location whose value is invariant across the function. For example,
879 /// loading a value from the constant pool or from the argument area of
880 /// a function if it does not change. This should only return true of *all*
881 /// loads the instruction does are invariant (if it does multiple loads).
882 bool isInvariantLoad(AliasAnalysis *AA) const;
884 /// isConstantValuePHI - If the specified instruction is a PHI that always
885 /// merges together the same virtual register, return the register, otherwise
887 unsigned isConstantValuePHI() const;
889 /// hasUnmodeledSideEffects - Return true if this instruction has side
890 /// effects that are not modeled by mayLoad / mayStore, etc.
891 /// For all instructions, the property is encoded in MCInstrDesc::Flags
892 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
893 /// INLINEASM instruction, in which case the side effect property is encoded
894 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
896 bool hasUnmodeledSideEffects() const;
898 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
900 bool allDefsAreDead() const;
902 /// copyImplicitOps - Copy implicit register operands from specified
903 /// instruction to this instruction.
904 void copyImplicitOps(const MachineInstr *MI);
909 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
912 //===--------------------------------------------------------------------===//
913 // Accessors used to build up machine instructions.
915 /// addOperand - Add the specified operand to the instruction. If it is an
916 /// implicit operand, it is added to the end of the operand list. If it is
917 /// an explicit operand it is added at the end of the explicit operand list
918 /// (before the first implicit operand).
919 void addOperand(const MachineOperand &Op);
921 /// setDesc - Replace the instruction descriptor (thus opcode) of
922 /// the current instruction with a new one.
924 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
926 /// setDebugLoc - Replace current source information with new such.
927 /// Avoid using this, the constructor argument is preferable.
929 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
931 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
932 /// fewer operand than it started with.
934 void RemoveOperand(unsigned i);
936 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
937 /// This function should be used only occasionally. The setMemRefs function
938 /// is the primary method for setting up a MachineInstr's MemRefs list.
939 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
941 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
942 /// list. This does not transfer ownership.
943 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
944 MemRefs = NewMemRefs;
945 NumMemRefs = NewMemRefsEnd - NewMemRefs;
949 /// getRegInfo - If this instruction is embedded into a MachineFunction,
950 /// return the MachineRegisterInfo object for the current function, otherwise
952 MachineRegisterInfo *getRegInfo();
954 /// untieRegOperand - Break any tie involving OpIdx.
955 void untieRegOperand(unsigned OpIdx) {
956 MachineOperand &MO = getOperand(OpIdx);
957 if (MO.isReg() && MO.isTied()) {
958 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
963 /// addImplicitDefUseOperands - Add all implicit def and use operands to
964 /// this instruction.
965 void addImplicitDefUseOperands();
967 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
968 /// this instruction from their respective use lists. This requires that the
969 /// operands already be on their use lists.
970 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
972 /// AddRegOperandsToUseLists - Add all of the register operands in
973 /// this instruction from their respective use lists. This requires that the
974 /// operands not be on their use lists yet.
975 void AddRegOperandsToUseLists(MachineRegisterInfo&);
977 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
979 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
982 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
983 /// MachineInstr* by *value* of the instruction rather than by pointer value.
984 /// The hashing and equality testing functions ignore definitions so this is
985 /// useful for CSE, etc.
986 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
987 static inline MachineInstr *getEmptyKey() {
991 static inline MachineInstr *getTombstoneKey() {
992 return reinterpret_cast<MachineInstr*>(-1);
995 static unsigned getHashValue(const MachineInstr* const &MI);
997 static bool isEqual(const MachineInstr* const &LHS,
998 const MachineInstr* const &RHS) {
999 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1000 LHS == getEmptyKey() || LHS == getTombstoneKey())
1002 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1006 //===----------------------------------------------------------------------===//
1007 // Debugging Support
1009 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1014 } // End llvm namespace