1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
23 class TargetInstrDesc;
26 template <typename T> struct ilist_traits;
27 template <typename T> struct ilist;
29 //===----------------------------------------------------------------------===//
30 /// MachineInstr - Representation of each machine instruction.
33 const TargetInstrDesc *TID; // Instruction descriptor.
34 unsigned short NumImplicitOps; // Number of implicit operands (which
35 // are determined at construction time).
37 std::vector<MachineOperand> Operands; // the operands
38 MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
39 MachineBasicBlock *Parent; // Pointer to the owning basic block.
41 // OperandComplete - Return true if it's illegal to add a new operand
42 bool OperandsComplete() const;
44 MachineInstr(const MachineInstr&);
45 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
47 // Intrusive list support
48 friend struct ilist_traits<MachineInstr>;
49 friend struct ilist_traits<MachineBasicBlock>;
50 void setParent(MachineBasicBlock *P) { Parent = P; }
52 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
53 /// TID NULL and no operands.
56 /// MachineInstr ctor - This constructor create a MachineInstr and add the
57 /// implicit operands. It reserves space for number of operands specified by
59 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
61 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
62 /// the MachineInstr is created and added to the end of the specified basic
65 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
69 const MachineBasicBlock* getParent() const { return Parent; }
70 MachineBasicBlock* getParent() { return Parent; }
72 /// getDesc - Returns the target instruction descriptor of this
74 const TargetInstrDesc &getDesc() const { return *TID; }
76 /// getOpcode - Returns the opcode of this MachineInstr.
78 int getOpcode() const;
80 /// Access to explicit operands of the instruction.
82 unsigned getNumOperands() const { return Operands.size(); }
84 const MachineOperand& getOperand(unsigned i) const {
85 assert(i < getNumOperands() && "getOperand() out of range!");
88 MachineOperand& getOperand(unsigned i) {
89 assert(i < getNumOperands() && "getOperand() out of range!");
93 /// getNumExplicitOperands - Returns the number of non-implicit operands.
95 unsigned getNumExplicitOperands() const;
97 /// isIdenticalTo - Return true if this instruction is identical to (same
98 /// opcode and same operands as) the specified instruction.
99 bool isIdenticalTo(const MachineInstr *Other) const {
100 if (Other->getOpcode() != getOpcode() ||
101 Other->getNumOperands() != getNumOperands())
103 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
104 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
109 /// clone - Create a copy of 'this' instruction that is identical in
110 /// all ways except the the instruction has no parent, prev, or next.
111 MachineInstr* clone() const { return new MachineInstr(*this); }
113 /// removeFromParent - This method unlinks 'this' from the containing basic
114 /// block, and returns it, but does not delete it.
115 MachineInstr *removeFromParent();
117 /// eraseFromParent - This method unlinks 'this' from the containing basic
118 /// block and deletes it.
119 void eraseFromParent() {
120 delete removeFromParent();
123 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
125 bool isDebugLabel() const;
127 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
128 /// the specific register or -1 if it is not found. It further tightening
129 /// the search criteria to a use that kills the register if isKill is true.
130 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false) const;
132 /// findRegisterDefOperand() - Returns the MachineOperand that is a def of
133 /// the specific register or NULL if it is not found.
134 MachineOperand *findRegisterDefOperand(unsigned Reg);
136 /// findFirstPredOperandIdx() - Find the index of the first operand in the
137 /// operand list that is used to represent the predicate. It returns -1 if
139 int findFirstPredOperandIdx() const;
141 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
142 /// to two addr elimination.
143 bool isRegReDefinedByTwoAddr(unsigned Reg) const;
145 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
147 void copyKillDeadInfo(const MachineInstr *MI);
149 /// copyPredicates - Copies predicate operand(s) from MI.
150 void copyPredicates(const MachineInstr *MI);
152 /// addRegisterKilled - We have determined MI kills a register. Look for the
153 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
154 /// add a implicit operand if it's not found. Returns true if the operand
155 /// exists / is added.
156 bool addRegisterKilled(unsigned IncomingReg, const MRegisterInfo *RegInfo,
157 bool AddIfNotFound = false);
159 /// addRegisterDead - We have determined MI defined a register without a use.
160 /// Look for the operand that defines it and mark it as IsDead. If
161 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
162 /// true if the operand exists / is added.
163 bool addRegisterDead(unsigned IncomingReg, const MRegisterInfo *RegInfo,
164 bool AddIfNotFound = false);
166 /// copyKillDeadInfo - copies killed/dead information from one instr to another
167 void copyKillDeadInfo(MachineInstr *OldMI,
168 const MRegisterInfo *RegInfo);
173 void print(std::ostream *OS, const TargetMachine *TM) const {
174 if (OS) print(*OS, TM);
176 void print(std::ostream &OS, const TargetMachine *TM = 0) const;
177 void print(std::ostream *OS) const { if (OS) print(*OS); }
180 //===--------------------------------------------------------------------===//
181 // Accessors used to build up machine instructions.
183 /// addOperand - Add the specified operand to the instruction. If it is an
184 /// implicit operand, it is added to the end of the operand list. If it is
185 /// an explicit operand it is added at the end of the explicit operand list
186 /// (before the first implicit operand).
187 void addOperand(const MachineOperand &Op);
189 /// setDesc - Replace the instruction descriptor (thus opcode) of
190 /// the current instruction with a new one.
192 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
194 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
195 /// fewer operand than it started with.
197 void RemoveOperand(unsigned i);
200 /// getRegInfo - If this instruction is embedded into a MachineFunction,
201 /// return the MachineRegisterInfo object for the current function, otherwise
203 MachineRegisterInfo *getRegInfo();
205 /// addImplicitDefUseOperands - Add all implicit def and use operands to
206 /// this instruction.
207 void addImplicitDefUseOperands();
209 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
210 /// this instruction from their respective use lists. This requires that the
211 /// operands already be on their use lists.
212 void RemoveRegOperandsFromUseLists();
214 /// AddRegOperandsToUseLists - Add all of the register operands in
215 /// this instruction from their respective use lists. This requires that the
216 /// operands not be on their use lists yet.
217 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
220 //===----------------------------------------------------------------------===//
223 inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
228 } // End llvm namespace