1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/DenseMapInfo.h"
28 #include "llvm/InlineAsm.h"
29 #include "llvm/Support/DebugLoc.h"
34 template <typename T> class SmallVectorImpl;
36 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
39 class MachineFunction;
40 class MachineMemOperand;
42 //===----------------------------------------------------------------------===//
43 /// MachineInstr - Representation of each machine instruction.
45 class MachineInstr : public ilist_node<MachineInstr> {
47 typedef MachineMemOperand **mmo_iterator;
49 /// Flags to specify different kinds of comments to output in
50 /// assembly code. These flags carry semantic information not
51 /// otherwise easily derivable from the IR text.
59 FrameSetup = 1 << 0, // Instruction is used as a part of
60 // function frame setup code.
61 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
62 // the first MI in a bundle)
65 const MCInstrDesc *MCID; // Instruction descriptor.
67 uint8_t Flags; // Various bits of additional
68 // information about machine
71 uint8_t AsmPrinterFlags; // Various bits of information used by
72 // the AsmPrinter to emit helpful
73 // comments. This is *not* semantic
74 // information. Do not use this for
75 // anything other than to convey comment
76 // information to AsmPrinter.
78 uint16_t NumMemRefs; // information on memory references
81 std::vector<MachineOperand> Operands; // the operands
82 MachineBasicBlock *Parent; // Pointer to the owning basic block.
83 DebugLoc debugLoc; // Source line information.
85 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
86 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
88 // Intrusive list support
89 friend struct ilist_traits<MachineInstr>;
90 friend struct ilist_traits<MachineBasicBlock>;
91 void setParent(MachineBasicBlock *P) { Parent = P; }
93 /// MachineInstr ctor - This constructor creates a copy of the given
94 /// MachineInstr in the given MachineFunction.
95 MachineInstr(MachineFunction &, const MachineInstr &);
97 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
98 /// MCID NULL and no operands.
101 /// MachineInstr ctor - This constructor create a MachineInstr and add the
102 /// implicit operands. It reserves space for number of operands specified by
103 /// MCInstrDesc. An explicit DebugLoc is supplied.
104 MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = false);
106 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
107 /// the MachineInstr is created and added to the end of the specified basic
109 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
110 const MCInstrDesc &MCID);
114 // MachineInstrs are pool-allocated and owned by MachineFunction.
115 friend class MachineFunction;
118 const MachineBasicBlock* getParent() const { return Parent; }
119 MachineBasicBlock* getParent() { return Parent; }
121 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
123 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
125 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
127 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
129 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
131 bool getAsmPrinterFlag(CommentFlag Flag) const {
132 return AsmPrinterFlags & Flag;
135 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
137 void setAsmPrinterFlag(CommentFlag Flag) {
138 AsmPrinterFlags |= (uint8_t)Flag;
141 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
143 void clearAsmPrinterFlag(CommentFlag Flag) {
144 AsmPrinterFlags &= ~Flag;
147 /// getFlags - Return the MI flags bitvector.
148 uint8_t getFlags() const {
152 /// getFlag - Return whether an MI flag is set.
153 bool getFlag(MIFlag Flag) const {
157 /// setFlag - Set a MI flag.
158 void setFlag(MIFlag Flag) {
159 Flags |= (uint8_t)Flag;
162 void setFlags(unsigned flags) {
166 /// clearFlag - Clear a MI flag.
167 void clearFlag(MIFlag Flag) {
168 Flags &= ~((uint8_t)Flag);
171 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
174 /// A bundle looks like this before it's finalized:
186 /// In this case, the first MI starts a bundle but is not inside a bundle, the
187 /// next 2 MIs are considered "inside" the bundle.
189 /// After a bundle is finalized, it looks like this:
205 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
206 /// a bundle, but the next three MIs are.
207 bool isInsideBundle() const {
208 return getFlag(InsideBundle);
211 /// setIsInsideBundle - Set InsideBundle bit.
213 void setIsInsideBundle(bool Val = true) {
215 setFlag(InsideBundle);
217 clearFlag(InsideBundle);
220 /// isBundled - Return true if this instruction part of a bundle. This is true
221 /// if either itself or its following instruction is marked "InsideBundle".
222 bool isBundled() const;
224 /// getDebugLoc - Returns the debug location id of this MachineInstr.
226 DebugLoc getDebugLoc() const { return debugLoc; }
228 /// emitError - Emit an error referring to the source location of this
229 /// instruction. This should only be used for inline assembly that is somehow
230 /// impossible to compile. Other errors should have been handled much
233 /// If this method returns, the caller should try to recover from the error.
235 void emitError(StringRef Msg) const;
237 /// getDesc - Returns the target instruction descriptor of this
239 const MCInstrDesc &getDesc() const { return *MCID; }
241 /// getOpcode - Returns the opcode of this MachineInstr.
243 int getOpcode() const { return MCID->Opcode; }
245 /// Access to explicit operands of the instruction.
247 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
249 const MachineOperand& getOperand(unsigned i) const {
250 assert(i < getNumOperands() && "getOperand() out of range!");
253 MachineOperand& getOperand(unsigned i) {
254 assert(i < getNumOperands() && "getOperand() out of range!");
258 /// getNumExplicitOperands - Returns the number of non-implicit operands.
260 unsigned getNumExplicitOperands() const;
262 /// iterator/begin/end - Iterate over all operands of a machine instruction.
263 typedef std::vector<MachineOperand>::iterator mop_iterator;
264 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
266 mop_iterator operands_begin() { return Operands.begin(); }
267 mop_iterator operands_end() { return Operands.end(); }
269 const_mop_iterator operands_begin() const { return Operands.begin(); }
270 const_mop_iterator operands_end() const { return Operands.end(); }
272 /// Access to memory operands of the instruction
273 mmo_iterator memoperands_begin() const { return MemRefs; }
274 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
275 bool memoperands_empty() const { return NumMemRefs == 0; }
277 /// hasOneMemOperand - Return true if this instruction has exactly one
278 /// MachineMemOperand.
279 bool hasOneMemOperand() const {
280 return NumMemRefs == 1;
283 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
284 /// queries but they are bundle aware.
287 IgnoreBundle, // Ignore bundles
288 AnyInBundle, // Return true if any instruction in bundle has property
289 AllInBundle // Return true if all instructions in bundle have property
292 /// hasProperty - Return true if the instruction (or in the case of a bundle,
293 /// the instructions inside the bundle) has the specified property.
294 /// The first argument is the property being queried.
295 /// The second argument indicates whether the query should look inside
296 /// instruction bundles.
297 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
298 // Inline the fast path.
299 if (Type == IgnoreBundle || !isBundle())
300 return getDesc().getFlags() & (1 << MCFlag);
302 // If we have a bundle, take the slow path.
303 return hasPropertyInBundle(1 << MCFlag, Type);
306 /// isVariadic - Return true if this instruction can have a variable number of
307 /// operands. In this case, the variable operands will be after the normal
308 /// operands but before the implicit definitions and uses (if any are
310 bool isVariadic(QueryType Type = IgnoreBundle) const {
311 return hasProperty(MCID::Variadic, Type);
314 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
315 /// ARM instructions which can set condition code if 's' bit is set.
316 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
317 return hasProperty(MCID::HasOptionalDef, Type);
320 /// isPseudo - Return true if this is a pseudo instruction that doesn't
321 /// correspond to a real machine instruction.
323 bool isPseudo(QueryType Type = IgnoreBundle) const {
324 return hasProperty(MCID::Pseudo, Type);
327 bool isReturn(QueryType Type = AnyInBundle) const {
328 return hasProperty(MCID::Return, Type);
331 bool isCall(QueryType Type = AnyInBundle) const {
332 return hasProperty(MCID::Call, Type);
335 /// isBarrier - Returns true if the specified instruction stops control flow
336 /// from executing the instruction immediately following it. Examples include
337 /// unconditional branches and return instructions.
338 bool isBarrier(QueryType Type = AnyInBundle) const {
339 return hasProperty(MCID::Barrier, Type);
342 /// isTerminator - Returns true if this instruction part of the terminator for
343 /// a basic block. Typically this is things like return and branch
346 /// Various passes use this to insert code into the bottom of a basic block,
347 /// but before control flow occurs.
348 bool isTerminator(QueryType Type = AnyInBundle) const {
349 return hasProperty(MCID::Terminator, Type);
352 /// isBranch - Returns true if this is a conditional, unconditional, or
353 /// indirect branch. Predicates below can be used to discriminate between
354 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
355 /// get more information.
356 bool isBranch(QueryType Type = AnyInBundle) const {
357 return hasProperty(MCID::Branch, Type);
360 /// isIndirectBranch - Return true if this is an indirect branch, such as a
361 /// branch through a register.
362 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
363 return hasProperty(MCID::IndirectBranch, Type);
366 /// isConditionalBranch - Return true if this is a branch which may fall
367 /// through to the next instruction or may transfer control flow to some other
368 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
369 /// information about this branch.
370 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
371 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
374 /// isUnconditionalBranch - Return true if this is a branch which always
375 /// transfers control flow to some other block. The
376 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
377 /// about this branch.
378 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
379 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
382 // isPredicable - Return true if this instruction has a predicate operand that
383 // controls execution. It may be set to 'always', or may be set to other
384 /// values. There are various methods in TargetInstrInfo that can be used to
385 /// control and modify the predicate in this instruction.
386 bool isPredicable(QueryType Type = AllInBundle) const {
387 // If it's a bundle than all bundled instructions must be predicable for this
389 return hasProperty(MCID::Predicable, Type);
392 /// isCompare - Return true if this instruction is a comparison.
393 bool isCompare(QueryType Type = IgnoreBundle) const {
394 return hasProperty(MCID::Compare, Type);
397 /// isMoveImmediate - Return true if this instruction is a move immediate
398 /// (including conditional moves) instruction.
399 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
400 return hasProperty(MCID::MoveImm, Type);
403 /// isBitcast - Return true if this instruction is a bitcast instruction.
405 bool isBitcast(QueryType Type = IgnoreBundle) const {
406 return hasProperty(MCID::Bitcast, Type);
409 /// isSelect - Return true if this instruction is a select instruction.
411 bool isSelect(QueryType Type = IgnoreBundle) const {
412 return hasProperty(MCID::Select, Type);
415 /// isNotDuplicable - Return true if this instruction cannot be safely
416 /// duplicated. For example, if the instruction has a unique labels attached
417 /// to it, duplicating it would cause multiple definition errors.
418 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
419 return hasProperty(MCID::NotDuplicable, Type);
422 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
423 /// which must be filled by the code generator.
424 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
425 return hasProperty(MCID::DelaySlot, Type);
428 /// canFoldAsLoad - Return true for instructions that can be folded as
429 /// memory operands in other instructions. The most common use for this
430 /// is instructions that are simple loads from memory that don't modify
431 /// the loaded value in any way, but it can also be used for instructions
432 /// that can be expressed as constant-pool loads, such as V_SETALLONES
433 /// on x86, to allow them to be folded when it is beneficial.
434 /// This should only be set on instructions that return a value in their
435 /// only virtual register definition.
436 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
437 return hasProperty(MCID::FoldableAsLoad, Type);
440 //===--------------------------------------------------------------------===//
441 // Side Effect Analysis
442 //===--------------------------------------------------------------------===//
444 /// mayLoad - Return true if this instruction could possibly read memory.
445 /// Instructions with this flag set are not necessarily simple load
446 /// instructions, they may load a value and modify it, for example.
447 bool mayLoad(QueryType Type = AnyInBundle) const {
448 return hasProperty(MCID::MayLoad, Type);
452 /// mayStore - Return true if this instruction could possibly modify memory.
453 /// Instructions with this flag set are not necessarily simple store
454 /// instructions, they may store a modified value based on their operands, or
455 /// may not actually modify anything, for example.
456 bool mayStore(QueryType Type = AnyInBundle) const {
457 return hasProperty(MCID::MayStore, Type);
460 //===--------------------------------------------------------------------===//
461 // Flags that indicate whether an instruction can be modified by a method.
462 //===--------------------------------------------------------------------===//
464 /// isCommutable - Return true if this may be a 2- or 3-address
465 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
466 /// result if Y and Z are exchanged. If this flag is set, then the
467 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
470 /// Note that this flag may be set on instructions that are only commutable
471 /// sometimes. In these cases, the call to commuteInstruction will fail.
472 /// Also note that some instructions require non-trivial modification to
474 bool isCommutable(QueryType Type = IgnoreBundle) const {
475 return hasProperty(MCID::Commutable, Type);
478 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
479 /// which can be changed into a 3-address instruction if needed. Doing this
480 /// transformation can be profitable in the register allocator, because it
481 /// means that the instruction can use a 2-address form if possible, but
482 /// degrade into a less efficient form if the source and dest register cannot
483 /// be assigned to the same register. For example, this allows the x86
484 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
485 /// is the same speed as the shift but has bigger code size.
487 /// If this returns true, then the target must implement the
488 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
489 /// is allowed to fail if the transformation isn't valid for this specific
490 /// instruction (e.g. shl reg, 4 on x86).
492 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
493 return hasProperty(MCID::ConvertibleTo3Addr, Type);
496 /// usesCustomInsertionHook - Return true if this instruction requires
497 /// custom insertion support when the DAG scheduler is inserting it into a
498 /// machine basic block. If this is true for the instruction, it basically
499 /// means that it is a pseudo instruction used at SelectionDAG time that is
500 /// expanded out into magic code by the target when MachineInstrs are formed.
502 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
503 /// is used to insert this into the MachineBasicBlock.
504 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
505 return hasProperty(MCID::UsesCustomInserter, Type);
508 /// hasPostISelHook - Return true if this instruction requires *adjustment*
509 /// after instruction selection by calling a target hook. For example, this
510 /// can be used to fill in ARM 's' optional operand depending on whether
511 /// the conditional flag register is used.
512 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
513 return hasProperty(MCID::HasPostISelHook, Type);
516 /// isRematerializable - Returns true if this instruction is a candidate for
517 /// remat. This flag is deprecated, please don't use it anymore. If this
518 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
519 /// verify the instruction is really rematable.
520 bool isRematerializable(QueryType Type = AllInBundle) const {
521 // It's only possible to re-mat a bundle if all bundled instructions are
522 // re-materializable.
523 return hasProperty(MCID::Rematerializable, Type);
526 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
527 /// less) than a move instruction. This is useful during certain types of
528 /// optimizations (e.g., remat during two-address conversion or machine licm)
529 /// where we would like to remat or hoist the instruction, but not if it costs
530 /// more than moving the instruction into the appropriate register. Note, we
531 /// are not marking copies from and to the same register class with this flag.
532 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
533 // Only returns true for a bundle if all bundled instructions are cheap.
534 // FIXME: This probably requires a target hook.
535 return hasProperty(MCID::CheapAsAMove, Type);
538 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
539 /// have special register allocation requirements that are not captured by the
540 /// operand register classes. e.g. ARM::STRD's two source registers must be an
541 /// even / odd pair, ARM::STM registers have to be in ascending order.
542 /// Post-register allocation passes should not attempt to change allocations
543 /// for sources of instructions with this flag.
544 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
545 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
548 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
549 /// have special register allocation requirements that are not captured by the
550 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
551 /// even / odd pair, ARM::LDM registers have to be in ascending order.
552 /// Post-register allocation passes should not attempt to change allocations
553 /// for definitions of instructions with this flag.
554 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
555 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
560 CheckDefs, // Check all operands for equality
561 CheckKillDead, // Check all operands including kill / dead markers
562 IgnoreDefs, // Ignore all definitions
563 IgnoreVRegDefs // Ignore virtual register definitions
566 /// isIdenticalTo - Return true if this instruction is identical to (same
567 /// opcode and same operands as) the specified instruction.
568 bool isIdenticalTo(const MachineInstr *Other,
569 MICheckType Check = CheckDefs) const;
571 /// removeFromParent - This method unlinks 'this' from the containing basic
572 /// block, and returns it, but does not delete it.
573 MachineInstr *removeFromParent();
575 /// eraseFromParent - This method unlinks 'this' from the containing basic
576 /// block and deletes it.
577 void eraseFromParent();
579 /// isLabel - Returns true if the MachineInstr represents a label.
581 bool isLabel() const {
582 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
583 getOpcode() == TargetOpcode::EH_LABEL ||
584 getOpcode() == TargetOpcode::GC_LABEL;
587 bool isPrologLabel() const {
588 return getOpcode() == TargetOpcode::PROLOG_LABEL;
590 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
591 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
592 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
594 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
595 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
596 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
597 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
598 bool isStackAligningInlineAsm() const;
599 InlineAsm::AsmDialect getInlineAsmDialect() const;
600 bool isInsertSubreg() const {
601 return getOpcode() == TargetOpcode::INSERT_SUBREG;
603 bool isSubregToReg() const {
604 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
606 bool isRegSequence() const {
607 return getOpcode() == TargetOpcode::REG_SEQUENCE;
609 bool isBundle() const {
610 return getOpcode() == TargetOpcode::BUNDLE;
612 bool isCopy() const {
613 return getOpcode() == TargetOpcode::COPY;
615 bool isFullCopy() const {
616 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
619 /// isCopyLike - Return true if the instruction behaves like a copy.
620 /// This does not include native copy instructions.
621 bool isCopyLike() const {
622 return isCopy() || isSubregToReg();
625 /// isIdentityCopy - Return true is the instruction is an identity copy.
626 bool isIdentityCopy() const {
627 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
628 getOperand(0).getSubReg() == getOperand(1).getSubReg();
631 /// isTransient - Return true if this is a transient instruction that is
632 /// either very likely to be eliminated during register allocation (such as
633 /// copy-like instructions), or if this instruction doesn't have an
634 /// execution-time cost.
635 bool isTransient() const {
636 switch(getOpcode()) {
637 default: return false;
638 // Copy-like instructions are usually eliminated during register allocation.
639 case TargetOpcode::PHI:
640 case TargetOpcode::COPY:
641 case TargetOpcode::INSERT_SUBREG:
642 case TargetOpcode::SUBREG_TO_REG:
643 case TargetOpcode::REG_SEQUENCE:
644 // Pseudo-instructions that don't produce any real output.
645 case TargetOpcode::IMPLICIT_DEF:
646 case TargetOpcode::KILL:
647 case TargetOpcode::PROLOG_LABEL:
648 case TargetOpcode::EH_LABEL:
649 case TargetOpcode::GC_LABEL:
650 case TargetOpcode::DBG_VALUE:
655 /// getBundleSize - Return the number of instructions inside the MI bundle.
656 unsigned getBundleSize() const;
658 /// readsRegister - Return true if the MachineInstr reads the specified
659 /// register. If TargetRegisterInfo is passed, then it also checks if there
660 /// is a read of a super-register.
661 /// This does not count partial redefines of virtual registers as reads:
663 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
664 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
667 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
668 /// virtual register. Take into account that a partial define is a
669 /// read-modify-write operation.
670 bool readsVirtualRegister(unsigned Reg) const {
671 return readsWritesVirtualRegister(Reg).first;
674 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
675 /// indicating if this instruction reads or writes Reg. This also considers
677 /// If Ops is not null, all operand indices for Reg are added.
678 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
679 SmallVectorImpl<unsigned> *Ops = 0) const;
681 /// killsRegister - Return true if the MachineInstr kills the specified
682 /// register. If TargetRegisterInfo is passed, then it also checks if there is
683 /// a kill of a super-register.
684 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
685 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
688 /// definesRegister - Return true if the MachineInstr fully defines the
689 /// specified register. If TargetRegisterInfo is passed, then it also checks
690 /// if there is a def of a super-register.
691 /// NOTE: It's ignoring subreg indices on virtual registers.
692 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
693 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
696 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
697 /// or partially define) the specified register.
698 /// NOTE: It's ignoring subreg indices on virtual registers.
699 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
700 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
703 /// registerDefIsDead - Returns true if the register is dead in this machine
704 /// instruction. If TargetRegisterInfo is passed, then it also checks
705 /// if there is a dead def of a super-register.
706 bool registerDefIsDead(unsigned Reg,
707 const TargetRegisterInfo *TRI = NULL) const {
708 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
711 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
712 /// the specific register or -1 if it is not found. It further tightens
713 /// the search criteria to a use that kills the register if isKill is true.
714 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
715 const TargetRegisterInfo *TRI = NULL) const;
717 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
718 /// a pointer to the MachineOperand rather than an index.
719 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
720 const TargetRegisterInfo *TRI = NULL) {
721 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
722 return (Idx == -1) ? NULL : &getOperand(Idx);
725 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
726 /// the specified register or -1 if it is not found. If isDead is true, defs
727 /// that are not dead are skipped. If Overlap is true, then it also looks for
728 /// defs that merely overlap the specified register. If TargetRegisterInfo is
729 /// non-null, then it also checks if there is a def of a super-register.
730 /// This may also return a register mask operand when Overlap is true.
731 int findRegisterDefOperandIdx(unsigned Reg,
732 bool isDead = false, bool Overlap = false,
733 const TargetRegisterInfo *TRI = NULL) const;
735 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
736 /// a pointer to the MachineOperand rather than an index.
737 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
738 const TargetRegisterInfo *TRI = NULL) {
739 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
740 return (Idx == -1) ? NULL : &getOperand(Idx);
743 /// findFirstPredOperandIdx() - Find the index of the first operand in the
744 /// operand list that is used to represent the predicate. It returns -1 if
746 int findFirstPredOperandIdx() const;
748 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
749 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
750 /// getOperand(OpIdx) does not belong to an inline asm operand group.
752 /// If GroupNo is not NULL, it will receive the number of the operand group
753 /// containing OpIdx.
755 /// The flag operand is an immediate that can be decoded with methods like
756 /// InlineAsm::hasRegClassConstraint().
758 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
760 /// getRegClassConstraint - Compute the static register class constraint for
761 /// operand OpIdx. For normal instructions, this is derived from the
762 /// MCInstrDesc. For inline assembly it is derived from the flag words.
764 /// Returns NULL if the static register classs constraint cannot be
767 const TargetRegisterClass*
768 getRegClassConstraint(unsigned OpIdx,
769 const TargetInstrInfo *TII,
770 const TargetRegisterInfo *TRI) const;
772 /// tieOperands - Add a tie between the register operands at DefIdx and
773 /// UseIdx. The tie will cause the register allocator to ensure that the two
774 /// operands are assigned the same physical register.
776 /// Tied operands are managed automatically for explicit operands in the
777 /// MCInstrDesc. This method is for exceptional cases like inline asm.
778 void tieOperands(unsigned DefIdx, unsigned UseIdx);
780 /// findTiedOperandIdx - Given the index of a tied register operand, find the
781 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
782 /// index of the tied operand which must exist.
783 unsigned findTiedOperandIdx(unsigned OpIdx) const;
785 /// isRegTiedToUseOperand - Given the index of a register def operand,
786 /// check if the register def is tied to a source operand, due to either
787 /// two-address elimination or inline assembly constraints. Returns the
788 /// first tied use operand index by reference if UseOpIdx is not null.
789 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
790 const MachineOperand &MO = getOperand(DefOpIdx);
791 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
794 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
798 /// isRegTiedToDefOperand - Return true if the use operand of the specified
799 /// index is tied to an def operand. It also returns the def operand index by
800 /// reference if DefOpIdx is not null.
801 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
802 const MachineOperand &MO = getOperand(UseOpIdx);
803 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
806 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
810 /// clearKillInfo - Clears kill flags on all operands.
812 void clearKillInfo();
814 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
816 void copyKillDeadInfo(const MachineInstr *MI);
818 /// copyPredicates - Copies predicate operand(s) from MI.
819 void copyPredicates(const MachineInstr *MI);
821 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
822 /// properly composing subreg indices where necessary.
823 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
824 const TargetRegisterInfo &RegInfo);
826 /// addRegisterKilled - We have determined MI kills a register. Look for the
827 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
828 /// add a implicit operand if it's not found. Returns true if the operand
829 /// exists / is added.
830 bool addRegisterKilled(unsigned IncomingReg,
831 const TargetRegisterInfo *RegInfo,
832 bool AddIfNotFound = false);
834 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
835 /// provided, this includes super-register kills.
836 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
838 /// addRegisterDead - We have determined MI defined a register without a use.
839 /// Look for the operand that defines it and mark it as IsDead. If
840 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
841 /// true if the operand exists / is added.
842 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
843 bool AddIfNotFound = false);
845 /// addRegisterDefined - We have determined MI defines a register. Make sure
846 /// there is an operand defining Reg.
847 void addRegisterDefined(unsigned IncomingReg,
848 const TargetRegisterInfo *RegInfo = 0);
850 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
851 /// dead except those in the UsedRegs list.
853 /// On instructions with register mask operands, also add implicit-def
854 /// operands for all registers in UsedRegs.
855 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
856 const TargetRegisterInfo &TRI);
858 /// isSafeToMove - Return true if it is safe to move this instruction. If
859 /// SawStore is set to true, it means that there is a store (or call) between
860 /// the instruction's location and its intended destination.
861 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
862 bool &SawStore) const;
864 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
865 /// instruction which defined the specified register instead of copying it.
866 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
867 unsigned DstReg) const;
869 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
870 /// or volatile memory reference, or if the information describing the memory
871 /// reference is not available. Return false if it is known to have no
872 /// ordered or volatile memory references.
873 bool hasOrderedMemoryRef() const;
875 /// isInvariantLoad - Return true if this instruction is loading from a
876 /// location whose value is invariant across the function. For example,
877 /// loading a value from the constant pool or from the argument area of
878 /// a function if it does not change. This should only return true of *all*
879 /// loads the instruction does are invariant (if it does multiple loads).
880 bool isInvariantLoad(AliasAnalysis *AA) const;
882 /// isConstantValuePHI - If the specified instruction is a PHI that always
883 /// merges together the same virtual register, return the register, otherwise
885 unsigned isConstantValuePHI() const;
887 /// hasUnmodeledSideEffects - Return true if this instruction has side
888 /// effects that are not modeled by mayLoad / mayStore, etc.
889 /// For all instructions, the property is encoded in MCInstrDesc::Flags
890 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
891 /// INLINEASM instruction, in which case the side effect property is encoded
892 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
894 bool hasUnmodeledSideEffects() const;
896 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
898 bool allDefsAreDead() const;
900 /// copyImplicitOps - Copy implicit register operands from specified
901 /// instruction to this instruction.
902 void copyImplicitOps(const MachineInstr *MI);
907 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
910 //===--------------------------------------------------------------------===//
911 // Accessors used to build up machine instructions.
913 /// addOperand - Add the specified operand to the instruction. If it is an
914 /// implicit operand, it is added to the end of the operand list. If it is
915 /// an explicit operand it is added at the end of the explicit operand list
916 /// (before the first implicit operand).
917 void addOperand(const MachineOperand &Op);
919 /// setDesc - Replace the instruction descriptor (thus opcode) of
920 /// the current instruction with a new one.
922 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
924 /// setDebugLoc - Replace current source information with new such.
925 /// Avoid using this, the constructor argument is preferable.
927 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
929 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
930 /// fewer operand than it started with.
932 void RemoveOperand(unsigned i);
934 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
935 /// This function should be used only occasionally. The setMemRefs function
936 /// is the primary method for setting up a MachineInstr's MemRefs list.
937 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
939 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
940 /// list. This does not transfer ownership.
941 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
942 MemRefs = NewMemRefs;
943 NumMemRefs = NewMemRefsEnd - NewMemRefs;
947 /// getRegInfo - If this instruction is embedded into a MachineFunction,
948 /// return the MachineRegisterInfo object for the current function, otherwise
950 MachineRegisterInfo *getRegInfo();
952 /// untieRegOperand - Break any tie involving OpIdx.
953 void untieRegOperand(unsigned OpIdx) {
954 MachineOperand &MO = getOperand(OpIdx);
955 if (MO.isReg() && MO.isTied()) {
956 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
961 /// addImplicitDefUseOperands - Add all implicit def and use operands to
962 /// this instruction.
963 void addImplicitDefUseOperands();
965 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
966 /// this instruction from their respective use lists. This requires that the
967 /// operands already be on their use lists.
968 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
970 /// AddRegOperandsToUseLists - Add all of the register operands in
971 /// this instruction from their respective use lists. This requires that the
972 /// operands not be on their use lists yet.
973 void AddRegOperandsToUseLists(MachineRegisterInfo&);
975 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
977 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
980 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
981 /// MachineInstr* by *value* of the instruction rather than by pointer value.
982 /// The hashing and equality testing functions ignore definitions so this is
983 /// useful for CSE, etc.
984 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
985 static inline MachineInstr *getEmptyKey() {
989 static inline MachineInstr *getTombstoneKey() {
990 return reinterpret_cast<MachineInstr*>(-1);
993 static unsigned getHashValue(const MachineInstr* const &MI);
995 static bool isEqual(const MachineInstr* const &LHS,
996 const MachineInstr* const &RHS) {
997 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
998 LHS == getEmptyKey() || LHS == getTombstoneKey())
1000 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1004 //===----------------------------------------------------------------------===//
1005 // Debugging Support
1007 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1012 } // End llvm namespace