1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 class MachineFunction;
38 class MachineMemOperand;
40 //===----------------------------------------------------------------------===//
41 /// MachineInstr - Representation of each machine instruction.
43 class MachineInstr : public ilist_node<MachineInstr> {
45 typedef MachineMemOperand **mmo_iterator;
47 /// Flags to specify different kinds of comments to output in
48 /// assembly code. These flags carry semantic information not
49 /// otherwise easily derivable from the IR text.
57 FrameSetup = 1 << 0 // Instruction is used as a part of
58 // function frame setup code.
61 const MCInstrDesc *MCID; // Instruction descriptor.
63 uint8_t Flags; // Various bits of additional
64 // information about machine
67 uint8_t AsmPrinterFlags; // Various bits of information used by
68 // the AsmPrinter to emit helpful
69 // comments. This is *not* semantic
70 // information. Do not use this for
71 // anything other than to convey comment
72 // information to AsmPrinter.
74 std::vector<MachineOperand> Operands; // the operands
75 mmo_iterator MemRefs; // information on memory references
76 mmo_iterator MemRefsEnd;
77 MachineBasicBlock *Parent; // Pointer to the owning basic block.
78 DebugLoc debugLoc; // Source line information.
80 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
81 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
83 // Intrusive list support
84 friend struct ilist_traits<MachineInstr>;
85 friend struct ilist_traits<MachineBasicBlock>;
86 void setParent(MachineBasicBlock *P) { Parent = P; }
88 /// MachineInstr ctor - This constructor creates a copy of the given
89 /// MachineInstr in the given MachineFunction.
90 MachineInstr(MachineFunction &, const MachineInstr &);
92 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
93 /// MCID NULL and no operands.
96 // The next two constructors have DebugLoc and non-DebugLoc versions;
97 // over time, the non-DebugLoc versions should be phased out and eventually
100 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
101 /// implicit operands. It reserves space for the number of operands specified
102 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
103 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
105 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
106 /// the MachineInstr is created and added to the end of the specified basic
107 /// block. The version with a DebugLoc should be preferred.
108 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
116 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
117 /// the MachineInstr is created and added to the end of the specified basic
119 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
120 const MCInstrDesc &MCID);
124 // MachineInstrs are pool-allocated and owned by MachineFunction.
125 friend class MachineFunction;
128 const MachineBasicBlock* getParent() const { return Parent; }
129 MachineBasicBlock* getParent() { return Parent; }
131 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
133 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
135 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
137 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
139 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
141 bool getAsmPrinterFlag(CommentFlag Flag) const {
142 return AsmPrinterFlags & Flag;
145 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
147 void setAsmPrinterFlag(CommentFlag Flag) {
148 AsmPrinterFlags |= (uint8_t)Flag;
151 /// getFlags - Return the MI flags bitvector.
152 uint8_t getFlags() const {
156 /// getFlag - Return whether an MI flag is set.
157 bool getFlag(MIFlag Flag) const {
161 /// setFlag - Set a MI flag.
162 void setFlag(MIFlag Flag) {
163 Flags |= (uint8_t)Flag;
166 void setFlags(unsigned flags) {
170 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
172 void clearAsmPrinterFlag(CommentFlag Flag) {
173 AsmPrinterFlags &= ~Flag;
176 /// getDebugLoc - Returns the debug location id of this MachineInstr.
178 DebugLoc getDebugLoc() const { return debugLoc; }
180 /// emitError - Emit an error referring to the source location of this
181 /// instruction. This should only be used for inline assembly that is somehow
182 /// impossible to compile. Other errors should have been handled much
185 /// If this method returns, the caller should try to recover from the error.
187 void emitError(StringRef Msg) const;
189 /// getDesc - Returns the target instruction descriptor of this
191 const MCInstrDesc &getDesc() const { return *MCID; }
193 /// getOpcode - Returns the opcode of this MachineInstr.
195 int getOpcode() const { return MCID->Opcode; }
197 /// Access to explicit operands of the instruction.
199 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
201 const MachineOperand& getOperand(unsigned i) const {
202 assert(i < getNumOperands() && "getOperand() out of range!");
205 MachineOperand& getOperand(unsigned i) {
206 assert(i < getNumOperands() && "getOperand() out of range!");
210 /// getNumExplicitOperands - Returns the number of non-implicit operands.
212 unsigned getNumExplicitOperands() const;
214 /// iterator/begin/end - Iterate over all operands of a machine instruction.
215 typedef std::vector<MachineOperand>::iterator mop_iterator;
216 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
218 mop_iterator operands_begin() { return Operands.begin(); }
219 mop_iterator operands_end() { return Operands.end(); }
221 const_mop_iterator operands_begin() const { return Operands.begin(); }
222 const_mop_iterator operands_end() const { return Operands.end(); }
224 /// Access to memory operands of the instruction
225 mmo_iterator memoperands_begin() const { return MemRefs; }
226 mmo_iterator memoperands_end() const { return MemRefsEnd; }
227 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
229 /// hasOneMemOperand - Return true if this instruction has exactly one
230 /// MachineMemOperand.
231 bool hasOneMemOperand() const {
232 return MemRefsEnd - MemRefs == 1;
236 CheckDefs, // Check all operands for equality
237 CheckKillDead, // Check all operands including kill / dead markers
238 IgnoreDefs, // Ignore all definitions
239 IgnoreVRegDefs // Ignore virtual register definitions
242 /// isIdenticalTo - Return true if this instruction is identical to (same
243 /// opcode and same operands as) the specified instruction.
244 bool isIdenticalTo(const MachineInstr *Other,
245 MICheckType Check = CheckDefs) const;
247 /// removeFromParent - This method unlinks 'this' from the containing basic
248 /// block, and returns it, but does not delete it.
249 MachineInstr *removeFromParent();
251 /// eraseFromParent - This method unlinks 'this' from the containing basic
252 /// block and deletes it.
253 void eraseFromParent();
255 /// isLabel - Returns true if the MachineInstr represents a label.
257 bool isLabel() const {
258 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
259 getOpcode() == TargetOpcode::EH_LABEL ||
260 getOpcode() == TargetOpcode::GC_LABEL;
263 bool isPrologLabel() const {
264 return getOpcode() == TargetOpcode::PROLOG_LABEL;
266 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
267 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
268 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
270 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
271 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
272 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
273 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
274 bool isStackAligningInlineAsm() const;
275 bool isInsertSubreg() const {
276 return getOpcode() == TargetOpcode::INSERT_SUBREG;
278 bool isSubregToReg() const {
279 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
281 bool isRegSequence() const {
282 return getOpcode() == TargetOpcode::REG_SEQUENCE;
284 bool isCopy() const {
285 return getOpcode() == TargetOpcode::COPY;
287 bool isFullCopy() const {
288 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
291 /// isCopyLike - Return true if the instruction behaves like a copy.
292 /// This does not include native copy instructions.
293 bool isCopyLike() const {
294 return isCopy() || isSubregToReg();
297 /// isIdentityCopy - Return true is the instruction is an identity copy.
298 bool isIdentityCopy() const {
299 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
300 getOperand(0).getSubReg() == getOperand(1).getSubReg();
303 /// readsRegister - Return true if the MachineInstr reads the specified
304 /// register. If TargetRegisterInfo is passed, then it also checks if there
305 /// is a read of a super-register.
306 /// This does not count partial redefines of virtual registers as reads:
308 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
309 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
312 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
313 /// virtual register. Take into account that a partial define is a
314 /// read-modify-write operation.
315 bool readsVirtualRegister(unsigned Reg) const {
316 return readsWritesVirtualRegister(Reg).first;
319 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
320 /// indicating if this instruction reads or writes Reg. This also considers
322 /// If Ops is not null, all operand indices for Reg are added.
323 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
324 SmallVectorImpl<unsigned> *Ops = 0) const;
326 /// killsRegister - Return true if the MachineInstr kills the specified
327 /// register. If TargetRegisterInfo is passed, then it also checks if there is
328 /// a kill of a super-register.
329 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
330 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
333 /// definesRegister - Return true if the MachineInstr fully defines the
334 /// specified register. If TargetRegisterInfo is passed, then it also checks
335 /// if there is a def of a super-register.
336 /// NOTE: It's ignoring subreg indices on virtual registers.
337 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
338 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
341 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
342 /// or partially define) the specified register.
343 /// NOTE: It's ignoring subreg indices on virtual registers.
344 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
345 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
348 /// registerDefIsDead - Returns true if the register is dead in this machine
349 /// instruction. If TargetRegisterInfo is passed, then it also checks
350 /// if there is a dead def of a super-register.
351 bool registerDefIsDead(unsigned Reg,
352 const TargetRegisterInfo *TRI = NULL) const {
353 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
356 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
357 /// the specific register or -1 if it is not found. It further tightens
358 /// the search criteria to a use that kills the register if isKill is true.
359 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
360 const TargetRegisterInfo *TRI = NULL) const;
362 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
363 /// a pointer to the MachineOperand rather than an index.
364 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
365 const TargetRegisterInfo *TRI = NULL) {
366 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
367 return (Idx == -1) ? NULL : &getOperand(Idx);
370 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
371 /// the specified register or -1 if it is not found. If isDead is true, defs
372 /// that are not dead are skipped. If Overlap is true, then it also looks for
373 /// defs that merely overlap the specified register. If TargetRegisterInfo is
374 /// non-null, then it also checks if there is a def of a super-register.
375 int findRegisterDefOperandIdx(unsigned Reg,
376 bool isDead = false, bool Overlap = false,
377 const TargetRegisterInfo *TRI = NULL) const;
379 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
380 /// a pointer to the MachineOperand rather than an index.
381 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
382 const TargetRegisterInfo *TRI = NULL) {
383 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
384 return (Idx == -1) ? NULL : &getOperand(Idx);
387 /// findFirstPredOperandIdx() - Find the index of the first operand in the
388 /// operand list that is used to represent the predicate. It returns -1 if
390 int findFirstPredOperandIdx() const;
392 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
393 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
394 /// getOperand(OpIdx) does not belong to an inline asm operand group.
396 /// If GroupNo is not NULL, it will receive the number of the operand group
397 /// containing OpIdx.
399 /// The flag operand is an immediate that can be decoded with methods like
400 /// InlineAsm::hasRegClassConstraint().
402 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
404 /// getRegClassConstraint - Compute the static register class constraint for
405 /// operand OpIdx. For normal instructions, this is derived from the
406 /// MCInstrDesc. For inline assembly it is derived from the flag words.
408 /// Returns NULL if the static register classs constraint cannot be
411 const TargetRegisterClass*
412 getRegClassConstraint(unsigned OpIdx,
413 const TargetInstrInfo *TII,
414 const TargetRegisterInfo *TRI) const;
416 /// isRegTiedToUseOperand - Given the index of a register def operand,
417 /// check if the register def is tied to a source operand, due to either
418 /// two-address elimination or inline assembly constraints. Returns the
419 /// first tied use operand index by reference is UseOpIdx is not null.
420 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
422 /// isRegTiedToDefOperand - Return true if the use operand of the specified
423 /// index is tied to an def operand. It also returns the def operand index by
424 /// reference if DefOpIdx is not null.
425 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
427 /// clearKillInfo - Clears kill flags on all operands.
429 void clearKillInfo();
431 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
433 void copyKillDeadInfo(const MachineInstr *MI);
435 /// copyPredicates - Copies predicate operand(s) from MI.
436 void copyPredicates(const MachineInstr *MI);
438 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
439 /// properly composing subreg indices where necessary.
440 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
441 const TargetRegisterInfo &RegInfo);
443 /// addRegisterKilled - We have determined MI kills a register. Look for the
444 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
445 /// add a implicit operand if it's not found. Returns true if the operand
446 /// exists / is added.
447 bool addRegisterKilled(unsigned IncomingReg,
448 const TargetRegisterInfo *RegInfo,
449 bool AddIfNotFound = false);
451 /// addRegisterDead - We have determined MI defined a register without a use.
452 /// Look for the operand that defines it and mark it as IsDead. If
453 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
454 /// true if the operand exists / is added.
455 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
456 bool AddIfNotFound = false);
458 /// addRegisterDefined - We have determined MI defines a register. Make sure
459 /// there is an operand defining Reg.
460 void addRegisterDefined(unsigned IncomingReg,
461 const TargetRegisterInfo *RegInfo = 0);
463 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
464 /// dead except those in the UsedRegs list.
465 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
466 const TargetRegisterInfo &TRI);
468 /// isSafeToMove - Return true if it is safe to move this instruction. If
469 /// SawStore is set to true, it means that there is a store (or call) between
470 /// the instruction's location and its intended destination.
471 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
472 bool &SawStore) const;
474 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
475 /// instruction which defined the specified register instead of copying it.
476 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
477 unsigned DstReg) const;
479 /// hasVolatileMemoryRef - Return true if this instruction may have a
480 /// volatile memory reference, or if the information describing the
481 /// memory reference is not available. Return false if it is known to
482 /// have no volatile memory references.
483 bool hasVolatileMemoryRef() const;
485 /// isInvariantLoad - Return true if this instruction is loading from a
486 /// location whose value is invariant across the function. For example,
487 /// loading a value from the constant pool or from the argument area of
488 /// a function if it does not change. This should only return true of *all*
489 /// loads the instruction does are invariant (if it does multiple loads).
490 bool isInvariantLoad(AliasAnalysis *AA) const;
492 /// isConstantValuePHI - If the specified instruction is a PHI that always
493 /// merges together the same virtual register, return the register, otherwise
495 unsigned isConstantValuePHI() const;
497 /// hasUnmodeledSideEffects - Return true if this instruction has side
498 /// effects that are not modeled by mayLoad / mayStore, etc.
499 /// For all instructions, the property is encoded in MCInstrDesc::Flags
500 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
501 /// INLINEASM instruction, in which case the side effect property is encoded
502 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
504 bool hasUnmodeledSideEffects() const;
506 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
508 bool allDefsAreDead() const;
510 /// copyImplicitOps - Copy implicit register operands from specified
511 /// instruction to this instruction.
512 void copyImplicitOps(const MachineInstr *MI);
517 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
520 //===--------------------------------------------------------------------===//
521 // Accessors used to build up machine instructions.
523 /// addOperand - Add the specified operand to the instruction. If it is an
524 /// implicit operand, it is added to the end of the operand list. If it is
525 /// an explicit operand it is added at the end of the explicit operand list
526 /// (before the first implicit operand).
527 void addOperand(const MachineOperand &Op);
529 /// setDesc - Replace the instruction descriptor (thus opcode) of
530 /// the current instruction with a new one.
532 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
534 /// setDebugLoc - Replace current source information with new such.
535 /// Avoid using this, the constructor argument is preferable.
537 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
539 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
540 /// fewer operand than it started with.
542 void RemoveOperand(unsigned i);
544 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
545 /// This function should be used only occasionally. The setMemRefs function
546 /// is the primary method for setting up a MachineInstr's MemRefs list.
547 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
549 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
550 /// list. This does not transfer ownership.
551 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
552 MemRefs = NewMemRefs;
553 MemRefsEnd = NewMemRefsEnd;
557 /// getRegInfo - If this instruction is embedded into a MachineFunction,
558 /// return the MachineRegisterInfo object for the current function, otherwise
560 MachineRegisterInfo *getRegInfo();
562 /// addImplicitDefUseOperands - Add all implicit def and use operands to
563 /// this instruction.
564 void addImplicitDefUseOperands();
566 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
567 /// this instruction from their respective use lists. This requires that the
568 /// operands already be on their use lists.
569 void RemoveRegOperandsFromUseLists();
571 /// AddRegOperandsToUseLists - Add all of the register operands in
572 /// this instruction from their respective use lists. This requires that the
573 /// operands not be on their use lists yet.
574 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
577 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
578 /// MachineInstr* by *value* of the instruction rather than by pointer value.
579 /// The hashing and equality testing functions ignore definitions so this is
580 /// useful for CSE, etc.
581 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
582 static inline MachineInstr *getEmptyKey() {
586 static inline MachineInstr *getTombstoneKey() {
587 return reinterpret_cast<MachineInstr*>(-1);
590 static unsigned getHashValue(const MachineInstr* const &MI);
592 static bool isEqual(const MachineInstr* const &LHS,
593 const MachineInstr* const &RHS) {
594 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
595 LHS == getEmptyKey() || LHS == getTombstoneKey())
597 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
601 //===----------------------------------------------------------------------===//
604 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
609 } // End llvm namespace