1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
56 FrameSetup = 1 << 0 // Instruction is used as a part of
57 // function frame setup code.
60 const TargetInstrDesc *TID; // Instruction descriptor.
61 uint16_t NumImplicitOps; // Number of implicit operands (which
62 // are determined at construction time).
64 uint8_t Flags; // Various bits of additional
65 // information about machine
68 uint8_t AsmPrinterFlags; // Various bits of information used by
69 // the AsmPrinter to emit helpful
70 // comments. This is *not* semantic
71 // information. Do not use this for
72 // anything other than to convey comment
73 // information to AsmPrinter.
75 std::vector<MachineOperand> Operands; // the operands
76 mmo_iterator MemRefs; // information on memory references
77 mmo_iterator MemRefsEnd;
78 MachineBasicBlock *Parent; // Pointer to the owning basic block.
79 DebugLoc debugLoc; // Source line information.
81 // OperandComplete - Return true if it's illegal to add a new operand
82 bool OperandsComplete() const;
84 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
85 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
87 // Intrusive list support
88 friend struct ilist_traits<MachineInstr>;
89 friend struct ilist_traits<MachineBasicBlock>;
90 void setParent(MachineBasicBlock *P) { Parent = P; }
92 /// MachineInstr ctor - This constructor creates a copy of the given
93 /// MachineInstr in the given MachineFunction.
94 MachineInstr(MachineFunction &, const MachineInstr &);
96 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
97 /// TID NULL and no operands.
100 // The next two constructors have DebugLoc and non-DebugLoc versions;
101 // over time, the non-DebugLoc versions should be phased out and eventually
104 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
105 /// implicit operands. It reserves space for the number of operands specified
106 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
107 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
109 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
110 /// the MachineInstr is created and added to the end of the specified basic
111 /// block. The version with a DebugLoc should be preferred.
112 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
114 /// MachineInstr ctor - This constructor create a MachineInstr and add the
115 /// implicit operands. It reserves space for number of operands specified by
116 /// TargetInstrDesc. An explicit DebugLoc is supplied.
117 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
120 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
121 /// the MachineInstr is created and added to the end of the specified basic
123 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
124 const TargetInstrDesc &TID);
128 // MachineInstrs are pool-allocated and owned by MachineFunction.
129 friend class MachineFunction;
132 const MachineBasicBlock* getParent() const { return Parent; }
133 MachineBasicBlock* getParent() { return Parent; }
135 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
137 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
139 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
141 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
143 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
145 bool getAsmPrinterFlag(CommentFlag Flag) const {
146 return AsmPrinterFlags & Flag;
149 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
151 void setAsmPrinterFlag(CommentFlag Flag) {
152 AsmPrinterFlags |= (uint8_t)Flag;
155 /// getFlags - Return the MI flags bitvector.
156 uint8_t getFlags() const {
160 /// getFlag - Return whether an MI flag is set.
161 bool getFlag(MIFlag Flag) const {
165 /// setFlag - Set a MI flag.
166 void setFlag(MIFlag Flag) {
167 Flags |= (uint8_t)Flag;
170 void setFlags(unsigned flags) {
174 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
176 void clearAsmPrinterFlag(CommentFlag Flag) {
177 AsmPrinterFlags &= ~Flag;
180 /// getDebugLoc - Returns the debug location id of this MachineInstr.
182 DebugLoc getDebugLoc() const { return debugLoc; }
184 /// getDesc - Returns the target instruction descriptor of this
186 const TargetInstrDesc &getDesc() const { return *TID; }
188 /// getOpcode - Returns the opcode of this MachineInstr.
190 int getOpcode() const { return TID->Opcode; }
192 /// Access to explicit operands of the instruction.
194 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
196 const MachineOperand& getOperand(unsigned i) const {
197 assert(i < getNumOperands() && "getOperand() out of range!");
200 MachineOperand& getOperand(unsigned i) {
201 assert(i < getNumOperands() && "getOperand() out of range!");
205 /// getNumExplicitOperands - Returns the number of non-implicit operands.
207 unsigned getNumExplicitOperands() const;
209 /// iterator/begin/end - Iterate over all operands of a machine instruction.
210 typedef std::vector<MachineOperand>::iterator mop_iterator;
211 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
213 mop_iterator operands_begin() { return Operands.begin(); }
214 mop_iterator operands_end() { return Operands.end(); }
216 const_mop_iterator operands_begin() const { return Operands.begin(); }
217 const_mop_iterator operands_end() const { return Operands.end(); }
219 /// Access to memory operands of the instruction
220 mmo_iterator memoperands_begin() const { return MemRefs; }
221 mmo_iterator memoperands_end() const { return MemRefsEnd; }
222 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
224 /// hasOneMemOperand - Return true if this instruction has exactly one
225 /// MachineMemOperand.
226 bool hasOneMemOperand() const {
227 return MemRefsEnd - MemRefs == 1;
231 CheckDefs, // Check all operands for equality
232 CheckKillDead, // Check all operands including kill / dead markers
233 IgnoreDefs, // Ignore all definitions
234 IgnoreVRegDefs // Ignore virtual register definitions
237 /// isIdenticalTo - Return true if this instruction is identical to (same
238 /// opcode and same operands as) the specified instruction.
239 bool isIdenticalTo(const MachineInstr *Other,
240 MICheckType Check = CheckDefs) const;
242 /// removeFromParent - This method unlinks 'this' from the containing basic
243 /// block, and returns it, but does not delete it.
244 MachineInstr *removeFromParent();
246 /// eraseFromParent - This method unlinks 'this' from the containing basic
247 /// block and deletes it.
248 void eraseFromParent();
250 /// isLabel - Returns true if the MachineInstr represents a label.
252 bool isLabel() const {
253 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
254 getOpcode() == TargetOpcode::EH_LABEL ||
255 getOpcode() == TargetOpcode::GC_LABEL;
258 bool isPrologLabel() const {
259 return getOpcode() == TargetOpcode::PROLOG_LABEL;
261 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
262 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
263 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
265 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
266 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
267 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
268 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
269 bool isStackAligningInlineAsm() const;
270 bool isInsertSubreg() const {
271 return getOpcode() == TargetOpcode::INSERT_SUBREG;
273 bool isSubregToReg() const {
274 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
276 bool isRegSequence() const {
277 return getOpcode() == TargetOpcode::REG_SEQUENCE;
279 bool isCopy() const {
280 return getOpcode() == TargetOpcode::COPY;
283 /// isCopyLike - Return true if the instruction behaves like a copy.
284 /// This does not include native copy instructions.
285 bool isCopyLike() const {
286 return isCopy() || isSubregToReg();
289 /// isIdentityCopy - Return true is the instruction is an identity copy.
290 bool isIdentityCopy() const {
291 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
292 getOperand(0).getSubReg() == getOperand(1).getSubReg();
295 /// readsRegister - Return true if the MachineInstr reads the specified
296 /// register. If TargetRegisterInfo is passed, then it also checks if there
297 /// is a read of a super-register.
298 /// This does not count partial redefines of virtual registers as reads:
300 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
301 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
304 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
305 /// virtual register. Take into account that a partial define is a
306 /// read-modify-write operation.
307 bool readsVirtualRegister(unsigned Reg) const {
308 return readsWritesVirtualRegister(Reg).first;
311 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
312 /// indicating if this instruction reads or writes Reg. This also considers
314 /// If Ops is not null, all operand indices for Reg are added.
315 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
316 SmallVectorImpl<unsigned> *Ops = 0) const;
318 /// killsRegister - Return true if the MachineInstr kills the specified
319 /// register. If TargetRegisterInfo is passed, then it also checks if there is
320 /// a kill of a super-register.
321 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
322 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
325 /// definesRegister - Return true if the MachineInstr fully defines the
326 /// specified register. If TargetRegisterInfo is passed, then it also checks
327 /// if there is a def of a super-register.
328 /// NOTE: It's ignoring subreg indices on virtual registers.
329 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
330 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
333 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
334 /// or partially define) the specified register.
335 /// NOTE: It's ignoring subreg indices on virtual registers.
336 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
337 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
340 /// registerDefIsDead - Returns true if the register is dead in this machine
341 /// instruction. If TargetRegisterInfo is passed, then it also checks
342 /// if there is a dead def of a super-register.
343 bool registerDefIsDead(unsigned Reg,
344 const TargetRegisterInfo *TRI = NULL) const {
345 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
348 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
349 /// the specific register or -1 if it is not found. It further tightens
350 /// the search criteria to a use that kills the register if isKill is true.
351 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
352 const TargetRegisterInfo *TRI = NULL) const;
354 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
355 /// a pointer to the MachineOperand rather than an index.
356 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
357 const TargetRegisterInfo *TRI = NULL) {
358 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
359 return (Idx == -1) ? NULL : &getOperand(Idx);
362 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
363 /// the specified register or -1 if it is not found. If isDead is true, defs
364 /// that are not dead are skipped. If Overlap is true, then it also looks for
365 /// defs that merely overlap the specified register. If TargetRegisterInfo is
366 /// non-null, then it also checks if there is a def of a super-register.
367 int findRegisterDefOperandIdx(unsigned Reg,
368 bool isDead = false, bool Overlap = false,
369 const TargetRegisterInfo *TRI = NULL) const;
371 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
372 /// a pointer to the MachineOperand rather than an index.
373 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
374 const TargetRegisterInfo *TRI = NULL) {
375 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
376 return (Idx == -1) ? NULL : &getOperand(Idx);
379 /// findFirstPredOperandIdx() - Find the index of the first operand in the
380 /// operand list that is used to represent the predicate. It returns -1 if
382 int findFirstPredOperandIdx() const;
384 /// isRegTiedToUseOperand - Given the index of a register def operand,
385 /// check if the register def is tied to a source operand, due to either
386 /// two-address elimination or inline assembly constraints. Returns the
387 /// first tied use operand index by reference is UseOpIdx is not null.
388 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
390 /// isRegTiedToDefOperand - Return true if the use operand of the specified
391 /// index is tied to an def operand. It also returns the def operand index by
392 /// reference if DefOpIdx is not null.
393 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
395 /// clearKillInfo - Clears kill flags on all operands.
397 void clearKillInfo();
399 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
401 void copyKillDeadInfo(const MachineInstr *MI);
403 /// copyPredicates - Copies predicate operand(s) from MI.
404 void copyPredicates(const MachineInstr *MI);
406 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
407 /// properly composing subreg indices where necessary.
408 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
409 const TargetRegisterInfo &RegInfo);
411 /// addRegisterKilled - We have determined MI kills a register. Look for the
412 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
413 /// add a implicit operand if it's not found. Returns true if the operand
414 /// exists / is added.
415 bool addRegisterKilled(unsigned IncomingReg,
416 const TargetRegisterInfo *RegInfo,
417 bool AddIfNotFound = false);
419 /// addRegisterDead - We have determined MI defined a register without a use.
420 /// Look for the operand that defines it and mark it as IsDead. If
421 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
422 /// true if the operand exists / is added.
423 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
424 bool AddIfNotFound = false);
426 /// addRegisterDefined - We have determined MI defines a register. Make sure
427 /// there is an operand defining Reg.
428 void addRegisterDefined(unsigned IncomingReg,
429 const TargetRegisterInfo *RegInfo = 0);
431 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
432 /// dead except those in the UsedRegs list.
433 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
434 const TargetRegisterInfo &TRI);
436 /// isSafeToMove - Return true if it is safe to move this instruction. If
437 /// SawStore is set to true, it means that there is a store (or call) between
438 /// the instruction's location and its intended destination.
439 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
440 bool &SawStore) const;
442 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
443 /// instruction which defined the specified register instead of copying it.
444 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
445 unsigned DstReg) const;
447 /// hasVolatileMemoryRef - Return true if this instruction may have a
448 /// volatile memory reference, or if the information describing the
449 /// memory reference is not available. Return false if it is known to
450 /// have no volatile memory references.
451 bool hasVolatileMemoryRef() const;
453 /// isInvariantLoad - Return true if this instruction is loading from a
454 /// location whose value is invariant across the function. For example,
455 /// loading a value from the constant pool or from the argument area of
456 /// a function if it does not change. This should only return true of *all*
457 /// loads the instruction does are invariant (if it does multiple loads).
458 bool isInvariantLoad(AliasAnalysis *AA) const;
460 /// isConstantValuePHI - If the specified instruction is a PHI that always
461 /// merges together the same virtual register, return the register, otherwise
463 unsigned isConstantValuePHI() const;
465 /// hasUnmodeledSideEffects - Return true if this instruction has side
466 /// effects that are not modeled by mayLoad / mayStore, etc.
467 /// For all instructions, the property is encoded in TargetInstrDesc::Flags
468 /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is
469 /// INLINEASM instruction, in which case the side effect property is encoded
470 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
472 bool hasUnmodeledSideEffects() const;
474 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
476 bool allDefsAreDead() const;
478 /// copyImplicitOps - Copy implicit register operands from specified
479 /// instruction to this instruction.
480 void copyImplicitOps(const MachineInstr *MI);
485 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
488 //===--------------------------------------------------------------------===//
489 // Accessors used to build up machine instructions.
491 /// addOperand - Add the specified operand to the instruction. If it is an
492 /// implicit operand, it is added to the end of the operand list. If it is
493 /// an explicit operand it is added at the end of the explicit operand list
494 /// (before the first implicit operand).
495 void addOperand(const MachineOperand &Op);
497 /// setDesc - Replace the instruction descriptor (thus opcode) of
498 /// the current instruction with a new one.
500 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
502 /// setDebugLoc - Replace current source information with new such.
503 /// Avoid using this, the constructor argument is preferable.
505 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
507 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
508 /// fewer operand than it started with.
510 void RemoveOperand(unsigned i);
512 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
513 /// This function should be used only occasionally. The setMemRefs function
514 /// is the primary method for setting up a MachineInstr's MemRefs list.
515 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
517 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
518 /// list. This does not transfer ownership.
519 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
520 MemRefs = NewMemRefs;
521 MemRefsEnd = NewMemRefsEnd;
525 /// getRegInfo - If this instruction is embedded into a MachineFunction,
526 /// return the MachineRegisterInfo object for the current function, otherwise
528 MachineRegisterInfo *getRegInfo();
530 /// addImplicitDefUseOperands - Add all implicit def and use operands to
531 /// this instruction.
532 void addImplicitDefUseOperands();
534 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
535 /// this instruction from their respective use lists. This requires that the
536 /// operands already be on their use lists.
537 void RemoveRegOperandsFromUseLists();
539 /// AddRegOperandsToUseLists - Add all of the register operands in
540 /// this instruction from their respective use lists. This requires that the
541 /// operands not be on their use lists yet.
542 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
545 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
546 /// MachineInstr* by *value* of the instruction rather than by pointer value.
547 /// The hashing and equality testing functions ignore definitions so this is
548 /// useful for CSE, etc.
549 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
550 static inline MachineInstr *getEmptyKey() {
554 static inline MachineInstr *getTombstoneKey() {
555 return reinterpret_cast<MachineInstr*>(-1);
558 static unsigned getHashValue(const MachineInstr* const &MI);
560 static bool isEqual(const MachineInstr* const &LHS,
561 const MachineInstr* const &RHS) {
562 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
563 LHS == getEmptyKey() || LHS == getTombstoneKey())
565 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
569 //===----------------------------------------------------------------------===//
572 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
577 } // End llvm namespace